Features • E2 Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store Configuration Programs For Field Programmable Gate Arrays (FPGA) • Simple Interface to SRAM FPGAs • Compatible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K, • • • • • • • • EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola MPA1000 FPGAs Cascadable To Support Additional Configurations or Future Higher-density Arrays Low-power CMOS EEPROM Process Programmable Reset Polarity Available In PLCC Package (Pin Compatable across Product Family) In-System Programmable Via 2-Wire Bus Emulation of 24CXX Serial EPROMs Available in 3.3V ± 10% LV and 5V Versions System Friendly READY Pin Description The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The high-density AT17 Series is packaged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The high-density AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. The user can select the polarity of the reset function by programming one EEPROM byte. The devices also support a write protection mode and a system friendly READY pin, which signifies a “good” power level to the device and can be used to ensure reliable system power-up. The high-density AT17 Series can be programmed with industry-standard programmers, and the Atmel ATDH2200 Programming board. FPGA Configuration E2PROM Memory 512K and 1M AT17C512 AT17LV512 AT17C010 AT17LV010 Pin Configurations 20-Pin PLCC N C D A T A N C V C C 3 2 1 20 N C CLK 4 19 18 WP1 5 17 SER_EN RESET/OE 6 16 NC WP2 7 15 R E A DY CE 8 9 10 11 12 N C G N D N C N C 14 13 NC CEO N C Rev. 0944A-A–12/97 1 Controlling The High-Density AT17 Series Serial EEPROMs Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory: • The DATA output of the high-density AT17 Series drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the high-density AT17 Series. • The CEO output of any AT17C/LV512/010 drives the CE input of the next AT17C/LV512/010 in a cascade chain of PROMs. • SER_EN must be connected to VCC, (except during ISP). READY is available as an open-collector indicator of the device’s RESET status; it is driven Low while the device is in its POWER-ON RESET cycle and released (tri-stated) when the cycle is complete. There are two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms. Condition 1 The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to Block Diagram 2 AT17C/LV512/010 its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configuration cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the high-density AT17 Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle. Condition 2 The FPGA D/P output drives only the CE input of the highdensity AT17 Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone High. A High lev el on the RES ET/OE inpu t to the AT17C/LVxxx – during FPGA reset – clears the Configurator’s internal address pointer, so that the reconfiguration starts at the beginning. The high-density AT17 Series does not require an inverter since the RESET polarity is programmable. AT17C/LV512/010 Pin Configurations 20 PLCC Name I/O Description 2 DATA I/O Three-state DATA output for reading. Input/Output pin for programming. 4 CLK I Clock input. Used to increment the internal address and bit counter for reading and programming. 5 WP1 I WRITE PROTECT (1). Used to protect portions of memory during programming. See programming guide for details. 6 RESET/OE I RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the address and bit counters. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE. 7 WP2 I WRITE PROTECT (2). Used to protect portions of memory during programming. See programming guide for details. 8 CE I Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial Programming mode (i.e., when SER_EN is Low). 10 GND 14 CEO O Chip Enable Out output. This signal is asserted Low on the clock cycle following the last bit read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until OE goes High. Thereafter, CEO will stay High until the entire PROM is read again and senses the status of RESET polarity. A2 I Device selection input, A2. This is used to enable (or select) the device during programming, when SER_EN is Low (see Programming Guide for more details) 15 READY O Open collector reset state indicator. Driven Low during power-up reset, released when powerup is complete. (Recommend a 4.7KΩ Pull-up on this pin if used). 17 SER_EN I Serial enable is normally high during FPGA loading operations. Bringing SER_EN Low, enables the two wire serial interface mode for programming. 20 VCC Ground pin. +3.3V/+5V power supply pin. Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ............................ -0.1V to VCC + 0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Maximum Soldering Temp. (10 s @ 1/16 in.)..................260°C ESD (RZAP = 1.5K, CZAP = 100 pF)............................... 2000V 3 FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. After configuration is complete, the address counters of all cascaded Configurators are reset if the reset signal drives the RESET/OE on each Configurator to its active (High) level. If the address counters are not to be reset upon completion, then the RESET/OE inputs can be tied to ground. For more details, please reference the AT17C Series Programming Guide. Programming Mode Cascading Serial Configuration EEPROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory. As the last bit from the first Configurator is read, the clock signal to the Configurator asserts its CEO output Low and disables its DATA line. The second Configurator recognizes the Low level on its CE input and enables its DATA output. Figure 1. Condition 1 Connection The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2wire interface. The programming is done at V CC supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel's Configuration Memories Application Note for further information. The AT17C Series parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal. AT17C/LVXXX Reset Polarity The AT17C/LVXXX lets the user choose the reset polarity as either RESET/OE or RESET/OE. Standby Mode The AT17C/LVXXX enters a low-power standby mode whenever CE is asserted High. In this mode, the Configurator consumes less than 0.5mA at 5.0 volts. The output remains in a high impedance state regardless of the state of the OE input. Operating Conditions Symbol VCC 4 Description AT17CXXX AT17LVXXX Min/Max Min/Max Units Commercial Supply voltage relative to GND -0°C to +70°C 4.75 / 5.25 3.0 / 3.6 V Industrial Supply voltage relative to GND -40°C to +85°C 4.5 / 5.5 3.0 / 3.6 V Military Supply voltage relative to GND -55°C to +125°C 4.5 / 5.5 3.0 / 3.6 V AT17C/LV512/010 AT17C/LV512/010 DC Characteristics VCC = 5V ± 5% Commercial / 5V ± 10% Ind./Mil. Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) 0.4 V ICCA Supply current, active mode (at FMAX) 10 mA IL Input or output leakage current (VIN = VCC or GND) 10 µA Commercial 0.5 mA ICCS Supply current, standby mode Industrial/Military 0.5 mA 3.86 V Commercial 0.32 3.76 V V Industrial 0.37 3.7 V V Military -10 DC Characteristics VCC = 3.3V ± 10% Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -2.5 mA) VOL Low-level output voltage (IOL = +3 mA) VOH High-level output voltage (IOH = -2 mA) VOL Low-level output voltage (IOL = +3 mA) VOH High-level output voltage (IOH = -2 mA) VOL Low-level output voltage (IOL = +2.5 mA) ICCA Supply current, active mode IL Input or output leakage current (VIN = VCC or GND) ICCS Supply current, standby mode 2.4 V Commercial 0.4 2.4 V V Industrial 0.4 2.4 V V Military 0.4 V 5 mA 10 µA Commercial 100 µA Industrial/Military 100 µA -10 5 AC Characteristics AC Characteristics When Cascading 6 AT17C/LV512/010 AT17C/LV512/010 . AC Characteristics for AT17C512/010 VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil Commercial/Industrial Symbol Description Max Units 30 35 ns CE to Data Delay 45 45 ns CLK to Data Delay 50 50 ns (2) OE to Data Delay TCE(2) TCAC(2) TOE (2) Data Hold From CE, OE, or CLK (3) CE or OE to Data Float Delay TOH TDF Min Max Military 0 Min 0 ns 50 50 ns TLC CLK Low Time 20 20 ns THC CLK High Time 20 20 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 20 25 ns THCE CE Hold Time to CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (Guarantees Counter Is Reset) 20 20 ns FMAX MAX Input Clock Frequency 15 15 MHz VRDY Ready Pin Open Collector Voltage 1.2 2.2 1.2 2.2 V Max Units AC Characteristics for AT17C512/010 When Cascading VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil. Commercial/Industrial Symbol TCDF (3) Description Min Max Military Min CLK to Data Float Delay 50 50 ns TOCK(2) CLK to CEO Delay 35 40 ns TOCE(2) CE to CEO Delay 35 35 ns 30 30 ns (2) TOOE RESET/OE to CEO Delay Notes: 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. 7 AC Characteristics for AT17LV512/010 VCC = 3.3V ± 10% Commercial/Industrial Military Symbol Description TOE(2) OE to Data Delay TCE(2) TCAC(2) TOH Data Hold From CE, OE, or CLK TDF(3) CE or OE to Data Float Delay TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 30 35 ns THCE CE Hold Time to CLK (to guarantee proper counting) 0 0 ns OE High Time (Guarantees Counter Is Reset) 25 25 ns MAX Input Clock Frequency 15 10 MHz THOE FMAX (4) VRDY Notes: Max Units 50 55 ns CE to Data Delay 55 60 ns CLK to Data Delay 55 60 ns Min Max 0 Min 0 ns 50 Ready Pin Open Collector Voltage 1. Preliminary specifications for military operating range only. 1.2 2.2 50 1.2 2.2 ns V 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. 4. During cascade FMAX = 12.5 MHz. AC Characteristics for AT17LV512/010 When Cascading VCC = 3.3V ± 10% Commercial/Industrial Symbol Max Units 50 50 ns CLK to CEO Delay 50 55 ns TOCE(2) CE to CEO Delay 35 40 ns TOOE(2) RESET/OE to CEO Delay 35 35 ns TCDF (3) CLK to Data Float Delay (2) TOCK 8 Description AT17C/LV512/010 Min Max Military Min AT17C/LV512/010 Ordering Information - 5V Devices Memory Size Ordering Code Package 512K AT17C512-10JC 20J Commercial (0°C to 70°C) AT17C512-10JI 20J Industrial (-40°C to 85°C) AT17C010-10JC 20J Commercial (0°C to 70°C) AT17C010-10JI 20J Industrial (-40°C to 85°C) 1M Operation Range Ordering Information - 3.3V Devices Memory Size 512K 1M Ordering Code Package Operation Range AT17LV512-10JC 20J Commercial (0°C to 70°C) AT17LV512-10JI 20J Industrial (-40°C to 85°C) AT17LV010-10JC 20J Commercial (0°C to 70°C) AT17LV010-10JI 20J Industrial (-40°C to 85°C) Package Type 20J 20 Lead, Plastic J-Leaded Chip Carrier (PLCC) 9