Intersil ISL80102IR15Z High performance 2a and 3a ldo Datasheet

ISL80102, ISL80103
Features
The ISL80102 and ISL80103 are low voltage,
high-current, single output LDOs specified for 2A and 3A
output current, respectively. These parts operate from
input voltages of 2.2V to 6V and are capable of providing
output voltages of 0.8V to 5V on the adjustable VOUT
versions. Fixed output voltage options available in 0.8V,
1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5V. Other custom
voltage options available upon request.
• 0.5% initial VOUT Accuracy
For applications that demand in-rush current less than
current limit, an external capacitor on the in-rush set pin
provides adjustment. The ENABLE feature allows the part
to be placed into a low quiescent current shutdown
mode. Sub-micron CMOS process is utilized for this
product family to deliver the best in class analog
performance and overall value.
• Adjustable In-Rush Current Limiting
These CMOS LDOs will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable a leading
class fast load transient response, and hence a lower
total AC regulation band for an LDO in this category.
• 900mV Enable Input Threshold
Pin Configuration
ISL80102, ISL80103
(10 LD 3X3 DFN)
TOP VIEW
• Designed for 2.2V to 6V Input Supply
• ±1.8% Guaranteed VOUT Accuracy for Junction
Temperature Range from -40°C to +125°C
• 185mV Dropout @ 3A, 125mV Dropout @ 2A
• Fast Load Transient Response
• Rated Output Current Options of 2A and 3A
• Fixed and Adjustable VOUT Options Available
• 65dB Typical PSRR
• Output Noise of 100µVRMS between 300Hz to
300kHz
• PG Feature
• Short-Circuit Current Protection
• 1A Peak Reverse Current
• Over-Temperature Shutdown
• Any Cap Stable with Minimum 10µF Ceramic
• Available in a 10 Ld DFN Package and soon to follow
TO220-5, TO263-5 and SOT223-5 (1A and 2A
versions)
• Pb-Free (RoHS Compliant)
Applications*(see page 15)
• DSP, FPGA and µP Core Power Supplies
VOUT
1
10 VIN
VOUT
2
9 VIN
• Post Regulation of Switched Mode Power Supplies
SENSE/ADJ
3
8 DNC
• Industrial Systems
PG
4
7 ENABLE
• Medical Equipment
GND
5
6 SS
• Telecommunications and Networking Equipment
• Noise-Sensitive Instrumentation Systems
• Servers
• Hard Disk Drives (HD/HDD)
September 30, 2009
FN6660.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL80102, ISL80103
High Performance 2A and 3A LDOs
ISL80102, ISL80103
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
VOUT
3
SENSE/ADJ
Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set
VOUT.
4
PG
VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be
grounded if not used.
5
GND
6
SS
7
ENABLE
8
DNC
Do not connect this pin to ground or supply. Leave floating.
9, 10
VIN
Input supply pin.
Output voltage pin.
GND pin.
External cap controls in-rush current.
EPAD
VIN independent chip enable. TTL and CMOS compatible.
Must be soldered directly to GND plane
Block Diagram
VIN
R4
M5
10µA 10µA
IL/10,000
M4
M1
POWER PMOS
IL
M3
VOUT
+
R8
R7
LEVEL
SHIFT
-
R9
EN
EN
R1
SNS
+
500mV
R2
R4
EN
ADJ
+
EN
EN
M7
-
+
500mV V TO I
SS
+
+
485mV
-
PG
M2
R3
GND
2
FN6660.0
September 30, 2009
ISL80102, ISL80103
Typical Applications
9
2.5V ± 10%
10µF
10
V OUT
VIN
V OUT
VIN
SENSE/ADJ
10k
1
1.8V ± 1.8%
2
10µF
3
100k
ISL80102
ISL80103
7
6
ENABLE
PG
4
SS
(*Note 12)
GND
5
FIXED
FIGURE 1.
9
2.5V ± 10%
10µF
10
VIN
VOUT
ISL80102
ISL80103
VIN
VOUT
1
2
1.8V ± 1.8%
10µF
2.6k
100k
10k
SE NSE/ADJ
1k
7
6
(*NOTE 12)
ENABLE
PG
4
SS
GND
5
ADJUSTABLE
FIGURE 2.
3
FN6660.0
September 30, 2009
ISL80102, ISL80103
Ordering Information
PART
MARKING
VOUT VOLTAGE
(Note 4)
TEMP. RANGE
(°C)
ISL80102IRAJZ
(Notes 1, 3)
DZJA
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR08Z
(Notes 1, 3)
DZKA
0.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR12Z
(Notes 1, 3)
DZLA
1.2V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR15Z
(Notes 1, 3)
DZMA
1.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR18Z
(Notes 1, 3)
DZNA
1.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR25Z
(Notes 1, 3)
DZPA
2.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR33Z
(Notes 1, 3)
DZRA
3.3V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR50Z
(Notes 1, 3)
DZSA
5.0V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IRAJZ
(Notes 1, 3)
DZAA
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR08Z
(Notes 1, 3)
DZBA
0.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR12Z
(Notes 1, 3)
DZCA
1.2V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR15Z
(Note 3)
DZDA
1.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR15Z-T
(Notes 2, 3)
DZDA
1.5V
-40 to +125
10 Ld 3x3 DFN
Tape and Reel
L10.3x3
ISL80103IR18Z
(Notes 1, 3)
DZEA
1.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR25Z
(Notes 1, 3)
DZFA
2.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR33Z
(Note 3)
DZGA
3.3V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR33Z-T
(Notes 2, 3)
DZGA
3.3V
-40 to +125
10 Ld 3x3 DFN
Tape and Reel
L10.3x3
ISL80103IR50Z
(Note 3)
DZHA
5.0V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR50Z-T
(Notes 2, 3)
DZHA
5.0V
-40 to +125
10 Ld 3x3 DFN
Tape and Reel
L10.3x3
PART NUMBER
PACKAGE
(Pb-Free)
PKG
DWG. #
NOTES:
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For other output voltages, contact Intersil Marketing.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on
MSL please see techbrief TB363.
4
FN6660.0
September 30, 2009
ISL80102, ISL80103
Absolute Maximum Ratings (Note 8)
Thermal Information
VIN relative to GND . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VOUT relative to GND . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS
Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
Recommended Operating Conditions
Junction Temperature Range (TJ) . .
VIN relative to GND . . . . . . . . . . . .
VOUT range . . . . . . . . . . . . . . . . . .
PG, ENABLE, SENSE/ADJ, SS relative
PG sink current . . . . . . . . . . . . . . .
θJA (°C/W) θJC (°C/W)
10 Ld 3x3 DFN Package (Notes 6, 7)
45
4
Maximum Junction Temperature (Plastic Package). . . +150°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
. . . . . -40°C to +125°C
. . . . . . . . . 2.2V to 6V
. . . . . . . . 800mV to 5V
to GND . . . . . 0V to 6V
. . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are established over the following specified
conditions: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Application Section” on page 7 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse
load techniques used by ATE to ensure TJ = TA defines established limits.
SYMBOL
TEST CONDITIONS
MIN
(Note 9) TYP
MAX
(Note 9) UNITS
DC CHARACTERISTICS
DC Output Voltage
Accuracy
VOUT
VOUT Options: 0.8V, 1.2V, 1.5V and 1.8V
2.2V < VIN < 3.6V; 0A < ILOAD < 3A
-1.8
0.5
1.8
%
VOUT + 0.4V < VIN < 6V; 0A < ILOAD < 3A
-1.8
0.5
-1.8
%
2.2V < VIN < 6V, 0A < ILOAD < 3A
491
500
509
mV
0.1
0.4
%
0.1
0.8
%
VOUT Options: 2.5V, 3.3V and 5.0V
Feedback Pin (ADJ option
only)
DC Input Line Regulation
VFB
ΔVOUT/ΔVIN VOUT + 0.4V < VIN < 3.6V, VOUT = 1.8V
VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
DC Output Load Regulation ΔVOUT/ΔIOU 0A < ILOAD < 3A, All voltage options
T
0A < ILOAD < 2A, All voltage options
VADJ = 0.5V
Feedback Input Current
Ground Pin Current
IQ
Ground Pin Current in
Shutdown
ISHDN
Dropout Voltage (Note 10)
VDO
Output Short Circuit
Current (3A Version)
ISC
Output Short Circuit
Current (2A Version)
Thermal Shutdown
Temperature
TSD
5
-0.8
%
-0.6
%
0.01
1
µA
ILOAD = 0A, 2.2V < VIN < 6V
7.5
9
mA
ILOAD = 3A, 2.2V < VIN < 6V
8.5
12
mA
ENABLE Pin = 0.2V, VIN = 5V
0.4
ENABLE Pin = 0.2V, VIN = 6V
3.3
16
µA
ILOAD = 3A, VOUT = 2.5V
120
185
mV
ILOAD = 2A, VOUT = 2.5V
81
125
mV
VOUT = 0V, VOUT + 0.4V < VIN < 6V
5.0
A
VOUT = 0V, VOUT + 0.4V < VIN < 6V
2.8
A
VOUT + 0.4V < VIN < 6V
160
°C
µA
FN6660.0
September 30, 2009
ISL80102, ISL80103
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are established over the following specified
conditions: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Application Section” on page 7 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse
load techniques used by ATE to ensure TJ = TA defines established limits. (Continued)
SYMBOL
Thermal Shutdown
Hysteresis (Rising
Threshold)
TEST CONDITIONS
MIN
(Note 9) TYP
MAX
(Note 9) UNITS
TSDn
VOUT + 0.4V < VIN < 6V
15
°C
PSRR
f = 1kHz, ILOAD = 1A; VIN = 2.2V
55
dB
AC CHARACTERISTICS
Input Supply Ripple
Rejection
f = 120Hz, ILOAD = 1A; VIN = 2.2V
62
ILOAD = 10mA, BW = 300Hz < f < 300kHz
Output Noise Voltage
100
µVRMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
2.2V < VIN < 6V
0.3
0.8
0.95
Hysteresis (rising
threshold)
Must be independent of VIN, 2.2V < VIN < 6V
135
mV
Enable Pin Turn-on Delay
COUT = 10µF, ILOAD = 1A
150
µs
Enable Pin Leakage Current
VIN = 6V, EN = 3V
1
V
µA
SOFT START CHARACTERISTICS
In-rush Current Limit
Adjust
323
RPD
ICHG
Ω
-7
-4.5
-2
µA
75
84
92
%VOUT
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold
VOUT PG Flag Hysteresis
4
PG Flag Low Voltage
ISINK = 500µA
PG Flag Leakage Current
VIN = 6V, PG = 6V
%
47
100
mV
0.05
1
µA
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
10. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal
value.
11. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
lifetime average current.
12. Minimum cap on VIN and VOUT required for stability.
13. Used when large bulk capacitance required on VOUT for application.
6
FN6660.0
September 30, 2009
ISL80102, ISL80103
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs
is optimized for a true 2.5V to 1.8V conversion where the
input supply can have a tolerance of as much as ±10%
for conditions noted in the “Electrical Specifications” table
on page 5. Minimum guaranteed input voltage is 2.2V.
However, due to the nature of an LDO, VIN must be some
margin higher than the output voltage plus dropout at
the maximum rated current of the application if active
filtering (PSRR) is expected from VIN to VOUT. The
Dropout spec of this family of LDOs has been generously
specified in order to allow applications to design for a
level of efficiency that can accommodate the smaller
outline package for those applications that cannot
accommodate the profile of the TO220/263.
External Capacitor Requirements
GENERAL GUIDELINE
External capacitors are required for proper operation.
Careful attention must be paid to layout guidelines and
selection of capacitor type and value to ensure optimal
performance.
OUTPUT CAPACITOR
The required minimum output capacitor is 10µF X5R/X7R
to ensure stable operation. Lower cost Y5V and Z5U type
ceramic capacitors are acceptable if the size of the
capacitor is larger to compensate for the significantly
lower tolerance over X5R/X7R types (approximately 2x).
Additional capacitors of any value in Ceramic, POSCAP or
Alum/Tantalum Electrolytic types may be placed in
parallel to improve PSRR at higher frequencies and/or
load transient AC output voltage tolerances. This
minimum capacitor must be connected to VOUT and
Ground pins of the LDO with PCB traces no longer than
0.5cm.
INPUT CAPACITOR
The minimum input capacitor required for proper
operation is 10µF having a ceramic dielectric. This
minimum capacitor must be connected to VOUT and
Ground pins of the LDO with PCB traces no longer than
0.5cm.
Thermal Fault Protection
In the event the die temperature exceeds typically
+160°C, then the output of the LDO will shut down until
the die temperature can cool down to typically +145°C.
The level of power combined with the thermal impedance
of the package (+50°C/W for DFN) will determine if the
junction temperature exceeds the thermal shutdown
temperature specified in the “Electrical Specifications”
table on page 5 (see thermal packaging guidelines).
Current Limit Protection
The ISL80102/3 family of LDOs incorporates protection
against overcurrent due to any short or overload
condition applied to the output pin. The current limit
7
circuit performs as a constant current source when the
output current exceeds the current limit threshold noted
in the “Electrical Specifications” table on page 5. If the
short or overload condition is removed from VOUT, then
the output returns to normal voltage mode regulation. In
the event of an overload condition on the DFN package
the LDO will begin to cycle on and off due to the die
temperature exceeding thermal fault condition. The
TO220/263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if
the heatsink of this larger package can keep the die
temperature below the specified typical thermal
shutdown temperature.
Functional Description
Enable Operation
The Enable turn-on threshold is typically 770mV with a
hysteresis of 135mV. The Enable pin doesn't have an
internal pull-up or pull-down resistor. As a result, this pin
must not be left floating. This pin must be tied to VIN if it
is not used. A 1kΩ to 10kΩ pull-up resistor will be
required for applications that use open collector or open
drain outputs to control the Enable pin. The Enable pin
may be connected directly to VIN for applications that are
always on.
Soft-Start Operation
The soft start circuit controls the rate at which the output
voltage comes up to regulation at power-up or coming
out of a chip disable. A constant current charges an
external soft start capacitor. The external capacitor
always gets discharged to 0V at start-up of after coming
out of a chip disable. The discharge rate is the RC time
constant of RPD and CSS. The soft-start function
effectively limits the amount of in-rush current below the
programmed current limit during start-up or an enable
sequence to avoid an overcurrent fault condition. This
can be an issue for applications that require large,
external bulk capacitances on VOUT where high levels of
charging current can be seen for a significant period of
time. High in-rush currents can cause VIN to drop below
minimum which could cause VOUT to shutdown. Figure 3
shows the relationship between in-rush current and CSS
with a COUT of 1000µF.
5.0
IN-RUSH CURRENT LIMIT (A)
Application Section
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
20
40
60
Css (nF)
80
100
FIGURE 3. IN-RUSH CURRENT vs SOFT-START
CAPACITANCE
FN6660.0
September 30, 2009
ISL80102, ISL80103
Power-Good Operation
The PGOOD circuit monitors VOUT and signals a fault
condition when VOUT is below 84% of the nominal output
voltage. The PGOOD flag is an open-drain NMOS that can
sink 10mA during a fault condition. The PGOOD pin
requires an external pull up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
be pulled up to a voltage source greater than VIN. During
a fault condition, the PGOOD output is pulled low. The
PGOOD fault can be caused by the current limit fault or
low input voltage. The PGOOD does not function during
thermal shutdown and when the part is disabled.
Output Voltage Selection
The maximum allowed junction temperature, TJ(MAX)
and the maximum expected ambient temperature,
TA(MAX) will determine the maximum allowed junction
temperature rise (ΔTJ) as shown in Equation 4:
ΔT J = T J ( MAX ) – T A ( MAX )
(EQ. 4)
To calculate the maximum ambient operating
temperature, use the junction-to-ambient thermal
resistance (θJA) for the DFN package with Equation 5:
P D ( MAX ) = ( T J ( MAX ) – T A ) ⁄ θ JA
(EQ. 5)
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
and 5V. An external resistor divider, R1 and R2, is used to
set the output voltage as shown in Equation 1. The
recommended value for R2 is 500Ω to 1kΩ. R1 is then
chosen according to Equation 2:
Substitute PD for PD(MAX) and the maximum ambient
operating temperature can be found by solving for TA
using Equation 6:
⎛ R1
⎞
V OUT = 0.5V × ⎜ ------- + 1⎟
⎝ R2
⎠
(EQ. 1)
V OUT
R 1 = R 2 × ⎛ ---------------- – 1⎞
⎝ 0.5V
⎠
(EQ. 2)
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 4
shows a curve for the θJA of the DFN package for
different copper area sizes.
T A = T JMAX – P D ( MAX ) × θ JA
(EQ. 6)
Heatsinking The DFN Package
46
Power Dissipation
The junction temperature must not exceed the range
specified in the Recommended Operating Conditions. The
power dissipation can be calculated by using Equation 3:
θJA, C/W
44
42
40
38
36
34
2
P D = ( V IN – V OUT ) × I OUT + V IN × I GND
8
(EQ. 3)
4
6
8
10 12 14 16 18 20 22
2
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
24
FIGURE 4. 3mmx3mm-10 Pin DFN ON 4-LAYER PCB
WITH THERMAL VIAS θJA vs EPAD-MOUNT
COPPER LAND AREA ON PCB
FN6660.0
September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A.
1.8
2.0
1.8
1.6
OUTPUT VOLTAGE (V)
ΔVOUT (%)
1.2
0.6
0
-0.6
-1.2
+125°C
1.4
1.2
+25°C
1.0
-40°C
0.8
0.6
0.4
0.2
-1.8
-50
-25
0
25
50
75
100 125
JUNCTION TEMPERATURE (°C)
0
150
FIGURE 5. OUTPUT VOLTAGE vs TEMPERATURE
GROUND CURRENT (mA)
ΔVOUT (%)
0.6
+25°C
0.0
-0.6
-40°C
-1.2
+125°C
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
5
6
8
7
6
5
4
3
2
1
0
3.0
3
2
4
12.0
8.9
11.5
11.0
CURRENT (mA)
-40°C
8.5
8.3
+25°C
8.1
+125°C
7.9
-40°C
10.5
10.0
9.5
+125°C
9.0
8.5
7.7
+25°C
8.0
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3.0
FIGURE 9. GROUND CURRENT vs OUTPUT CURRENT
9
6
FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE
9.1
8.7
5
INPUT VOLTAGE (V)
FIGURE 7. OUTPUT VOLTAGE vs OUTPUT CURRENT
GROUND CURRENT (mA)
3
2
4
SUPPLY VOLTAGE (V)
9
1.2
7.5
1
FIGURE 6. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
1.8
-1.8
0
7.5
0.8
1.4
2.0
2.6
3.2
3.8
OUTPUT VOLTAGE (V)
4.4
5.0
FIGURE 10. GROUND CURRENT vs OUTPUT VOLTAGE
FN6660.0
September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
12
4.5
11
10
9
8
7
6
5
4
3
2
1
0
-40 -25 -10
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VIN = 5V
0.5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 11. SHUTDOWN CURRENT vs TEMPERATURE
DROPOUT VOLTAGE (mV)
GROUND CURRENT (µA)
5.0
150
140
130
120
110
2A
100
90
3A
80
70
60
50
40
30
20
1A
10
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 13. DROPOUT VOLTAGE vs TEMPERATURE
VIN = 6V
5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 12. SHUTDOWN CURRENT vs TEMPERATURE
DROPOUT VOLTAGE (mV)
GROUND CURRENT (µA)
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3.0
FIGURE 14. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
VOLTAGE (V)
0.80
0.75
VIN (1V/DIV)
0.70
SS (1V/DIV)
0.65
0.60
0.55
0.50
VOUT (1V/DIV)
0.45
0.40
0.35
0.30
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 15. ENABLE THRESHOLD VOLTAGE vs
TEMPERATURE
10
PG (1V/DIV)
TIME (10ms/DIV)
FIGURE 16. POWER-UP (VIN = 2.2V)
FN6660.0
September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
EN (1V/DIV)
VIN (1V/DIV)
SS (1V/DIV)
SS (1V/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
PG (1V/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (10ms/DIV)
FIGURE 18. ENABLE START-UP
FIGURE 17. POWER-DOWN (VIN = 2.2V)
300
SS (1V/DIV)
VOUT (1V/DIV)
START-UP TIME (µs)
EN (1V/DIV)
PG (1V/DIV)
CURRENT LIMIT (A)
START-UP TIME (µs)
200
150
100
50
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 21. START-UP TIME vs TEMPERATURE
11
150
100
50
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
6.0
FIGURE 20. START-UP TIME vs SUPPLY VOLTAGE
300
250
200
0
2.0
TIME (5ms/DIV)
FIGURE 19. ENABLE SHUTDOWN
250
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-40 -25 -10
ISL80103
ISL80102
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 22. CURRENT LIMIT vs TEMPERATURE
FN6660.0
September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
CURRENT LIMIT (A)
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
ISL80103
VOUT (1V/DIV)
ISL80102
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
6.0
IOUT (1A/DIV)
TIME (10ms/DIV)
FIGURE 23. CURRENT LIMIT vs SUPPLY VOLTAGE
FIGURE 24. CURRENT LIMIT RESPONSE (ISL80102)
VOUT (1V/DIV)
VOUT (1V/DIV)
IOUT (1A/DIV)
IOUT (2A/DIV)
TIME (100ms/DIV)
TIME (20ms/DIV)
FIGURE 25. THERMAL CYCLING (ISL80102)
FIGURE 26. CURRENT LIMIT RESPONSE (ISL80103)
EN (1V/DIV)
VOUT (1V/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
VOUT (1V/DIV)
TIME (50ms/DIV)
FIGURE 27. THERMAL CYCLING (ISL80103)
12
TIME (1ms/DIV)
FIGURE 28. IN-RUSH CURRENT WITH NO
SOFT-START CAPACITOR, COUT = 1000µF
FN6660.0
September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
EN (1V/DIV)
EN (1V/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
TIME (1ms/DIV)
TIME (1ms/DIV)
FIGURE 29. IN-RUSH WITH 22nF SOFT-START
CAPACITOR, COUT = 1000µF
FIGURE 30. IN-RUSH WITH 47nF SOFT-START
CAPACITOR, COUT = 1000µF
VOUT (50mV/DIV)
VOUT (50mV/DIV)
3A
3A
0A
0A
IOUT (2A/DIV)
IOUT (2A/DIV)
TIME (100µs/DIV)
FIGURE 31. LOAD TRANSIENT 0A TO 3A,
COUT = 10µF CERAMIC
TIME (100µs/DIV)
FIGURE 32. LOAD TRANSIENT 0A TO 3A,
COUT = 10µF CERAMIC + 100µF OSCON
VOUT (50mV/DIV)
3A
VOUT (50mV/DIV)
IOUT (2A/DIV)
1A
3A
1A
TIME (100µs/DIV)
FIGURE 33. LOAD TRANSIENT 1A TO 3A,
COUT = 10µF CERAMIC
13
IOUT (2A/DIV)
TIME (100µs/DIV)
FIGURE 34. LOAD TRANSIENT 1A TO 3A,
COUT = 10µF CERAMIC + 100µF OSCON
FN6660.0
September 30, 2009
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
3.2V
80
2.2V
100mA
70
VIN (1V/DIV)
60
dB
50
1A
40
30
20
VOUT (10mV/DIV)
10
0
10
100
TIME (200µs/DIV)
FIGURE 35. LINE TRANSIENT
1M
80
70
70
100µF
2.5V
60
60
50
dB
40
30
20
10
IL = 100mA
0
10
100
2V
40
30
10µF
20
2.2V
50
47µF
1k
10k
FREQUENCY (Hz)
100k
IL = 1A
0
10
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 38. PSRR vs VIN
FIGURE 37. PSRR vs COUT
10
NOISE µV/√Hz
dB
100k
FIGURE 36. PSRR vs LOAD
80
10
1k
10k
FREQUENCY (Hz)
1
0.1
0.01
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 39. SPECTRAL NOISE DENSITY vs FREQUENCY
14
FN6660.0
September 30, 2009
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
09/30/09
FN6660.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL80102, ISL80103
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN6660.0
September 30, 2009
ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
3.00
6
PIN #1 INDEX AREA
A
B
1
6
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
4
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
4
(4X)
0.10 M C A B
0.415
PACKAGE
OUTLINE
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
BASE PLANE
2.00
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
C
0.20 REF
5
1.60
0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
16
FN6660.0
September 30, 2009