ICST ICS557G-08 2:1 multiplexer chip for pci-express Datasheet

ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS
Description
Features
The ICS557-08 is a 2:1 multiplexer chip that allows the
user to select one of the two HCSL (Host Clock Signal
Level) or LVDS input pairs and fan out to one pair of
differential HCSL or LVDS outputs. This chip is suited
especially for PCI-Express applications, where there is
a need to select the PCI-Express clock either locally
from the PCI-E card or from the motherboard.
•
•
•
•
•
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Operating voltage of 3.3 V
Low power consumption
Input clock frequency of up to 200 MHz for HCSL and
up to 100 MHz for LVDS
• Jitter 60 ps (cycle-to-cycle)
Block Diagram
OE
VDD
3
IN1
CLK
IN1
MUX
2 to 1
IN2
CLK
IN2
3
SEL
PD
1
MDS 557-08 C
I n t e gra te d C i r c u i t S y s t e m s
Rr (IREF)
GND
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Pin Assignment
Select Table
VDD
1
16
SEL
IN1
2
15
CLK
IN1
3
14
CLK
PD
4
13
GND
IN2
5
12
GND
IN2
6
11
VDD
OE
7
10
VDD
GND
8
9
IREF
SEL
Input Pair
selected
0
IN2/ IN2
1
IN1/ IN1
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Pin
Name
Pin
Type
1
VDD
Power
2
IN1
Input
HCSL/LVDS true input signal 1.
3
IN1
Input
HCSL/LVDS complimentary input signal 1.
Pin Description
Connect to +3.3 V. Supply voltage for Input clocks.
4
PD
Input
Powers down the chip and tri-states outputs when low. Internal pull-up resistor.
5
IN2
Input
HCSL/LVDS true input signal 2.
6
IN2
Input
HCSL/LVDS complimentary input signal 2.
7
OE
Input
Provides output or, tri-states output (High = enable outputs; Low = disable). Internal
pull-up resistor.
8
GND
Power
Connect to ground.
9
IREF
Output
Precision resistor attached to this pin is connected to the internal current reference.
10
VDD
Power
Connect to +3.3 V. Supply Voltage for Output Clocks.
11
VDD
Power
Connect to +3.3 V. Supply Voltage for Output Clocks.
12
GND
Power
Connect to ground.
13
GND
Power
Connect to ground.
14
CLK
Output
HCSL/LVDS Complimentary output clock .
15
CLK
Output
HCSL/LVDS True output clock.
16
SEL
Input
2
MDS 557-08 C
In te grated Circuit Systems
SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Application Information
Decoupling Capacitors
External Components
As with any high-performance mixed-signal IC, the
ICS557-08 must be isolated from system power supply
noise to perform optimally.
A minimum number of external components are
required for proper operation. Decoupling capacitors of
0.01 µF should be connected between VDD and GND
pins as close to the device as possible.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
If board target trace impedance (Z) is 50Ω, then Rr =
475Ω (1%), providing IREF of 2.32 mA, output current
(IOH) is equal to 6*IREF.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Each 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS557-08.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
Load Resistors RL
Since the clock outputs are open source outputs, 50Ω
external resistors to ground are to be connected at
each clock output.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-08 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
The ICS557-08 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
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MDS 557-08 C
In te grated Circuit Systems
Current Reference Source Rr (Iref)
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Output Structures
6*IREF
IREF
=2.3 mA
R R 475Ω
See Output Termination
Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-08.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
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In te grated Circuit Systems
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Differential Routing on a Single PCB
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
PCI-Express Device Routing
L1
L2
L4
RS
L1’
L4’
L2’
RS
RT
ICS557-08
Output
Clock
L3’
RT
PCI-Express
Load or
Connector
L3
Typical PCI-Express (HCSL)
Waveform
700 mV
0
tOR
500 ps
500 ps
0.525 V
0.175 V
0.525 V
0.175 V
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In te grated Circuit Systems
tOF
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
RP
RQ
RT
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
ohm
ohm
ohm
LVDS Device Routing
L1
L3
RQ
L1’
RT
ICS557-08
Clock
Output
RP
L3’
RT
L2’
LVDS
Device
Load
L2
Typical LVDS Waveform
1325 mV
1000 mV
tOR
500 ps
500 ps
1250 mV
1150 mV
1250 mV
1150 mV
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In te grated Circuit Systems
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-08. These ratings are
stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
125°C
Soldering Temperature
260°C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Supply Voltage
Conditions
V
1
Min.
Typ.
Max.
Units
3.135
3.465
V
Input High Voltage
VIH
OE, SEL, PD
2.0
VDD +0.3
V
Input Low Voltage1
VIL
OE, SEL, PD
VSS-0.3
0.8
V
Input Leakage Current2
IIL
0 < Vin < VDD
-5
5
µA
Operating Supply Current
IDD
50Ω, 2 pF
40
mA
IDDOE
OE =Low
20
mA
IDDPD
No load, PD =Low
400
µA
Input pin capacitance
7
pF
Output pin capacitance
6
pF
5
nH
Input Capacitance
CIN
Output Capacitance
COUT
Pin Inductance
LPIN
Output Resistance
ROUT
CLK outputs
Pull-up Resistor
RPUP
OE, SEL, PD
1 Single edge is monotonic when transitioning through
2 Inputs with pull-ups/-downs are not included.
kΩ
110
kΩ
region.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
AC Electrical Characteristics Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Operating Frequency
1,2
Input High Voltage
1,2
Input Low Voltage
Differential Input
Voltages
Input Offset Voltage
Max.
Units
HCSL termination
Conditions
Min.
200
MHz
LVDS termination
100
MHz
850
mV
VIH
HCSL
660
VIL
Typ.
700
HCSL
-150
0
(VID)
LVDS
250
350
450
mV
(VIS)
LVDS
1.125
1.25
1.375
V
700
850
mV
550
mV
140
mV
1,2
VOH
HCSL
660
1,2
VOL
Output High Voltage
Output Low Voltage
HCSL
-150
0
Crossing Point
Voltage1,2
Absolute
250
350
Crossing Point
Voltage1,2,4
Variation over all edges
Jitter, Cycle-to-Cycle1,3
mV
mV
60
1,2
ps
Rise Time
tOR
From 0.175 V to 0.525 V
175
332
700
ps
Fall Time1,2
tOF
From 0.525 V to 0.175 V
175
344
700
ps
125
ps
55
%
Rise/Fall Time
Variation1,2
Duty Cycle1,3
45
5
Output Enable Time
All outputs
10
µs
Output Disable Time5
All outputs
10
µs
From power-up VDD=3.3 V
3.0
ms
4
ns
Stabilization Time
tSTABLE
Input to Output Delay
Input differential clock to output
differential clock delay measured at
crossing point of input levels to
crossing point of output levels
1
Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%).
2
Measurement taken from a single-ended waveform.
3
Measurement taken from a differential waveform.
4
Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
5
CLK and CLK pins are tri-stated when OE is Low asserted. CLK and CLK are driven differential when OE is High
unless its PD = low.
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In te grated Circuit Systems
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Thermal Resistance Junction to
Ambient
θJA
Still air
93
°C/W
θJA
1 m/s air flow
78
°C/W
θJA
3 m/s air flow
65
°C/W
Thermal Resistance Junction to Case
θJC
20
°C/W
Marking Diagram (ICS557GI-08)
Marking Diagram (ICS557G-08)
16
9
16
557G-08
######
YYWW$$
1
557GI-08
######
YYWW$$
8
1
16
9
9
557GI08L
######
YYWW
557G08LF
######
YYWW
1
8
Marking Diagram (ICS557GI-08LF)
Marking Diagram (ICS557G-08LF)
16
9
1
8
8
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb free package.
4. “I” denotes industrial temperature device
5. Bottom marking: (origin). Origin = country of origin if not USA.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
A
A2
Min
Inches*
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
*For reference only. Controlling dimensions in mm.
A1
c
-Ce
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
Tubes
16-pin TSSOP
0 to +70° C
Tape and Reel
16-pin TSSOP
0 to +70° C
ICS557G-08
ICS557G-08T
ICS557G-08LF
See Page 9
Tubes
16-pin TSSOP
0 to +70° C
ICS557G-08LFT
Tape and Reel
16-pin TSSOP
0 to +70° C
ICS557GI-08
Tubes
16-pin TSSOP
-40 to +85° C
Tape and Reel
16-pin TSSOP
-40 to +85° C
Tubes
16-pin TSSOP
-40 to +85° C
Tape and Reel
16-pin TSSOP
-40 to +85° C
ICS557GI-08T
ICS557GI-08LF
See Page 9
ICS557GI-08LFT
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
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In te grated Circuit Systems
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Revision History
Rev.
Originator
Date
Description of Change
C
D.Chan
02/16/06
11
MDS 557-08 C
In te grated Circuit Systems
Added industrial temp range; updated PCI-Express Waveform diagram to include 0.525 V;
changed “Supply Voltage, VDD” spec in Absolute Max. Ratings from 5.5 V to 7 V; changed
CLKOUT to CLK and CLK ; added marking diagrams for I-temp device.
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