PHILIPS HEF4050BT Hex non-inverting buffer Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4050B
buffers
HEX non-inverting buffers
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4050B
buffers
HEX non-inverting buffers
DESCRIPTION
The HEF4050B provides six non-inverting buffers with
high current output capability suitable for driving TTL or
high capacitive loads. Since input voltages in excess of the
buffers’ supply voltage are permitted, the buffers may also
be used to convert logic levels of up to 15 V to standard
TTL levels. Their guaranteed fan-out into common bipolar
logic elements is shown in the table below.
Fig.2 Pinning diagram.
HEF4050BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4050BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4050BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
APPLICATION INFORMATION
Some examples of applications for the HEF4050B are:
• LOCMOS to DTL/TTL converter
• HIGH sink current for driving 2 TTL loads
• HIGH-to-LOW level logic conversion
Fig.1 Functional diagram.
Input protection
Guaranteed fan-out in common logic families
DRIVEN ELEMENT
GUARANTEED
FAN-OUT
standard TTL
2
74 LS
9
74 L
16
Fig.4
Input protection circuit that allows input
voltages in excess of VDD.
FAMILY DATA, IDD LIMITS category BUFFERS
See Family Specifications
Fig.3 Logic diagram (one gate).
January 1995
2
Philips Semiconductors
Product specification
HEF4050B
buffers
HEX non-inverting buffers
DC CHARACTERISTICS
VSS = 0 V; VI = VSS or VDD
HEF
VDD
V
VO
V
Tamb (°C)
SYMBOL
−40
MIN.
Output (sink)
current LOW
Output (source)
current HIGH
4,75
0,4
10
0,5
15
1,5
5
4,6
10
9,5
15
13,5
5
2,5
IOL
+25
MAX.
MIN.
MAX.
MIN.
MAX.
2,3
−
mA
3,5
−
2,9
−
12,0
−
10,0
−
8,0
−
mA
24,0
−
20,0
−
16,0
−
mA
0,52 −
IOH
+85
0,44
−
0,36
−
mA
1,3
−
1,1
−
0,9
−
mA
3,6
−
3,0
−
2,4
−
mA
1,7
−
1,4
−
1,1
−
mA
Output (source)
current HIGH
HEC
VDD
V
VO
V
IOH
Tamb (°C)
SYMBOL
−55
MIN.
Output (sink)
4,75
0,4
10
0,5
15
1,5
Output (source)
5
4,6
current HIGH
10
9,5
15
13,5
current LOW
January 1995
IOL
+25
MAX.
+125
MIN.
MAX.
MIN.
MAX.
3,6
−
2,9
−
1,9
−
mA
12,5
−
10,0
−
6,7
−
mA
25,0
−
20,0
−
13,0
−
mA
−
mA
0,52
IOH
3
−
0,44
−
0,36
1,3
−
1,1
−
0,9
−
mA
3,6
−
3,0
−
2,4
−
mA
Philips Semiconductors
Product specification
HEF4050B
buffers
HEX non-inverting buffers
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Propagation delays
SYMBOL
5
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
35
70
ns
26 ns + (0,18 ns/pF) CL
On
10
20
35
ns
16 ns + (0,08 ns/pF) CL
HIGH to LOW
15
15
30
ns
12 ns + (0,05 ns/pF) CL
5
55
110
ns
28 ns + (0,55 ns/pF) CL
In
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
25
55
ns
14 ns + (0,23 ns/pF) CL
15
20
40
ns
12 ns + (0,16 ns/pF) CL
5
25
50
ns
7 ns + (0,35 ns/pF) CL
10
10
20
ns
3 ns + (0,14 ns/pF) CL
7
14
ns
2 ns + (0,09 ns/pF) CL
5
60
120
ns
10 ns + (1,0 ns/pF) CL
10
VDD
V
dissipation per
package (P)
tPLH
15
10
15
Dynamic power
tPHL
5
tTHL
tTLH
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
TYPICAL FORMULA FOR P (µW)
3 800 fi + ∑ (foCL) × VDD2
10
11 600 fi + ∑ (foCL) × VDD
15
65 900 fi + ∑ (foCL) ×
2
VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
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