Rohm BD8312HFN Output 1.5a or less high-efficiency step-down switching regulator with built-in power mosfet Datasheet

Single-chip Type with Built-in FET Switching Regulators
Output 1.5A or Less
High-efficiency Step-down Switching Regulator
with Built-in Power MOSFET
BD8312HFN
No.11027EDT04
●Description
BD8312HFN produces step-down output including 1.2, 1.8, 3.3, or 5 V from 4 batteries, batteries such as Li2cell or Li3cell,
etc. or a 5V/12V fixed power supply line.
This IC allows easy production of small power supply by a wide range of external constants, and is equipped with an external
coil/capacitor downsized by high frequency operation of 1.5 MHz, built-in synchronous rectification SW capable of
withstanding 15 V, and flexible phase compensation system on board.
●Features
1) Incorporates Pch/Nch synchronous rectification SW capable of withstanding 1.0 A/15V.
2) Incorporates phase compensation device between input and output of Error AMP.
3) Small coils and capacitors to be used by high frequency operation of 1.5MHz
4) Input voltage 3.5 V – 14 V
Output current 1.2A(7.4V input, 3.3V output)
0.8A(4.5V input, 3.3V output)
5) Incorporates soft-start function.
6) Incorporates timer latch system short protecting function.
7) As small as 2.9mm×3 mm, SON 8-pin package
HSON8
●Application
For portable equipment like DSC/DVC powered by 4 dry batteries or Li2cell and Li3cell, or general consumer-equipment
with 5 V/12 V lines
●Operating Conditions (Ta = 25℃)
Parameter
Power supply voltage
Output voltage
●Absolute Maximum Ratings
Parameter
Maximum applied power voltage
Maximum input current
Power dissipation
Operating temperature range
Storage temperature range
Junction temperature
Symbol
Voltage circuit
Unit
VCC
3.5 to 14
V
VOUT
1.2 to 12
V
Symbol
Rating
Unit
VCC, PVCC
15
V
Iinmax
1.0
A
Pd
630
mW
Topr
-25 to +85
℃
Tstg
-55 to +150
℃
Tjmax
+150
℃
*1 When used at Ta = 25℃ or more installed on a 70×70×1.6tmm board, the rating is reduced by 5.04mW/℃.
* These specifications are subject to change without advance notice for modifications and other reasons.
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1/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Electrical Characteristics
（Unless otherwise specified, Ta = 25 ℃, VCC = 7.4 V）
Parameter
Symbol
Target Value
Unit
Min
Typ
Max
VUV
-
2.9
3.2
V
ΔVUVhy
100
200
300
mV
Fosc
1.38
1.5
1.62
MHz
VREG
4.65
5.0
5.35
V
INV threshold voltage
VINV
0.99
1.00
1.01
V
Input bias current
IINV
-50
0
50
nA
Soft-start time
Tss
3.2
5.3
7.4
msec
Dmax
-
-
(※)100
%
PMOS ON resistance
RONP
-
450
600
mΩ
NMOS ON resistance
RONN
-
300
420
mΩ
Leak current
Ileak
-1
0
1
µA
Operation
VSTBH
2.5
-
11
V
No-operation
VSTBL
-0.3
-
0.3
V
250
400
700
kΩ
Conditions
[Low voltage input malfunction preventing circuit]
Detection threshold voltage
Hysteresis range
VREG monitor
[Oscillator]
Oscillation frequency
[Regulator]
Output voltage
[Error AMP]
VCC=12.0V ,
VINV=6.0V
[PWM comparator]
LX Max Duty
[Output]
[STB]
STB pin
control voltage
STB pin pull-down resistance
[Circuit current]
VCC pin
ISTB1
-
-
1
µA
PVCC pin
ISTB2
-
-
1
µA
Circuit current at operation VCC
-
600
900
µA
VINV=1.2V
Circuit current at operation
-
30
50
µA
VINV=1.2V
Standby current
PVCC
(※1) 100% is MAX Duty as behavior of a PWM conparetor.
Using in region where High side PMOS is 100% on state when the same or less input voltage than output voltage is supplied as an application circuit
causes detection of SCP then DC/DC converter stops.
 Not designed to be resistant to radiation
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2/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Description of Pins
GND
INV
VCC
STB
VREG
Pin No.
Pin Name
1
GND
Ground terminal
2
VCC
Control part power input terminal
3
VREG
5 V output terminal of regulator for
internal circuit
4
PGND
Power transistor ground terminal
5
Lx
6
PVCC
7
STB
ON/OFF terminal
8
INV
Error AMP input terminal
PVCC
PGND
Lx
Fig.1 Terminal layout
Function
Coil connecting terminal
DC/DC converter input terminal
●Block Diagram
ON/OFF
STB
Reference
5V REG
STBY_IO
OSC
1.0MHz
PRE
DRIVER
SCP
450mΩ
OSC×4000 ｃount
PWM
CONTROL
Step down
TIMMING
CONTROL
LX
VREG
PRE
DRIVER
+
+
-
GND
UVLO
VREF
DC/DC
converter
100% High
Duty
STOP
VREF
PVCC
VREG VCC
300mΩ
ERROR_AMP
Soft
Start
PGND
OSC×8000 ｃount
INV
Fig.2 Block diagram
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3/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Description of Blocks
1. Reference
This block produces ERROR AMP standard voltage.
The standard voltage is 1.0 V.
2. 5 V Reg
5 V low saturation regulator for internal analog circuit
BD8312HFN is equipped with this regulator for the purpose of protecting the internal circuit from high voltage. Therefore,
this output is reduced when VCC is less than 5 V, then PMOS ON resistance increases and Power efficiency and
Maximum output current of DC/DC converter decreases in this region. Please see attached data (fig14,15,16,17) about
increasing of PMOS ON resistance in this region.
3 UVLO
Circuit for preventing low voltage malfunction
Prevents malfunction of the internal circuit at activation of the power supply voltage or at low power supply voltage.
Monitors VCC pin voltage to turn off all output FET and DC/DC converter output when VCC voltage is lower than 2.9 V,
and reset the timer latch of the internal SCP circuit and soft-start circuit. This threshold contains 200 mV hysteresis.
4 SCP
Timer latch system short-circuit protection circuit
When DC/DC converter is 100% High Duty , the internal SCP circuit starts counting.
The internal counter is in synch with OSC, the latch circuit is activated about 2.7 msec after the counter counts about 4000
oscillations to turn off DC/DC converter output.
To reset the latch circuit, turn off the STB pin once. Then, turn it on again or turn on the power supply voltage again.
5 OSC
Circuit for oscillating sawtooth waves with an operation frequency fixed at 1.5 MHz
6 ERROR AMP
Error amplifier for detecting output signals and output PWM control signals
The internal standard voltage is set at 1.0 V.
A primary phase compensation device of 200 pF, 62 kΩ is built in-between the inverting input terminal and the output
terminal of this ERROR AMP.
7
PWM COMP
Voltage-pulse width converter for controlling output voltage corresponding to input voltage
Comparing the internal SLOPE waveform with the ERROR AMP output voltage, PWM COMP
controls the pulse width to the output to the driver.
8 SOFT START
Circuit for preventing in-rush current at startup by bringing the output voltage of the DC/DC converter into a soft-start
Soft-start time is in synch with the internal OSC, and the output voltage of the DC/DC converter reaches the set voltage
after about 8000 oscillations.
9
PRE DRIVER/TIMING CONTROL
CMOS inverter circuit for driving the built-in synchronous rectification SW
The synchronous rectification OFF time for preventing feedthrough is about 25 nsec.
10 STBY_IO
Voltage applied on STB pin (7 pin) to control ON/OFF of IC
Turned ON when a voltage of 2.5 V or higher is applied and turned OFF when the terminal is open or 0 V is applied.
Incorporates approximately 400 kΩ pull-down resistance.
11 Pch/Nch FET SW
Built-in synchronous rectification SW for switching the coil current of the DC/DC converter
Incorporates a 450 mΩ PchFET SW capable of withstanding 15 V.and 300 mΩ SW capable of withstanding 15 V.
Since the current rating of this FET is 1.0A, it should be used within 1.0A including the DC current and ripple current of the coil.
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4/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Reference data
（Unless otherwise specified, Ta = 25℃, VCC = 7.4 V）
1.02
5.3
1.02
5.2
1.00
0.99
VREG VOLTAGE [V]
1.01
INV THRESHOLD [V]
INV THRESHOLD [V]
1.01
1.00
5.1
5.0
4.9
0.99
4.8
0.98
4.7
0.98
-40
-20
0
20
40
60
80
100
120
0
2
4
6
TEMPERATURE [℃]
8
10
12
-40
14
0
VCC [V]
Fig.4. INV
threshold power supply property
Fig.3. INV
threshold temperature property
80
120
Fig.5. VREG output
temperature property
1.7
1.7
8
40
TEMPERATURE [℃]
7
5
4
3
2
FREQUENCY [ MHz ]
FREQUENCY [MHz]
VREG[V]
1.6
1.6
6
1.5
1.5
1.4
1.4
1
0
1.3
1.3
0
2
4
6
8
10
12
14
-40
0
40
80
6
Fig.6. VREG
output power supply property
Fig.7. fosc
temperature property
600
ID=500mA
ID=500mA
3.10
0.20
0.15
2.90
0.10
UVLO detection voltage
2.70
ON RESISTANCE [ mΩ]
UVLO release voltage
400
ON RESISTANCE [ mΩ ]
Hysteresis
VoltageVhys
Vhys[V]
ヒステリシス電圧
[V]
500
400
300
300
200
200
100
0.05
2.50
0
15
Fig.8. fosc
voltage property
500
-40
12
0.25
Hysteresis width
3.30
9
VCC [V]
TEMPERATURE [℃]
VCC [V]
3.50
3
120
40
80
0.00
120
0
100
-40
0
40
80
120
3
6
9
12
15
TEMPARATURE [℃]
VCC [V]
Fig.10. Nch FET ON resistance
temperature property
Fig.11. Nch FET ON resistance
power supply property
Environmental
temperature
Ta [℃] Ta [°C]
環境温度
Fig.9. UVLO
threshold temperature property
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5/14
2011.04 - Rev.D
Technical Note
BD8312HFN
1000
800
3.0
ID=500mA
ID=500mA
400
200
600
400
200
-40
0
40
80
6
9
12
1.5
1.0
Ta=-25℃
0.0
15
TEMPARATURE [℃]
VCC [V]
Fig.12. Pch FET ON resistance
temperature property
Fig.13. Pch FET ON resistance
power supply property
2.5
2.5
Ta=25℃
1.5
1.0
Ta=-25℃
PMOS ON Resistance (Ω)
2.5
PMOS ON Resistance (Ω)
3.0
Ta=85℃
2.0
Ta=25℃
Ta=85℃
1.5
1.0
Ta=-25℃
0.5
0.0
1.0
1.0
1.0
Ta=-25℃
0.0
2.0
1.0
Fig.17.PchFET ON resistance
Io property [VCC=5.0V]
Fig.16.PchFET ON resistance
Io property [VCC=4.5V]
2.5
2.0
Io [A]
Io [A]
Io [A]
Fig.15.PchFET ON resistance
Io property [VCC=4.0V]
Ta=25℃
Ta=85℃
1.5
0.0
0.0
2.0
2.0
0.5
0.0
0.0
2.0
Fig.14.PchFET ON resistance
Io property [VCC=3.5V]
3.0
2.0
1.0
Io [A]
3.0
0.5
1000
1000
800
800
600
600
1.5
1.0
0
50
400
100
150
Ta [℃]
Fig.18. STB
threshold temperature property
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400
200
200
OFF
-50
ICC [uA]
ON
2.0
ICC [uA]
STB Voltage [V]
2.0
0.0
3
120
Ta=25℃
0.5
0
0
PMOS ON Resistance (Ω)
PMOS ON Resistance (Ω)
SWOUT ON Resistance [Ω ]
SWOUT ON Resistance [Ω ]
600
Ta=85℃
2.5
800
0
0
-40
0
40
80
TEMPARATURE [℃]
Fig.19. Circuit current
temperature property
6/14
120
0
2
4
6
8
10
12
14
VCC [V]
Fig.20. Circuit current
voltage property
2011.04 - Rev.D
Technical Note
BD8312HFN
●Example of Application
Input: 4.5 to 10 V, output: 3.3 V / 500mA
VBAT=4.5～10V
1μF
GRM188B11A105KA61
（Murata）
GND
INV
VCC
STB
ON/OFF
10pF
PVCC
VREG
3.3V/500mA
1μF
GRM188B11A105KA61
（Murata）
Lx
PGND
4.7μH
1098AS-4R7M（TOKO）
10kΩ
200kΩ
51kΩ
10μF
GRM31CB11A106KA01
（Murata）
22kΩ
Fig.21 Reference application diagram
●Reference application data 1
100
3.35
80
60
OUTPUT VOLTAGE [V]
EFFICIENCY [%]
VCC=7.5V
3.33
VCC=4.5V
VCC=7.5V
VCC=5.5V
40
20
VCC=5.5V
3.31
VCC=4.5V
3.29
3.27
3.25
0
1
10
100
1000
1
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100
1000
Fig.23 Load regulation
(VOUT = 3.3 V)
Fig.22 Power conversion efficiency
(VOUT = 3.3 V)
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10
OUTPUT CURRENT [mA]
OUTPUT CURRENT [mA]
7/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Reference application data 2 (Input 4.5 V, 6.0 V, 8.4 V, 10 V, output 3.3 V ）
60
40
120
40
20
60
20
60
0
0
120
20
60
-20
-60
-40
-60
-60
-120
-40
-120
-40
-180
-60
-180
-60
100000 1000000
100
周波数 [Hz]
Frequency
[Hz]
1000
10000
60
180
60
40
20
60
0
0
Gain
Gain [dB]
120
Phase [deg]
Gain [dB]
40
20
60
0
0
-40
-180
-60
Gain
100
1000
Frequency
[Hz]
周波数 [Hz]
10000
100000
60
40
120
40
20
60
20
Gain [dB]
0
Gain
Phase [deg]
Gain [dB]
-60
-120
-40
-120
-180
-60
Phase
0
0
Gain
-60
-40
-120
-40
-120
-180
-60
10000
100000
1000000
Frequency
[Hz]
周波数 [Hz]
Fig.30 Frequency response 7
(VCC=8.4V, Io=500mA)
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100000
1000000
Fig.29 Frequency response 6
(VCC=6.0V, Io=500mA)
60
-20
1000
10000
120
-60
100
1000
180
-20
-60
-180
100
1000000
周波数 [Hz]
Frequency
[Hz]
Phase
0
0
Gain
-20
Fig.28 Frequency response 5
(VCC=4.5V, Io=500mA)
180
0
-60
Frequency
[Hz]
周波数 [Hz]
Fig.27 Frequency response 4
(VCC=10V, Io=250mA)
60
180
Phase
60
-120
1000000
60
180
Phase
20
-40
100000
Fig.26 Frequency response 3
(VCC=8.4V, Io=250mA)
120
-20
10000
100000 1000000
40
-60
-60
10000
120
-20
1000
1000
周波数 [Hz][Hz]
Frequency
Fig.25 Frequency response 2
(VCC=6.0V, Io=250mA)
Phase
-60
-180
100
100000 1000000
120
-120
Frequency
周波数 [Hz][Hz]
Fig.24 Frequency response 1
(VCC=4.5V, Io=250mA)
100
Gain
-20
-20
Gain [dB]
10000
0
Gain
Phase [deg]
1000
0
Phase
Phase [deg]
100
Gain [dB]
0
Gain
Phase [deg]
Gain [dB]
0
180
Phase [deg]
40
Phase
Phase [deg]
60
Gain [dB]
180
180
Phase
Phase [deg]
60
-180
100
1000
10000
100000
1000000
Frequency
[Hz]
周波数 [Hz]
Fig.31 Frequency response 8
(VCC=10V, Io=500mA)
8/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Reference board pattern
VOUT
Lx
VBAT
GND
・The radiation plate on the rear should be a GND flat surface of low impedance in common with the PGND flat surface.
・It is recommended to install a GND pin in another system as shown in the drawing without connecting it directly to this PNGD.
・Produce as wide a pattern as possible for the VBAT, Lx and PGND lines in which large current flows.
●Selection of Part for Applications
(1) Inductor
A shielded inductor that satisfies the current rating (current value,
Ipecac as shown in the drawing below) and has a low DCR
(direct resistance component) is recommended.
Inductor values affect inductor ripple current, which will cause output
ripple.
Ripple current can be reduced as the coil L value becomes larger
and the switching frequency becomes higher.
Ipeak =Iout ＋ ⊿IL/2 [A]
⊿IL=
Vin－Vout
L
×
Vout
Vin
Δ IL
Fig.32 Inductor current
(1)
1
×
f
[A]
(2)
(η: Efficiency, ⊿IL: Output ripple current, f: Switching frequency)
As a guide, inductor ripple current should be set at about 20 to 50% of the maximum input current.
*Current over the coil rating flowing in the coil brings the coil into magnetic saturation, which may lead to lower efficiency
or output oscillation. Select an inductor with an adequate margin so that the peak current does not exceed the rated
current of the coil.
(2) Output capacitor
A ceramic capacitor with low ESR is recommended for output in order to reduce output ripple.
There must be an adequate margin between the maximum rating and output voltage of the capacitor, taking the DC bias
property into consideration.
Output ripple voltage is acquired by the following equation.
Vpp=⊿IL×
1
＋ ⊿IL×RESR [V] ・・・ (3)
2π×f×Co
Setting must be performed so that output ripple is within the allowable ripple voltage.
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9/14
2011.04 - Rev.D
Technical Note
BD8312HFN
(3) Output voltage setting
The internal standard voltage of the ERROR AMP is 1.0 V.
Output voltage is acquired by Equation (4).
VOUT
ERROR AMP
R1
INV
Vo=
(R1+R2)
R2
R2
×1.0 [V] ・・・ (4)
VREF
1.0V
Fig.33 Setting of voltage feedback resistance
(4) DC/DC converter frequency response adjustment system
Condition for stable application
The condition for feedback system stability under negative feedback is that the phase delay is 135 °or less when gain is 1
(0dB).
Since DC/DC converter application is sampled according to the switching frequency, the bandwidth GBW of the whole
system (frequency at which gain is 0 dB) must be controlled to be equal to or lower than 1/10 of the switching frequency.
In summary, the conditions necessary for the DC/DC converter are:
- Phase delay must be 135°or lower when gain is 1 (0 dB).
- Bandwidth GBW (frequency when gain is 0 dB) must be equal to or lower than 1/10 of the switching frequency.
To satisfy those two points, R1, R2, R3, DS and RS in Fig. 34 should be set as follows.
[1] R1, R2, R3
BD8313HFN incorporates phase compensation devices of
R4=62kΩ and C2=200pF. These C2 and R1, R2, and R3
valuesdecide the primary pole that determines the bandwidth
of DC/DC converter.
VOUT
R1
Cs
Inside of IC
R4 C2
Rs
Primary pole point frequency
R2
FB
R3
1
fp=
2π A×(
R1×R2
+R3)×C2
R1+R2
・・・・(1)
Fig.34 Example of phase compensation setting
DC/DC converter DC Gain
DC Gain =A×
1
B
×
VIN
VO
A: Error AMP Gain
5
About 100dB = 10
B: Oscillator amplification = 0.5
VIN:
Input voltage
Output voltage
VOUT:
・・・・(2)
By Equations (1) and (2), the frequency fsw of point 0 dB under limitation of the bandwidth of the DC gain at the primary
pole point is as shown below.
fSW = fp×DC Gain =
1
(R1・R2)
2πC2×(
+R3 )
(R1+R2)
×
1
B
×
VIN
VO
・・・・(3)
It is recommended that fsw should be approx.10 kHz. When load response is difficult, it may be set at approx. 20 kHz.
By Equation (3), R1 and R2, which determine the voltage value, will be in the order of several hundred kΩ. If an
appropriate resistance value is not available since the resistance is so high and routing may cause noise, the use of R3
enables easy setting.
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10/14
2011.04 - Rev.D
Technical Note
BD8312HFN
[2] Cs and Rs setting
For DC/DC converter,
equation.
fLC=
the 2nd dimension pole point is caused by the coil and capacitor as expressed by the following
1
・・・・(4)
2π√(LC)
This secondary pole causes a phase rotation of 180°. To secure the stability of the system, put a zero point in 2 places to
perform compensation.
Zero point by built-in CR
fZ1=
Zero point by Cs
fZ1=
1
2πR4C2
1
2π(R1+R3)CS
= 13kHz
・・・・(5)
・・・・(6)
Setting fZ2 to be half to 2 times a frequency as large as fLC provides an appropriate phase margin.
It is desirable to set Rs at about 1/20 of (R1+R3) to cancel any phase boosting at high frequencies.
Those pole points are summarized in the figure below. The actual frequency property is different from the ideal
calculation because of part constants. If possible, check the phase margin with a frequency analyzer or network analyzer.
Otherwise, check for the presence or absence of ringing by load response waveform and also check for the presence or
absence of oscillation under a load of an adequate margin.
(5) (6)
(3)
(4)
Fig.35 Example of DC/DC converter frequency property
（Measured with FRA5097 by NF Corporation）
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11/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●I/O Equivalence Circuit
STB
INV
VCC
VCC
STB
VREG
INV
Lx, PGND, PVCC
VREG
VCC
VCC
PVCC
VREG
Lx
PGND
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12/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Notes for use
1) Absolute Maximum Rating
We dedicate much attention to the quality control of these products, however the possibility of deterioration or destruction
exists if the impressed voltage, operating temperature range, etc., exceed the absolute maximum ratings. In addition, it is
impossible to predict all destructive situations such as short-circuit modes, open circuit modes, etc. If a special mode
exceeding the absolute maximum rating is expected, please review matters and provide physical safety means such as
fuses, etc.
2) GND Potential
Keep the potential of the GND pin below the minimum potential at all times.
3) Thermal Design
Work out the thermal design with sufficient margin taking power dissipation (Pd) in the actual operation condition into account.
4) Short Circuit between Pins and Incorrect Mounting
Attention to IC direction or displacement is required when installing the IC on a PCB. If the IC is installed in the wrong way,
it may break. Also, the threat of destruction from short-circuits exists if foreign matter invades between outputs or the
output and GND of the power supply.
5) Operation under Strong Electromagnetic Field
Be careful of possible malfunctions under strong electromagnetic fields.
6) Common Impedance
When providing a power supply and GND wirings, show sufficient consideration for lowering common impedance and
reducing ripple (i.e., using thick short wiring, cutting ripple down by LC, etc.) as much as you can.
7) Thermal Protection Circuit (TSD Circuit)
This IC contains a thermal protection circuit (TSD circuit). The TSD circuit serves to shut off the IC from thermal runaway
and does not aim to protect or assure operation of the IC itself. Therefore, do not use the TSD circuit for continuous use or
operation after the circuit has tripped.
8) Rush Current at the Time of Power Activation
Be careful of the power supply coupling capacity and the width of the power supply and GND pattern wiring and routing since
rush current flows instantaneously at the time of power activation in the case of CMOS IC or ICs with multiple power supplies.
9) IC Terminal Input
This is a monolithic IC and has P+ isolation and a P substrate for element isolation between each element. P-N junctions
are formed and various parasitic elements are configured using these P layers and N layers of the individual elements.
For example, if a resistor and transistor are connected to a terminal as shown on Fig.36:
○ The P-N junction operates as a parasitic diode when GND > (Terminal A) in the case of a resistor or when GND >
(Pin B) in the case of a transistor (NPN)
○ Also, a parasitic NPN transistor operates using the N layer of another element adjacent to the previous diode in
the case of a transistor (NPN) when GND > (Pin B).
The parasitic element consequently rises under the potential relationship because of the IC’s structure. The parasitic
element pulls interference that could cause malfunctions or destruction out of the circuit. Therefore, use caution to avoid
the operation of parasitic elements caused by applying voltage to an input terminal lower than the GND (P board), etc.
B
C
N
P＋
N
P
N
P Substrate
P＋
P＋
N
Parasitic Element
GND
P
N
Ｎ
E
(Pin A)
P＋
～
～
(Pin B)
(Pin A)
～
～
Transistor (NPN)
Resistor
N
Parasitic Element
P Substrate
Parasitic Element
GND
GND
Fig.36 Example of simple structure of Bipolar IC
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© 2011 ROHM Co., Ltd. All rights reserved.
13/14
2011.04 - Rev.D
Technical Note
BD8312HFN
●Ordering part number
B
D
8
Part No.
3
1
2
H
Part No.
F
N
Package
HFN:HSON8
-
T
R
Packaging and forming specification
TR: Embossed tape and reel
HSON8
<Tape and Reel information>
(0.05)
(0.3)
(0.2)
1234
5678
(0.45)
(0.2) (1.8)
8 765
2.8 ± 0.1
3.0 ± 0.2
0.475
(2.2)
(0.15)
2.9±0.1
(MAX 3.1 include BURR)
4321
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
+0.1
0.13 –0.05
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
1pin
1PIN MARK
S
+0.03
0.02 –0.02
0.6MAX
)
0.1
S
0.65
0.32±0.1
0.08
Direction of feed
M
(Unit : mm)
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© 2011 ROHM Co., Ltd. All rights reserved.
Reel
14/14
∗ Order quantity needs to be multiple of the minimum quantity.
2011.04 - Rev.D
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
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More detail product informations and catalogs are available, please contact us.
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© 2011 ROHM Co., Ltd. All rights reserved.
R1120A