ADVANCED INFORMATION MX26L6420 64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM FEATURES • 4,194,304 x 16 byte structure • Single Power Supply Operation • • • • • • Status Reply - 2.7 to 3.6 volt for read, erase, and program operations Low Vcc write inhibit is equal to or less than 2.5V Compatible with JEDEC standard High Performance - Fast access time: 90/120ns (typ.) - Fast program time: 140s/chip (typ.) - Fast erase time: 150s/chip (typ.) Low Power Consumption - Low active read current: 17mA (typ.) at 5MHz - Low standby current: 30uA (typ.) Minimum 100 erase/program cycle • • • • - Data polling & Toggle bits provide detection of program and erase operation completion 12V ACC input pin provides accelerated program capability Output voltages and input voltages on the device is deterined by the voltage on the VI/O pin. - VI/O voltage range:1.65V~3.6V 10 years data retention Package - 44-Pin SOP - 48-Pin TSOP - 48-Ball CSP - 63-Ball CSP GENERAL DESCRIPTION The MX26L6420 is a 64M bit MTP EPROMTM organized as 4M bytes of 16 bits. MXIC's MTP EPROMTM offer the most cost-effective and reliable read/write non-volatile random access memory. The MX26L6420 is packaged in 44SOP, 48-pin TSOP, 48-ball CSP and 63-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. MXIC's MTP EPROMTM technology reliably stores memory contents even after 100 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The standard MX26L6420 offers access time as fast as 90ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX26L6420 has separate chip enable (CE) and output enable OE controls. MXIC's MTP EPROMTM augment EPROM functionality with in-circuit electrical erasure and programming. The MX26L6420 uses a command register to manage this functionality. The MX26L6420 uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/ Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epiprocess. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V. P/N:PM0823 REV. 0.5, JAN. 29, 2002 1 MX26L6420 PIN CONFIGURATION 48 CSP Ball pitch=0.75mm for MX26L6420XA (TOP view, Ball down) 1 2 3 4 5 6 7 8 A A13 A11 A8 ACC NC A19 A7 A4 B A14 A10 WE RESET A18 A17 A5 A2 C A15 A12 A9 A21 A20 A6 A3 A1 D A16 Q14 Q5 Q11 Q2 Q8 CE A0 E V I/O Q15 Q6 Q12 Q3 Q9 Q0 GND F GND Q7 Q13 Q4 VCC Q10 Q1 OE 8.0 mm 13.0 mm 63 CSP Ball pitch=0.8mm for MX26L6420XB(TOP view, Ball down) 13.0 mm 8 NC NC 7 NC NC A13 A12 A14 A15 A16 VIO Q15 GND 6 A9 A8 A10 A11 Q7 Q14 Q13 Q6 5 WE RESET A21 A19 Q5 Q12 VCC Q4 4 NC ACC A18 A20 Q2 Q10 Q11 Q3 3 A7 A17 A6 A5 Q0 Q8 Q9 Q1 A3 A4 A2 A1 A0 CE OE GND NC* NC* NC* NC* 8.0 mm 2 NC* 1 NC* NC* A B C D E F G H J K NC* NC* NC* NC* L M * Ball are shorted together via the substrate but not connected to the die. P/N:PM0823 REV. 0.5, JAN. 29, 2002 2 MX26L6420 48 TSOP A21 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MX26L6420 44 SOP 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 WE GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE RESET ACC VCC A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME Address Input Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input RESET VCC ACC V I/O Hardware Reset Pin, Active Low +3.0V single power supply Hardware Acceleration Pin I/O power supply (For 48 TSOP and 63-CSP package only) Device Ground Pin Not Connected Internally GND NC MX26L6420 A16 VI/O GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0 LOGIC SYMBOL PIN DESCRIPTION SYMBOL A0~A21 Q0~Q15 CE WE OE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 21 16 A0-A21 Q0-Q15 CE OE WE RESET ACC P/N:PM0823 REV. 0.5, JAN. 29, 2002 3 MX26L6420 BLOCK DIAGRAM WRITE CE OE WE CONTROL PROGRAM/ERASE STATE INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) LATCH A0-A21 BUFFER FLASH REGISTER ARRAY ARRAY Y-DECODER AND X-DECODER ADDRESS STATE MX26L6420 Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15 I/O BUFFER P/N:PM0823 REV. 0.5, JAN. 29, 2002 4 MX26L6420 ming and erase operations. All address are latched on the falling edge of WE or CE, whichever happens later. All data are latched on rising edge of WE or CE, whichever happens first. AUTOMATIC PROGRAMMING The MX26L6420 is word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX26L6420 is less than 150 seconds. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX26L6420 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. After the state machine has completed its task, it will allow the command register to respond to its full command set. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 90 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the program- P/N:PM0823 REV. 0.5, JAN. 29, 2002 5 MX26L6420 Table 1 BUS OPERATION(1) Operation CE OE WE RESET Address Q15~Q0 Read L L H H AIN DOUT Write(Note 1) L H L H AIN DIN VCC±0.3V X X VCC±0.3V X High-Z Output Disable L H H H X High-Z Reset X X X L X High-Z Standby Legend: L=Logic LOW=VIL,H=Logic High=VIH,VID=12.0±0.5V,X=Don't Care, AIN=Address IN, DIN=Data IN, DOUT=Data OUT Notes: 1. When the ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. Table 2. AUTOSELECT CODES (High Voltage Method) A5 Operation CE OE WE A0 A1 A8 to A6 A2 Read Silicon ID to A14 A9 A7 to A15~A21 Q15~Q0 A10 L L H L L X L X VID X X00 C2H L L H H L X L X VID X X 22FCH Manufactures Code Read Silicon ID Device Code Secured Silscon Sector Indicator xx88h L L H H H X L Bit (Q7) X VID X X (factory locked) xx08h (non-factory locked) P/N:PM0823 REV. 0.5, JAN. 29, 2002 6 MX26L6420 REQUIREMENTS FOR READING ARRAY DATA STANDBY MODE MX26L6420 can be set into Standby mode with two different approaches. One is using both CE and RESET pins and the other one is using RESET pin only. To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ± 0.3V. Under this condition, the current consumed is less than 50uA (typ.). If both of the CE and RESET are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby currect will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE = "H" until the operation is complated. The device can be read with standard access time (tCE) from either of these standby modes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory contect occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. When using only RESET, a CMOS standby mode is achieved with RESET input held at Vss ± 0.3V, Under this condition the current is consumed less than 50uA (typ.). Once the RESET pin is taken high,the device is back to active without recovery delay. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase memory , the system must drive WE and CE to VIL, and OE to VIH. In the standby mode the outputs are in the high impedance state, independent of the OE input. An erase operation can erase the entire device. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data."section has details on erasing the entire chip. MX26L6420 is capable to provide the Automatic Standby Mode to restrain power consumption during read-out of data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To active this mode, MX26L6420 automatically switch themselves to low power mode when MX26L6420 addresses remain stable during access time of tACC+30ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 50uA (CMOS level). After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal reqister (which is separate from the memory array) on Q15-Q0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence section for more information. OUTPUT DISABLE ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. P/N:PM0823 REV. 0.5, JAN. 29, 2002 7 MX26L6420 RESET OPERATION Table 3 VCC / VI/O Voltage Range The RESET pin provides a hardware method of resetting the device to reading array data. When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET pluse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitated once the device is ready to accept another command sequence, to ensure data integrity Part No. VCC=2.7V to 3.6VVCC=2.7V to 3.6V VI/O=2.7V to 3.6VVI/O=1.65V to 2.6V MX26L6420-90 90ns 100ns MX26L6420-12 120ns 130ns Notes: Typical values measured at VCC=2.7V to 3.6V, VI/O=2.7V to 3.6V Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater. DATA PROTECTION The MX26L6420 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. The RESET pin may be tied to system reset circuitry. A system reset would that also reset the MTP EPROM. Refer to the AC Characteristics tables for RESET parameters and to Figure 14 for the timing diagram. SILICON ID READ OPERATION MTP EPROM are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. EPROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. SECURED SILICON SECTOR The MX26L6420 features a Flash memory region where the system may access through a command sequence to create a permant part identification as so called Electronic Serial Number (ESN) in the device. Once this region is programmed, any further modification on the region is impossible. The secured silicon sector is a 512 words in length, and uses a Secured Silicon Sector Indicator Bit (Q7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevent duplication of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. MX26L6420 provides hardware method to access the silicon ID read operation. Which method requires VID on A9 pin, VIL on CE, OE, A6, and A1 pins. Which apply VIL on A0 pin, the device will output MXIC's manufacture code of C2H. Which apply VIH on A0 pin, the device will output MX26L6420 device code of 22FCH. The MX26L6420 offers the device with Secured Silicon Sector either factory locked or custor lockable. The factory-locked version is always protected when shipped from the factory , and has the Secured Silicon Sector Indicator Bit permanently set to a "1". The customerlockable version is shipped with the Secured Silicon Sector unprotected, allowing customer to utilize that sector in any form they prefer. The customer-lockable ver- VI/O PIN OPERATION MX26L6420 is capable to provide the I/O prower supply (VI/O) pin to control Input/Output voltage levels of the device. The data outputs and voltage tolerated at its data input is determined by the voltage on the VI/O pin. This device is allows to operate in 1.8V or 3V system as required. P/N:PM0823 REV. 0.5, JAN. 29, 2002 8 MX26L6420 sion has the secured sector Indicator Bit permanently set to a "0". Therefore, the Secured Silicon Sector Indicator Bit permanently set to a "0". Therefore, the Second Silicon Sector Indicator Bit prevents customer, lockable device from being used to replace devices that are factory locked. FACTORY LOCKED:Secured Silicon Sector Programmed and Protected At the Factory In device with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. A factory locked device has an 8-word random ESN at address 000000h-000007h. The system access the Secured Silicon Sector through a command sequence (refer to "Enter Secured Silicon/ Exit Secured Silicon Sector command Sequence). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the address normally occupied by the address 000000h-0001FFh. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending command to address 000000h-0001FFFh. CUSTOMER LOCKABLE:Secured Silicon Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 512-word Secured Silicon Sector. Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. LOW VCC WRITE INHIBIT When VCC is less than VLKO the device does not accept any write cycles. This protects dataduring VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater thanVLKO. The system must provide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLKO. The Secured Silicon Sector area can be protected using the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command sequence. This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that method is only applicable to the Secured Silicon Sector. WRITE PULSE "GLITCH" PROTECTION Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. POWER-UP SEQUENCE The MX26L6420 powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. P/N:PM0823 REV. 0.5, JAN. 29, 2002 9 MX26L6420 SOFTWARE COMMAND DEFINTIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 4 defines the valid register command sequences. Either of the two reset command sequences will reset the device(when applicable). All addresses are latched on the falling edge of WE or CE, whichever happens later. All data are latched on rising edge of WE or CE, whichever happens first. TABLE4. MX26L6420 COMMAND DEFINITIONS Command First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Bus Cycle Cycle Cycle Cycle Cycle Cycle Addr Data Addr Cycle Data Addr Data Addr Data Read(Note 5) 1 RA RD Reset(Note 6) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 C2 Device ID 4 555 AA 2AA 55 555 90 X01 22FC Secured Sector 4 555 AA 2AA 55 555 90 x03 see Addr Data Addr Data Autoselect(Note 7) Factory Protect Enter Secured Silicon Note9 3 555 AA 2AA 55 555 88 4 555 AA 2AA 55 555 90 xxx 00 Porgram 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 555 80 555 AA Sector Exit Secured Silicon Sector Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. 2AA 55 555 10 PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse. Notes: 1.See Table 1 for descriptions of bus operations. 2.All values are in hexadecimal. 3.Except when reading array or autoselect data, all bus cycles are write operation. 4.Address bits are don't care for unlock and command cycles, except when PA is required. 5.No unlock or command cycles required when device is in read mode. 6.The Reset command is required to return to the read mode when the device is in the autoselect mode or if Q5 goes high. 7.The fourth cycle of the autoselect command sequence is a read cycle. 8.In the third and fourth cycles of the command sequence, set A21=0. 8.Command is valid when device is ready to read array data or when device is in autoselect mode. 9.The data is 88h for factory locked and 08h for non-factory locked. P/N:PM0823 REV. 0.5, JAN. 29, 2002 10 MX26L6420 by writing two unlock cycles, followed by the SILICON ID READ command. The device then enters the SILICON ID READ mode, and the system may read at any address any number of times, without init iating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. The system must write the reset command to exit the autoselect mode and return to reading array data. The system must issue the reset command to re-enable the device for reading array data if Q5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. WORD PROGRAM COMMAND SEQUENCE The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide fur ther controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 4 shows the address and data requirements for the byte program command sequence. RESET COMMAND Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6. See "Write Operation Status" for information on these status bits. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins,however, the device ignores reset commands until the operation is complete. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Word Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command must be written to return to reading array data. If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data. Programming is allowed in any sequence. A bit cannot be programmed from a "0" back to a "1". Cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". SILICON ID READ COMMAND SEQUENCE The SILICON ID READ command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not. Table 4 shows the address and data requirements. This method is an alternative to that shown in Table 1, which is intended for EPROM programmers and requires VID on address bit A9. The SILICON ID READ command sequence is initiated P/N:PM0823 REV. 0.5, JAN. 29, 2002 11 MX26L6420 ACCELERATED PROGRAM OPERATIONS AUTOMATIC CHIP ERASE COMMAND The device offers accelerated program operations through the ACC pin. When the system asserts VHH on the ACC pin, the device automatically bypass the two "Unlock" write cycle. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. The device does not require the system to preprogram prior to erase. The Automatic Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 4 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. SETUP AUTOMATIC CHIP ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. The system can determine the status of the erase operation by using Q7, Q6. See "Write Operation Status" for information on these status bits. When the Automatic Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The MX26L6420 contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A6=VIL, A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A6=VIL, A1=VIL, A0=VIH returns the device code of 22FCH for MX26L6420. Figure 5 illustrates the algorithm for the erase operation.See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 4 for timing diagrams. TABLE 5. SILICON ID CODE Pins A0 A1 A6 Q15 | Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Manufacture code VIL VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H Device code for MX26L6420 VIH VIL VIL 22H 1 1 1 1 1 1 1 0 22FCH P/N:PM0823 REV. 0.5, JAN. 29, 2002 12 MX26L6420 WRITE OPERSTION STATUS The device provides several bits to determine the status of a write operation: Q5, Q6, Q7. Table 10 and the following subsections describe the functions of these bits. Q7, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 6. Write Operation Status Status Q7 Q6 Q5 Note1 In Progress Word Program in Auto Program Algorithm Auto Erase Algorithm Exceeded Word Program in Auto Program Algorithm Time Limits Auto Erase Algorithm Q7 Toggle 0 0 Toggle 0 Q7 Toggle 1 0 Toggle 1 Notes: 1. Performing successive read operations from any address will cause Q6 to toggle. P/N:PM0823 REV. 0.5, JAN. 29, 2002 13 MX26L6420 Q7: Data Polling Q5:Program/Erase Timing The Data Polling bit, Q7, indicates to the host sys-tem whether an Automatic Algorithm is in progress or completed. Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence. Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming during Er ase Suspend. When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program address to read valid status information on Q7. If this time-out condition occurs during chip erase operation, it specifies that device is bad and it may not be reused. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. During the Automatic Erase algorithm, Data Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete. Data Polling produces a "1" on Q7. This is analogous to the complement/true datum output described for the Automatic Program algorithm: the erase function changes all the bits to "1" prior to this, the device outputs the "complement,” or "0". If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad. If this time-out condition occurs during the word programming operation, the word is bad and maynot be reused, (other word are still functional and can be reused). After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchr onously with Q0-Q6 while Output Enable (OE) is asserted low. Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence(prior to the program or erase operation). During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. Table 6 shows the outputs for Toggle Bit I on Q6. P/N:PM0823 REV. 0.5, JAN. 29, 2002 14 MX26L6420 ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC Ambient Temperature with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE, and RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Commercial (C) Devices Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices Ambient Temperature (TA ). . . . . . . . . . -40°C to +85°C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 7. 2. Minimum DC input voltage on pins A9, OE, and RESET is -0.5 V. During voltage transitions, A9, OE, and RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Rat-ings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. P/N:PM0823 REV. 0.5, JAN. 29, 2002 15 MX26L6420 °C, VCC=2.7V~3.6V DC CHARACTERISTICS TA=0° °C to 70° Para- VI/O=2.7V~3.6V meter Description Test Conditions I LI VIN = VSS to VCC , Input Load Current (Note 1) Min Typ Max VI/O=1.65V~2.6V Min Typ Max Unit ±1.0 ±1.0 uA 35 35 uA ±1.0 ±1.0 uA VCC = VCC max I LIT A9 Input Load Current VCC=VCC max; A9 = 12.5V I LO Output Leakage Current VOUT = VSS to VCC , VCC= VCC max ICC1 VCC Active Read Current CE= VIL, OE = VIH 5 MHz (Notes1, 2) ICC2 VCC Active Write Current 1 MHz CE= V IL , OE = V IH 17 25 17 25 mA 4 7 4 7 mA 26 30 26 30 mA 30 100 30 100 uA (Notes 1, 3, 4) ICC3 ICC4 VCC Standby Current (CMOS) CE,RESET, (Note 1) ACC=VCC ± 0.3V VCC Standby Current (TTL) CE=VIH 0.5 1 0.5 1 mA RESET = V SS ± 0.3 V, 0.2 5 0.2 5 uA Acc pin 5 10 5 10 mA Vcc pin 15 30 15 30 mA 0.4 V (Note 1) ICC5 VCC Reset Current (Note 1) ACC = VCC ± 0.3 V IACC ACC Accelerated Program CE=VIL, OE=VIH Current, Word VIL Input Low Voltage -0.5 VIH Input High Voltage 0.7xVcc VHH Voltage for ACC 0.8 Vcc+0.3 VI/O-0.4 V VCC = 3.0 V ± 10% 11.5 12.5 11.5 12.5 V 11.5 12.5 11.5 12.5 V 0.45 V Program Acceleration VID Voltage for Autoselect VCC = 3.0 V ± 10% VOL Output Low Voltage IOL= 4.0mA,VCC=VCC min 0.45 VOH1 Output High Voltage IOH=-2.0mA,VCC=VCC min 0.85VI/O 0.85VI/O V VOH2 IOH=-100uA,VCC=VCC min VI/O-0.4 VI/O-0.4 V VLKO Low V CC Lock-Out Voltage 2.3 2.5 2.3 2.5 V (Note 4) Notes: 1. Maximum ICC specifications are tested with VCC = VCC max. 2. The ICC current listed is typically is less than 2 mA/MHz, with OE at V IH . Typical specifications are for VCC = 3.0 V. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Not 100% tested. P/N:PM0823 REV. 0.5, JAN. 29, 2002 16 MX26L6420 SWITCHING TEST CIRCUITS DEVICE UNDER TEST SPECIFICATIONS Test Condition 90 120 Output Load 1 TTL gate Output Load Capacitance, CL 30 100 (including jig capacitance) Input Rise and Fall Times 5 Input Pulse Levels 0.0-3.0 Input timing measurement 1.5 reference levels Output timing measurement 1.5 reference levels 2.7K ohm 3.3V TEST CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT Unit pF ns V V V KEY TO SWITCHING WAVEFORMS WAVEFROM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State(High Z) SWITCHING TEST WAVEFORMS 3.0V 1.5V Measurement Level VIO/2 0.0V INPUT OUTPUT P/N:PM0823 REV. 0.5, JAN. 29, 2002 17 MX26L6420 °C, VCC=2.7V~3.6V AC CHARACTERISTICS TA=0° °C to 70° Symbol DESCRIPTION CONDITION 90 120 Unit tACC Address to output delay CE=VIL MAX 90 120 ns OE=VIL MAX 90 120 ns OE=VIL tCE Chip enable to output delay tOE Output enable to output delay MAX 34 44 ns tDF OE High to output float(Note1) MAX 25 35 ns tOH Output hold time of from the rising edge of MIN 0 0 ns Address, CE, or OE, whichever happens first tRC Read cycle time (Note 1) MIN 90 120 ns tWC Write cycle time (Note 1) MIN 90 120 ns tCWC Command write cycle time(Note 1) MIN 90 120 ns tAS Address setup time MIN 0 0 ns tAH Address hold time MIN 45 50 ns tDS Data setup time MIN 45 50 ns tDH Data hold time MIN 0 0 ns tVCS Vcc setup time(Note 1) MIN 50 50 us tCS Chip enable setup time MIN 0 0 ns tCH Chip enable hold time MIN 0 0 ns tOES Output enable setup time (Note 1) MIN 0 0 ns tOEH Output enable hold time (Note 1) Read MIN 0 0 ns Toggle & MIN 10 10 ns Data Polling tWES WE setup time MIN 0 0 ns tWEH WE hold time MIN 0 0 ns tCEP CE pulse width MIN 45 50 ns tCEPH CE pulse width high MIN 30 30 ns tWP WE pulse width MIN 35 50 ns tWPH WE pulse width high MIN 30 30 ns tOLZ Output enable to output low Z MAX 30 40 ns tWHGL WE high to OE going low MIN 30 30 ns Note: 1.Not 100% Tested 2.tr = tf = 5ns P/N:PM0823 REV. 0.5, JAN. 29, 2002 18 MX26L6420 Fig 1. COMMAND WRITE OPERATION VCC Addresses 5V VIH ADD Valid VIL tAH tAS WE VIH VIL tOES tWPH tWP tCWC CE VIH VIL tCS OE tCH VIH tDS VIL tDH VIH Data DIN VIL READ/RESET OPERATION Fig 2. READ TIMING WAVEFORMS tRC VIH Addresses ADD Valid VIL tCE CE VIH VIL WE VIH tOEH VIL tDF tOE tOLZ VIH OE VIL tACC Outputs VOH HIGH Z tOH DATA Valid HIGH Z VOL P/N:PM0823 REV. 0.5, JAN. 29, 2002 19 MX26L6420 °C, VCC=2.7V~3.6V AC CHARACTERISTICS TA=0° °C to 70° Parameter Description Test Setup All Speed Options Unit tREADY RESET PIN Low (NOT During Automatic MAX 500 ns Algorithms) to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 10 us tRP2 RESET Pulse Width (NOT During Automatic Algorithms) MIN 500 ns tRH RESET High Time Before Read(See Note) MIN 50 ns Note:Not 100% tested Fig 3. RESET TIMING WAVFORM CE, OE tRH RESET tRP2 tReady Reset Timing NOT during Automatic Algorithms RESET tRP1 Reset Timing during Automatic Algorithms P/N:PM0823 REV. 0.5, JAN. 29, 2002 20 MX26L6420 ERASE/PROGRAM OPERATION Fig 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC 2AAh Address Read Status Data tAS VA 555h VA tAH CE tCH tGHWL OE tWHGL tWHWH2 tWP WE tCS tWPH tDS tDH 55h 10h In Progress Complete Data tVCS VCC P/N:PM0823 REV. 0.5, JAN. 29, 2002 21 MX26L6420 Fig 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Poll from system YES No DATA = FFh ? YES Auto Erase Completed P/N:PM0823 REV. 0.5, JAN. 29, 2002 22 MX26L6420 Fig 6. AUTOMATIC PROGRAM TIMING WAVEFORMS Program Command Sequence(last two cycle) tWC 555h Address Read Status Data (last two cycle) tAS PA PA PA tAH CE tCH tGHWL OE tWHGL tWHWH1 tWP WE tCS tWPH tDS tDH A0h PD Status DOUT Data tVCS VCC NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address Fig 7. Accelerated Program Timing Diagram (8.5V ~ 9.5V) VHH ACC VIL or VIH VIL or VIH tVHH tVHH P/N:PM0823 REV. 0.5, JAN. 29, 2002 23 MX26L6420 Fig 8. CE CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase PA for program 555 for chip erase Data Polling Address PA tWC tAS tAH tWH WE tWHGL tGHEL OE tCP tWHWH1 or 2 CE tCPH tWS tDS tBUSY tDH DQ7 DOUT Data tRH A0 for program 55 for erase PD for program 10 for chip erase RESET NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence. P/N:PM0823 REV. 0.5, JAN. 29, 2002 24 MX26L6420 Fig 9. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system Increment Address No Verify Word Ok ? YES No Last Address ? YES Auto Program Completed P/N:PM0823 REV. 0.5, JAN. 29, 2002 25 MX26L6420 Fig 10. SECURED SILICON SECTOR PROTECTED ALOGORITHMS FLOWCHART START Enter Secured Silicon Sector Wait 1us Frist Wait Cycle Data=60h Second Wait Cycle Data=60h A6=0, A1=1, A0=0 Wait 300us NO Data=01h? YES Device Failed Write Reset Command Secured Sector Protect Complete P/N:PM0823 REV. 0.5, JAN. 29, 2002 26 MX26L6420 Fig 11. SILICON ID READ TIMING WAVEFORM VCC 3V ADD VID VIH A9 VIL ADD A0 VIH A1 VIH VIL tACC tACC VIL VIH ADD VIL CE VIH VIL WE VIH tCE VIL OE VIH tOE VIL tDF tOH tOH VIH DATA Q0-Q15 DATA OUT DATA OUT VIL 22FC 00C2H P/N:PM0823 REV. 0.5, JAN. 29, 2002 27 MX26L6420 WRITE OPERATION STATUS Fig 12. DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA VA VA tACC tCE CE tCH tOE OE tOEH tDF WE tOH Q7 Complement Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle. P/N:PM0823 REV. 0.5, JAN. 29, 2002 28 MX26L6420 Fig 13. Data Polling Algorithm START Read Q7~Q0 Add. = VA (1) Q7 = Data ? Yes No No Q5 = 1 ? Yes Read Q7~Q0 Add. = VA Yes Q7 = Data ? (2) No PASS FAIL Notes: 1.VA=valid address for programming. 2.Q7 should be rechecked even Q5="1"because Q7 may change simultaneously with Q5. P/N:PM0823 REV. 0.5, JAN. 29, 2002 29 MX26L6420 Fig 14. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALOGRITHMS) tRC VA VA Address VA VA tACC tCE CE tCH tOE OE tDF tOEH WE tOH Q6 High Z Valid Status (first raed) Valid Status Valid Data (second read) (stops toggling) Valid Data NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. P/N:PM0823 REV. 0.5, JAN. 29, 2002 30 MX26L6420 Fig 15. Toggle Bit Algorithm START Read Q7~Q0 Read Q7~Q0 (Note 1) NO Toggle Bit Q6 =Toggle? YES NO Q5=1? YES (Note 1,2) Read Q7~Q0 Twice Toggle Bit Q6= Toggle? YES Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: 1.Read toggle bit twice to determine whether or not it is toggling. 2.Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM0823 REV. 0.5, JAN. 29, 2002 31 MX26L6420 ERASE AND PROGRAMMING PERFORMANCE(1) LIMITS PARAMETER MIN. TYP.(2) MAX. UNITS Chip Erase Time 150 300 sec Word Programming Time 30 350 us Chip Programming Time 140 250 sec 7 210 us Accelerated Word Program Time Erase/Program Cycles Note: 100 Cycles 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25°C,3.3V. Additionally programming typicals assume checkerboard pattern. LATCHUP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V -100mA +100mA Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. CAPACITANCE °C to 70° °C, VCC=2.7V~3.6V TA=0° Parameter Symbol Parameter Description Test Set TYP MAX UNIT CIN Input Capacitance VIN=0 6 7.5 pF COUT Output Capacitance VOUT=0 8.5 12 pF CIN2 Control Pin Capacitance VIN=0 7.5 9 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25°C, f=1.0MHz DATA RETENTION Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150 10 Years 125 20 Years P/N:PM0823 REV. 0.5, JAN. 29, 2002 32 MX26L6420 ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX26L6420MC-90 90 MX26L6420MC-12 120 MX26L6420TC-90 90 Temperature Range Commerical Commerical Commerical MX26L6420TC-12 120 Commerical MX26L6420XAC-90 MX26L6420XAC-12 MX26L6420XBC-90 MX26L6420XBC-12 MX26L6420MI-90 MX26L6420MI-12 MX26L6420TI-90 90 120 90 120 90 120 90 Commerical Commerical Commerical Commerical Industrial Industrial Industrial MX26L6420TI-12 120 Industrial MX26L6420XAI-90 MX26L6420XAI-12 MX26L6420XBI-90 MX26L6420XBI-12 90 120 90 120 Industrial Industrial Industrial Industrial P/N:PM0823 Package type Ball Pitch 44 pin SOP 44 pin SOP 48 pin TSOP (Normal Type) 48 pin TSOP (Normal Type) 48 ball CSP 48 ball CSP 48 ball CSP 48 ball CSP 44 pin SOP 44 pin SOP 48 pin TSOP (Normal Type) 48 pin TSOP (Normal Type) 48 ball CSP 48 ball CSP 48 ball CSP 48 ball CSP 0.75 mm 0.75 mm 0.8 mm 0.8 mm 0.75 mm 0.75 mm 0.8 mm 0.8 mm REV. 0.5, JAN. 29, 2002 33 MX26L6420 PACKAGE INFORMATION 44-PIN SOP P/N:PM0823 REV. 0.5, JAN. 29, 2002 34 MX26L6420 48-PIN PLASTIC TSOP P/N:PM0823 REV. 0.5, JAN. 29, 2002 35 MX26L6420 48-Ball CSP P/N:PM0823 REV. 0.5, JAN. 29, 2002 36 MX26L6420 63-Ball CSP P/N:PM0823 REV. 0.5, JAN. 29, 2002 37 MX26L6420 REVISION HISTORY Revision No. Description 0.1 1.To added the VI/O voltage range and performance 2.To modify Autoselect code table 3.To added Deep power-down mode 4.To added chip erase algorithm flowchart 5.To added secured silicon sector protect Algorithm flowchart 6.To added 63CSP package type 7.Modify DC Characteristics table for VIL/VIH voltage when VI/O range is 1.8V~2.6V 0.2 1.To Added 0.8mm ball pitch 48 ball CSP package 2.To modify VI/O voltage range from 1.8V to 1.65V 3.To modify ICC4/tCS/tCH/tOLZ/tWHGL spec 4.To modify VCC standby current from 50uA to 30uA 5.To modify programming time word program:20us-->30us, chip program:80s-->140s 6.Cancel the deep power-down mode 0.3 1.To modify chip erase time from 45ns(typ.) to 90ns 2.To modify the ICC1 @5MHz:9/16mA-->17/25mA ICC1 @1MHz:2/4mA-->4/7mA 3.To correct the VHH to 12V±0.5V 0.4 1.To added 48-ball CSP & 63-ball CSP Package Information 0.5 1.To modify the content error P/N:PM0823 Page P1,7 P5 P9,10 P23 P24 P2 P16 Date JUL/31/2001 P1,2,33 P1,8,16 P16,18 P1,16 P1,32 SEP/26/2001 P11,16 P1,32 P16 P16 P36,37 P1,7,12 NOV/27/2001 DEC/17/2001 JAN/29/2002 REV. 0.5, JAN. 29, 2002 38 MX26L6420 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.