LINER MBRD340 42v, 2.5a, 2mhz step-down switching regulator with 2.7î¼a quiescent current Datasheet

LT3975
42V, 2.5A, 2MHz Step-Down
Switching Regulator with
2.7µA Quiescent Current
FEATURES
DESCRIPTION
Ultralow Quiescent Current:
2.7µA IQ at 12VIN to 3.3VOUT
n Low Ripple Burst Mode® Operation
Output Ripple < 15mVP-P
n Wide Input Range: Operation from 4.3V to 42V
n 2.5A Maximum Output Current
n Excellent Start-Up and Dropout Performance
n Adjustable Switching Frequency: 200kHz to 2MHz
n Synchronizable Between 250kHz to 2MHz
n Accurate Programmable Undervoltage Lockout
n Low Shutdown Current: I = 700nA
Q
n Power Good Flag
n Soft-Start Capability
n Thermal Shutdown Protection
n Current Limit Foldback with Soft-Start Override
n Saturating Switch Design: 75mΩ On Resistance
n Small, Thermally Enhanced 16-Lead MSOP Package
The LT®3975 is an adjustable frequency monolithic buck
switching regulator that accepts a wide input voltage range
up to 42V. Low quiescent current design consumes only
2.7µA of supply current while regulating with no load. Low
ripple Burst Mode operation maintains high efficiency at
low output currents while keeping the output ripple below
15mV in a typical application. The LT3975 can supply up
to 2.5A of load current and has current limit foldback to
limit power dissipation during short circuit. A low dropout
voltage of 500mV is maintained when the input voltage
drops below the programmed output voltage, such as
during automotive cold crank.
n
APPLICATIONS
n
n
n
Automotive Battery Regulation
Portable Products
Industrial Supplies
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
An internally compensated current mode topology is used
for fast transient response and good loop stability. A high
efficiency 75mΩ switch is included on the die along with a
boost Schottky diode and the necessary oscillator, control,
and logic circuitry. An accurate 1.02V threshold enable pin
can be driven directly from a microcontroller or used as a
programmable undervoltage lockout. A capacitor on the
SS pin provides a controlled inrush current (soft-start).
A power good flag signals when VOUT reaches 91.6% of
the programmed output voltage. The LT3975 is available
in a small 16-lead MSOP package with exposed pad for
low thermal resistance.
TYPICAL APPLICATION
No-Load Supply Current
3.3V Step-Down Converter
4.5
VIN
4.3V TO 42V
IN REGULATION
VIN
OFF ON
EN
BOOST
PG
SW
10µF
10nF
RT
SYNC
78.7k
f = 600kHz
PDS560
LT3975
SS
0.47µF 3.3µH
OUT
FB
GND
VOUT
3.3V
2.5A
1M
10pF
47µF
1210
576k
3975 TA01a
INPUT CURRENT (µA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
40
45
3975 TA01b
3975f
1
LT3975
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, EN Voltage (Note 3)............................................42V
BOOST Pin Voltage....................................................55V
BOOST Pin Above SW Pin..........................................30V
FB, RT, SYNC, SS Voltage............................................6V
PG Voltage.................................................................30V
OUT Voltage...............................................................16V
Operating Junction Temperature Range (Note 2)
LT3975E.............................................. –40°C to 125°C
LT3975I.............................................. –40°C to 125°C
LT3975H............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
PIN CONFIGURATION
TOP VIEW
FB
SS
OUT
BOOST
SW
SW
SW
NC
1
2
3
4
5
6
7
8
17
GND
16
15
14
13
12
11
10
9
SYNC
PG
RT
EN
VIN
VIN
VIN
NC
MSE PACKAGE
16-LEAD PLASTIC MSOP
θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3975EMSE#PBF
LT3975EMSE#TRPBF
3975
16-Lead Plastic MSOP
–40°C to 125°C
LT3975IMSE#PBF
LT3975IMSE#TRPBF
3975
16-Lead Plastic MSOP
–40°C to 125°C
LT3975HMSE#PBF
LT3975HMSE#TRPBF
3975
16-Lead Plastic MSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
Minimum Input Voltage
Dropout Comparator Threshold
Dropout Comparator Threshold Hysteresis
Quiescent Current from VIN
FB Pin Current
Feedback Voltage
CONDITIONS
(Note 3)
(VIN – OUT) Falling
VEN Low
VEN High, VSYNC Low
VEN High, VSYNC Low
VFB = 1.5V
MIN
l
430
l
l
l
FB Voltage Line Regulation
Switching Frequency
Minimum Switch On-Time
Minimum Switch Off-Time (Note 4)
4.3V < VIN < 40V (Note 3)
RT = 11.8k
RT = 41.2k
RT = 294k
TYP
4
500
25
0.7
1.6
1.183
1.173
1.8
0.8
160
0.1
1.197
1.197
0.0003
2.25
1
200
105
150
MAX
4.3
570
1.3
2.7
30
12
1.212
1.222
0.01
2.7
1.2
240
200
UNITS
V
mV
mV
µA
µA
µA
nA
V
V
%/V
MHz
MHz
kHz
ns
ns
3975f
2
LT3975
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
Switch Current Limit
Foldback Switch Current Limit
Switch VCESAT
Switch Leakage Current
Boost Schottky Forward Voltage
Boost Schottky Reverse Leakage
Minimum Boost Voltage (Note 5)
BOOST Pin Current
EN Voltage Threshold
EN Voltage Hysteresis
EN Pin Current
PG Threshold Offset from VFB
PG Hysteresis as % of Output Voltage
PG Leakage
PG Sink Current
SYNC Low Threshold
SYNC High Threshold
SYNC Pin Current
SS Source Current
CONDITIONS
VFB = 1V
VFB = 0V
ISW = 1A
MIN
4
ISH = 100mA
VREVERSE = 12V
l
ISW = 1A, VBOOST – VSW = 3V
EN Falling, VIN ≥ 4.3V
l
VFB Falling
VPG = 3V
VPG = 0.4V
VSYNC = 6V
VSS = 0.5V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3975E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. The
LT3975I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3975H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C. The junction temperature (TJ, in °C) is
calculated from the ambient temperature (TA, in °C) and power dissipation
(PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
0.92
5
l
125
0.6
0.9
TYP
5.4
3.3
80
0.02
730
0.02
1.3
20
1.02
60
0.2
8.4
1.7
0.02
480
1.0
1.18
0.1
1.8
MAX
6.8
1
2
1.8
32
1.12
20
13
1
1.5
2.6
UNITS
A
A
mV
μA
mV
μA
V
mA
V
mV
nA
%
%
µA
μA
V
V
nA
μA
Note 3: Minimum input voltage depends on application circuit.
Note 4: The LT3975 contains circuitry that extends the maximum duty
cycle if there is sufficient voltage across the boost capacitor. See the
Application Information section for more details.
Note 5: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the switch.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair device
reliability or permanently damage the device.
3975f
3
LT3975
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency at 5VOUT
TA = 25°C, unless otherwise noted.
Efficiency at 3.3VOUT
Efficiency at 5VOUT
95
85
90
90
80
80
85
75
80
75
70
65
60
fSW = 800kHz
VOUT = 5V
L = MSS1260-332NL
55
50
0
0.5
1.5
1
LOAD CURRENT (A)
70
65
60
55
50
12V
24V
36V
2
EFFICIENCY (%)
100
EFFICIENCY (%)
90
EFFICIENCY (%)
100
40
2.5
0.5
0
1.5
1
LOAD CURRENT (A)
2
3975 G01
90
4.5
0
0.01
2.5
30
0
0.01
0.1
10
100
1
LOAD CURRENT (mA)
12V
24V
36V
3.5
3.0
2.5
2.0
1.0
0
5
10
15 20 25 30 35
INPUT VOLTAGE (V)
3975 G03
Reference Voltage
1.225
1.205
1.195
1.185
1.180
65
35
5
95
TEMPERATURE (°C)
125
155
3975 G07
5
35
95
65
TEMPERATURE (°C)
155
VOUT = 5V
LOAD = 1A
0.03
0.10
0.05
0
–0.20
125
3975 G06
0.04
0.02
0.01
0
–0.01
–0.02
–0.03
–0.15
1.175
–25
Line Regulation
–0.10
–25
10
0.05
–0.05
1.190
DUE TO CATCH
DIODE LEAKAGE
100
1
–55
45
CHANGE IN VOUT (%)
CHANGE IN VOUT (%)
REFERENCE VOLTAGE (V)
40
VIN = 12V
VOUT = 5V
0.15
1.220
1.170
–55
1000
Load Regulation
0.20
1.200
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 3.3V
3975 G05
1.230
1.210
1000 10000
1.5
1000 10000
1.215
10
100
1
LOAD CURRENT (mA)
No-Load Supply Current
10000
INPUT CURRENT (µA)
INPUT CURRENT (µA)
EFFICIENCY (%)
50
40
0.1
3975 G03
70
60
12V
24V
36V
10
IN REGULATION
VOUT = 3.3V
4.0
10
30
No-Load Supply Current
80
FRONT PAGE APPLICATION
VOUT = 3.3V
L = MSS1260-332NL
50
40
3975 G02
Efficiency at 3.3VOUT
20
70
60
20
12V
24V
36V
FRONT PAGE APPLICATION
VOUT = 3.3V
L = MSS1260-332NL
45
fSW = 800kHz
VOUT = 5V
L = MSS1260-332NL
–0.04
0
0.5
1
1.5
INPUT VOLTAGE (V)
2
2.5
3975 G08
–0.05
5
10
15
20 25 30 35
INPUT VOLTAGE (V)
40
45
2975 G09
3975f
4
LT3975
TYPICAL PERFORMANCE CHARACTERISTICS
Thermal Derating
Switch Current Limit
VIN = 12V
VOUT = 5V
2.5
CURRENT LIMIT (A)
H-GRADE
1.5
LIMITED BY MAXIMUM
JUNCTION TEMPERATURE
θJA = 40°C/W
1.0
0.5
7.0
6
6.5
4
3
2
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
0.2
0
0.4
0.6
30% DUTY CYCLE
VSS = 3V
30% DUTY CYCLE
1
0.2
0.4
0.6
0.8
FB PIN VOLTAGE (V)
1.0
4
3
2
0
1.2
170
160
40
MINIMUM ON-TIME (ns)
BOOST PIN CURRENT (mA)
45
35
25
20
15
10
0
0.5
1
1.5
SS PIN VOLTAGE (V)
2.5
3
3975 G16
0
0.5
1
1.5
2.0
SWITCH CURRENT (A)
190
150
140
LOAD = 1A
120
110
100
LOAD = 2.5A
90
60
–55
3.0
Minimum Off-Time
VSYNC = 0V
fSW = 2MHz
130
2.5
3975 G15
200
VSYNC = 0V
fSW = 2MHz
180
170
160
150
LOAD = 2.5A
140
LOAD = 1A
130
120
110
70
1.5
2
1
SWITCH CURRENT (A)
0
2.5
2
80
5
0.5
100
Minimum On-Time
180
0
150
3975 G14
BOOST Pin Current
30
Switch VCESAT
50
3975 G13
50
155
200
VFB = 0V
1
0
125
VFB = 1V
VCESAT (mV)
CURRENT LIMIT (A)
CURRENT LIMIT (A)
250
5
2
95
65
35
TEMPERATURE (°C)
5
3975 G12
Soft-Start
3
0
3.0
–55 –25
1
0.8
3975 G11
6
4
0
4.5
DUTY CYCLE
Current Limit Foldback
5
5.0
3.5
3975 G10
6
5.5
4.0
1
0
–50 –25
30% DUTY CYCLE
6.0
5
MINIMUM OFF-TIME (ns)
LOAD CURRENT (A)
I-GRADE
2.0
Switch Current Limit
7
CURRENT LIMIT (A)
3.0
TA = 25°C, unless otherwise noted.
–25
65
35
5
95
TEMPERATURE (°C)
125
155
3975 G17
100
–55
–25
65
35
5
95
TEMPERATURE (°C)
125
155
3975 G18
3975f
5
LT3975
TYPICAL PERFORMANCE CHARACTERISTICS
RT Programmed Switching
Frequency
Switching Frequency
RT RESISTOR (kΩ)
720
660
600
540
480
Frequency Foldback
350
700
300
600
SWITCHING FREQUENCY (kHz)
780
SWITCHING FREQUENCY (kHz)
TA = 25°C, unless otherwise noted.
250
200
150
100
50
420
–55 –25
65
35
95
5
TEMPERATURE (°C)
125
0
155
EN RISING
2
1.06
1.05
1.04
1.01
–55 –25
95
65
35
TEMPERATURE (°C)
125
5
1.04
–55 –25
155
5.0
6.0
800
4.5
INPUT VOLTAGE (V)
155
Burst Frequency
VOUT = 3.3V
FRONT PAGE APPLICATION
TO RUN/TO START
4.0
125
900
SWITCHING FREQUENCY (kHz)
VOUT = 5V
fSW = 800kHz
4.5
95
65
35
TEMPERATURE (°C)
5
3975 G24
Minimum Input Voltage,
VOUT = 3.3V
5.0
FB FALLING
1.07
3975 G23
Minimum Input Voltage,
VOUT = 5V
INPUT VOLTAGE (V)
1.08
1.05
3975 G22
TO RUN/TO START
FB RISING
1.09
1.06
EN FALLING
1.02
155
1.2
1
1.10
1.03
1
5.5
0.8
0.6
0.4
FB PIN VOLTAGE (V)
1.11
PG THRESHOLD (V)
EN THRESHOLD (V)
INPUT VOLTAGE (V)
3
0.2
PG Thresholds
1.07
4
0
1.12
1.08
5
6.5
100
3975 G21
1.09
125
200
EN Thresholds
6
65
35
95
5
TEMPERATURE (°C)
300
3975 G20
Internal Undervoltage Lockout
(UVLO)
0
–55 –25
400
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
SWITCHING FREQUENCY (MHz)
3975 G19
500
3.5
3.0
VOUT = 5V
fSW = 800kHz
700
600
500
VOUT = 3.3V
fSW = 600kHz
400
300
200
100
4.0
0
0.5
1.5
1
LOAD CURRENT (A)
2
2.5
3975 G25
2.5
0
0.5
1.5
1
LOAD CURRENT (A)
2
2.5
3975 G26
0
0
20
40 60 80 100 120 140 160
LOAD CURRENT (mA)
3975 G27
3975f
6
LT3975
TYPICAL PERFORMANCE CHARACTERISTICS
SS Pin Current
Boost Capacitor Charger
160
140
2.2
120
2.0
1.8
1.6
1.4
1.2
Boost Diode Forward Voltage
1.6
VBST = VIN
1.4
BOOST DIODE VOLTAGE (V)
VSS = 0.5V
2.4
OUT PIN CURRENT (mA)
SS PIN CURRENT (µA)
2.6
TA = 25°C, unless otherwise noted.
100
80
60
40
95
65
35
TEMPERATURE (°C)
5
125
155
0
1.0
0.8
0.6
0.4
0.2
20
1.0
–55 –25
1.2
0
2
4
8
10 12
6
OUT PIN VOLTAGE (V)
3975 G28
14
16
0
0
1
0.5
1.5
BOOST DIODE CURRENT (A)
3975 G30
3975 G29
Dropout Comparator Thresholds
2
Start-Up/Dropout Performance
Start-Up/Dropout Performance
600
VIN
1V/DIV
DROPOUT THRESHOLD (mV)
580
560
540
VOUT RISING
520
VIN
1V/DIV
VIN
VOUT
VOUT
1V/DIV
VIN
VOUT
VOUT
1V/DIV
500
480
VOUT FALLING
460
2.5Ω LOAD
100ms/DIV
(2A IN REGULATION)
440
3975 G32
1kΩ LOAD
100ms/DIV
(5mA IN REGULATION)
3975 G33
420
400
–55
–25
65
35
5
95
TEMPERATURE (°C)
125
155
3975 G31
Full Frequency Switching
Waveforms
Burst Mode Switching Waveforms
Dropout Switching Waveforms
VSW
5V/DIV
VSW
5V/DIV
VSW
2V/DIV
IL
0.5A/DIV
IL
1A/DIV
IL
1A/DIV
VOUT
10mV/DIV
VOUT
20mV/DIV
VOUT
50mV/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 20mA
COUT = 47µF
5µs/DIV
3975 G34
VIN = 12V
VOUT = 3.3V
ILOAD = 1A
COUT = 47µF
1µs/DIV
3975 G35
VIN = 5V
5µs/DIV
VOUT SET FOR 5V
ILOAD = 0.5A
COUT = 47µF
3975 G36
3975f
7
LT3975
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient: 0.5A to 2.5A
Load Transient: 20mA to 2A
IL
1A/DIV
IL
1A/DIV
VOUT
200mV/DIV
VOUT
200mV/DIV
12VIN
3.3VOUT
COUT = 47µF
20µs/DIV
TA = 25°C, unless otherwise noted.
3975 G37
12VIN
3.3VOUT
COUT = 47µF
20µs/DIV
3975 G38
PIN FUNCTIONS
FB (Pin 1): The LT3975 regulates the FB pin to 1.197V.
Connect the feedback resistor divider tap to this pin. Also,
connect a phase lead capacitor between FB and the output.
Typically, this capacitor is 10pF.
SS (Pin 2): A capacitor is tied between SS and ground to
slowly ramp up the peak current limit of the LT3975 on
start-up. There is an internal 1.8μA pull-up on this pin.
The soft-start capacitor is actively discharged when the
EN pin goes low, during undervoltage lockout or thermal
shutdown. Float this pin to disable soft-start.
OUT (Pin 3): This pin is an input to the dropout comparator
which maintains a minimum dropout of 500mV between
VIN and OUT. The OUT pin connects to the anode of the
internal boost diode. This pin also supplies the current to
the LT3975’s internal regulator when OUT is above 3.2V.
Connect this pin to the output when the programmed
output voltage is less than 16V.
BOOST (Pin 4): This pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar
NPN power switch.
SW (Pins 5, 6, 7): The SW pin is the output of an internal
power switch. Connect these pins to the inductor, catch
diode, and boost capacitor.
NC (Pins 8, 9): No Connects. These pins are not connected
to internal circuitry.
VIN (Pins 10, 11, 12): The VIN pin supplies current to the
LT3975’s internal circuitry and to the internal power switch.
These pins must be locally bypassed.
EN (Pin 13): The part is in shutdown when this pin is low
and active when this pin is high. The hysteretic threshold
voltage is 1.08V going up and 1.02V going down. The
EN threshold is only accurate when VIN is above 4.3V. If
VIN is lower than 3.9V, internal UVLO will place the part
in shutdown. Tie to VIN if shutdown feature is not used.
RT (Pin 14): A resistor is tied between RT and ground to
set the switching frequency.
PG (Pin 15): The PG pin is the open-drain output of an
internal comparator. PGOOD remains low until the FB pin
is within 8.4% of the final regulation voltage. PGOOD is
valid when VIN is above 2V.
SYNC (Pin 16): This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode operation
at low output loads. Tie to a clock source for synchronization, which will include pulse skipping at low output
loads. When in pulse-skipping mode, quiescent current
increases to 11µA in a typical application at no load. Do
not float this pin.
GND (Exposed Pad Pin 17): Ground. The exposed pad
must be soldered to the PCB.
3975f
8
LT3975
BLOCK DIAGRAM
OUT
VIN
C1
INTERNAL 1.197V REF
EN
1.02V
+
–
+
SHDN
RT
0.5V
–
+
SLOPE COMP
OSCILLATOR
200kHz TO 2MHz
RT
SYNC
+
–
+
–
VIN
SWITCH
LATCH
BOOST
R
S
C3
Q
SW
Burst Mode
DETECT
PG
ERROR AMP
+
–
+
–
1.097V
VC
L1
VOUT
D1 C2
VC CLAMP
1.8µA
SS
SHDN
C4
OPT
FB
GND
R2
R1
3975 BD
C5
3975f
9
LT3975
OPERATION
The LT3975 is a constant frequency, current mode stepdown regulator. An oscillator, with frequency set by RT,
sets an RS flip-flop, turning on the internal power switch.
An amplifier and comparator monitor the current flowing
between the VIN and SW pins, turning the switch off when
this current reaches a level determined by the voltage at
VC (see Block Diagram). An error amplifier measures the
output voltage through an external resistor divider tied
to the FB pin and servos the VC node. If the error amplifier’s output increases, more current is delivered to the
output; if it decreases, less current is delivered. An active
clamp on the VC pin provides current limit. The VC pin is
also clamped by the voltage on the SS pin; soft-start is
implemented by generating a voltage ramp at the SS pin
using an external capacitor.
An internal regulator provides power to the control circuitry.
The bias regulator normally draws power from the VIN
pin, but if the OUT pin is connected to an external voltage higher than 3.2V, bias power will be drawn from the
external source (typically the regulated output voltage).
This improves efficiency.
If the EN pin is low, the LT3975 is shut down and draws
700nA from the input. When the EN pin falls below 1.02V,
the switching regulator will shut down, and when the EN
pin rises above 1.08V, the switching regulator will become
active. This accurate threshold allows programmable
undervoltage lockout.
The switch driver operates from either VIN or from the
BOOST pin. An external capacitor is used to generate a
voltage at the BOOST pin that is higher than the input
supply. This allows the driver to fully saturate the internal
bipolar NPN power switch for efficient operation.
To further optimize efficiency, the LT3975 automatically
switches to Burst Mode operation in light load situations.
Between bursts, all circuitry associated with controlling
the output switch is shut down reducing the input supply
current to 1.7μA. In a typical application, 2.7μA will be
consumed from the supply when regulating with no load.
The oscillator reduces the LT3975’s operating frequency
when the voltage at the FB pin is low. This frequency
foldback helps to control the output current during startup and overload.
The LT3975 can provide up to 2.5A of output current.
A current limit foldback feature throttles back the current limit during overload conditions to limit the power
dissipation. When SS is below 2V, the LT3975 overrides
the current limit foldback circuit to avoid interfering with
start-up. Thermal shutdown further protects the part from
excessive power dissipation, especially in elevated ambient
temperature environments.
If the input voltage decreases towards the programmed
output voltage, the LT3975 will start to skip switch-off
times and decrease the switching frequency to maintain
output regulation. As the input voltage decreases below
the programmed output voltage, the output voltage will be
regulated 500mV below the input voltage. This enforced
minimum dropout voltage limits the duty cycle and keeps
the boost capacitor charged during dropout conditions.
Since sufficient boost voltage is maintained, the internal
switch can fully saturate yielding low dropout performance.
The LT3975 contains a power good comparator which
trips when the FB pin is at 91.6% of its regulated value.
The PG output is an open-drain transistor that is off when
the output is in regulation, allowing an external resistor
to pull the PG pin high. Power good is valid when VIN is
above 2V. When the LT3975 is shut down the PG pin is
actively pulled low.
3975f
10
LT3975
APPLICATIONS INFORMATION
Achieving Ultralow Quiescent Current
To enhance efficiency at light loads, the LT3975 operates
in low ripple Burst Mode operation, which keeps the output capacitor charged to the desired output voltage while
minimizing the input quiescent current. In Burst Mode
operation the LT3975 delivers single pulses of current to
the output capacitor followed by sleep periods where the
output power is supplied by the output capacitor. When in
sleep mode the LT3975 consumes 1.7μA, but when it turns
on all the circuitry to deliver a current pulse, the LT3975
consumes several mA of input current in addition to the
switch current. Therefore, the total quiescent current will
be greater than 1.7μA when regulating.
As the output load decreases, the frequency of single current pulses decreases (see Figure 1) and the percentage
of time the LT3975 is in sleep mode increases, resulting
in much higher light load efficiency. By maximizing the
time between pulses, the converter quiescent current
gets closer to the 1.7μA ideal. Therefore, to optimize the
quiescent current performance at light loads, the current
in the feedback resistor divider and the reverse current
in the catch diode must be minimized, as these appear
to the output as load currents. Use the largest possible
feedback resistors and a low leakage Schottky catch diode
in applications utilizing the ultralow quiescent current
performance of the LT3975. The feedback resistors should
preferably be on the order of MΩ and the Schottky catch
900
SWITCHING FREQUENCY (kHz)
800
VOUT = 5V
fSW = 800kHz
700
600
500
VOUT = 3.3V
fSW = 600kHz
400
300
200
100
0
0
20
40 60 80 100 120 140 160
LOAD CURRENT (mA)
3975 F01
Figure 1. Switching Frequency in Burst Mode Operation
diode should have less than a few µA of typical reverse
leakage at room temperature. These two considerations
are reiterated in the FB Resistor Network and Catch Diode
Selection sections.
It is important to note that another way to decrease the
pulse frequency is to increase the magnitude of each
single current pulse. However, this increases the output
voltage ripple because each cycle delivers more power to
the output capacitor. The magnitude of the current pulses
was selected to ensure less than 15mV of output ripple in
a typical application. See Figure 2.
VSW
5V/DIV
IL
0.5A/DIV
VOUT
10mV/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 20mA
COUT = 47µF
5µs/DIV
3975 F02
Figure 2. Burst Mode Operation
While in Burst Mode operation, the burst frequency and
the charge delivered with each pulse will not change with
output capacitance. Therefore, the output voltage ripple will
be inversely proportional to the output capacitance. In a
typical application with a 22µF output capacitor, the output
ripple is about 10mV, and with a 47µF output capacitor
the output ripple is about 5mV. The output voltage ripple
can continue to be decreased by increasing the output
capacitance, though care must be taken to minimize the
effects of output capacitor ESR and ESL.
At higher output loads (above 150mA for the front page
application) the LT3975 will be running at the frequency
programmed by the RT resistor, and will be operating in
standard PWM mode. The transition between PWM and
low ripple Burst Mode operation is seamless, and will not
disturb the output voltage.
To ensure proper Burst Mode operation, the SYNC pin
must be grounded. When synchronized with an external
clock, the LT3975 will pulse skip at light loads. At very
3975f
11
LT3975
APPLICATIONS INFORMATION
light loads, the part will go to sleep between groups of
pulses, so the quiescent current of the part will still be low,
but not as low as in Burst Mode operation. The quiescent
current in a typical application when synchronized with an
external clock is 11µA at no load. Holding the SYNC pin
DC high yields no advantages in terms of output ripple or
minimum load to full frequency, so is not recommended.
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
 V

R1= R2  OUT – 1
 1.197V 
Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy.
The total resistance of the FB resistor divider should be
selected to be as large as possible to enhance low current
performance. The resistor divider generates a small load
on the output, which should be minimized to optimize the
low supply current at light loads.
When using large FB resistors, a 10pF phase lead capacitor
should be connected from VOUT to FB.
Setting the Switching Frequency
The LT3975 uses a constant frequency PWM architecture
that can be programmed to switch from 200kHz to 2MHz
by using a resistor tied from the RT pin to ground. A table
showing the necessary RT value for a desired switching
frequency is in Table 1.
To estimate the necessary RT value for a desired switching
frequency, use the equation:
RT =
51.1
( fSW )1.09
– 9.27
where RT is in kΩ and fSW is in MHz.
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz)
RT VALUE (kΩ)
0.2
294
0.3
182
0.4
130
0.6
78.7
0.8
54.9
1.0
41.2
1.2
32.4
1.4
26.1
1.6
21.5
1.8
17.8
2.0
14.7
2.2
12.4
Operating Frequency Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, minimum dropout voltage, and
maximum input voltage. The advantage of high frequency
operation is that smaller inductor and capacitor values
may be used. The disadvantages are lower efficiency, and
lower maximum input voltage. The highest acceptable
switching frequency (fSW(MAX)) for a given application
can be calculated as follows:
fSW(MAX) =
VOUT + VD
tON(MIN) ( VIN – VSW + VD )
where VIN is the typical input voltage, VOUT is the output
voltage, VD is the catch diode drop (~0.5V), and VSW is
the internal switch drop (~0.22V at max load). This equation shows that slower switching frequency is necessary
to safely accommodate high VIN/VOUT ratio. This is due
to the limitation on the LT3975’s minimum on-time. The
minimum on-time is a strong function of temperature.
Use the typical minimum on-time curve to design for an
application’s maximum temperature, while adding about
30% for part-to-part variation. The minimum duty cycle that
can be achieved taking minimum on time into account is:
DCMIN = fSW • tON(MIN)
where fSW is the switching frequency, the tON(MIN) is the
minimum switch on-time.
3975f
12
LT3975
APPLICATIONS INFORMATION
A good choice of switching frequency should allow adequate input voltage range (see next two sections) and
keep the inductor and capacitor values small.
Maximum Input Voltage Range
The LT3975 can operate from input voltages of up to 42V.
Often the highest allowed VIN during normal operation
(VIN(OP-MAX)) is limited by the minimum duty cycle rather
than the absolute maximum ratings of the VIN pin. It can
be calculated using the following equation:
VIN(OP-MAX) =
VOUT + VD
–V +V
fSW • tON(MIN) D SW
where tON(MIN) is the minimum switch on-time. A lower
switching frequency can be used to extend normal operation to higher input voltages.
The circuit will tolerate inputs above the maximum operating input voltage and up to the absolute maximum
ratings of the VIN and BOOST pins, regardless of chosen
switching frequency. However, during such transients
where VIN is higher than VIN(OP-MAX), the LT3975 will enter
pulse-skipping operation where some switching pulses are
skipped to maintain output regulation. The output voltage
ripple and inductor current ripple will be higher than in
typical operation. Do not overload when VIN is greater
than VIN(OP-MAX).
Minimum Input Voltage Range
The minimum input voltage is determined by either the
LT3975’s minimum operating voltage of 4.3V, its maximum
duty cycle, or the enforced minimum dropout voltage.
See the Typical Performance Characteristics section for
the minimum input voltage across load for outputs of
3.3V and 5V.
The duty cycle is the fraction of time that the internal
switch is on during a clock cycle. Unlike many fixed frequency regulators, the LT3975 can extend its duty cycle
by remaining on for multiple clock cycles. The LT3975
will not switch off at the end of each clock cycle if there
is sufficient voltage across the boost capacitor (C3 in
the Block Diagram). Eventually, the voltage on the boost
capacitor falls and requires refreshing. When this occurs,
the switch will turn off, allowing the inductor current to
recharge the boost capacitor. This places a limitation on
the maximum duty cycle as follows:
DCMAX =
β SW
β SW + 1
where βSW is equal to the beta of the internal power switch.
The beta of the power switch is typically about 50, which
leads to a DCMAX of about 98%. This leads to a minimum
input voltage of approximately:
VIN(MIN1) =
VOUT + VD
– VD + VSW
DCMAX
where VOUT is the output voltage, VD is the catch diode
drop, VSW is the internal switch drop and DCMAX is the
maximum duty cycle.
The final factor affecting the minimum input voltage is
the minimum dropout voltage. When the OUT pin is tied
to the output, the LT3975 regulates the output such that
it stays 500mV below VIN. This enforced minimum dropout voltage is due to reasons that are covered in the next
section. This places a limitation on the minimum input
voltage as follows:
VIN(MIN2) = VOUT + VDROPOUT(MIN)
where VOUT is the programmed output voltage and
VDROPOUT(MIN) is the minimum dropout voltage of 500mV.
Combining these factors leads to the overall minimum
input voltage:
VIN(MIN) = Max (VIN(MIN1), VIN(MIN2), 4.3V)
Minimum Dropout Voltage
To achieve a low dropout voltage, the internal power switch
must always be able to fully saturate. This means that the
boost capacitor, which provides a base drive higher than
VIN, must always be able to charge up when the part starts
up and then must also stay charged during all operating
conditions.
3975f
13
LT3975
APPLICATIONS INFORMATION
During start-up if there is insufficient inductor current, such
as during light load situations, the boost capacitor will be
unable to charge. When the LT3975 detects that the boost
capacitor is not charged, it activates a 100mA (typical)
pull-down on the OUT pin. If the OUT pin is connected to
the output, the extra load will increase the inductor current
enough to sufficiently charge the boost capacitor. When
the boost capacitor is charged, the current source turns
off, and the part may re-enter Burst Mode operation.
To keep the boost capacitor charged regardless of load
during dropout conditions, a minimum dropout voltage
is enforced. When the OUT pin is tied to the output, the
LT3975 regulates the output such that:
VIN – VOUT > VDROPOUT(MIN)
where VDROPOUT(MIN) is 500mV. The 500mV dropout voltage limits the duty cycle and forces the switch to turn off
regularly to charge the boost capacitor. Since sufficient
voltage across the boost capacitor is maintained, the switch
is allowed to fully saturate and the internal switch drop
stays low for good dropout performance. Figure 3 shows
the overall VIN to VOUT performances during start-up and
dropout conditions.
VIN
1V/DIV
VIN
VOUT
VOUT
1V/DIV
1kΩ LOAD
100ms/DIV
(5mA IN REGULATION)
3975 F03
Figure 3. VIN to VOUT Performance
It is important to note that the 500mV dropout voltage
specified is the minimum difference between VIN and
VOUT. When measuring VIN to VOUT with a multimeter,
the measured value will be higher than 500mV because
you have to add half the ripple voltage on the input and
half the ripple voltage on the output. With the normal
ceramic capacitors specified in the data sheet, this measured dropout voltage can be as high as 650mV at high
load. If some bulk electrolytic capacitance is added to the
input and output the voltage ripple, and subsequently the
measured dropout voltage, can be significantly reduced.
Additionally, when operating in dropout at high currents,
high ripple voltage on the input and output can generate
audible noise. This noise can also be significantly reduced
by adding bulk capacitance to the input and output to
reduce the voltage ripple.
Inductor Selection and Maximum Output Current
For a given input and output voltage, the inductor value
and switching frequency will determine the ripple current.
The ripple current increases with higher VIN or VOUT and
decreases with higher inductance and faster switching
frequency. A good first choice for the inductor value is:
L=
VOUT + VD
1.5 • fSW
where fSW is the switching frequency in MHz, VOUT is the
output voltage, VD is the catch diode drop (~0.5V) and L
is the inductor value is μH.
The inductor’s RMS current rating must be greater than
the maximum load current and its saturation current
should be about 30% higher. For robust operation in fault
conditions (start-up or overload) and high input voltage
(>30V), the saturation current should be above 8.5A.
To keep the efficiency high, the series resistance (DCR)
should be less than 0.1Ω, and the core material should
be intended for high frequency applications. Table 2 lists
several inductor vendors.
Table 2. Inductor Vendors
VENDOR
URL
Coilcraft
www.coilcraft.com
Sumida
www.sumida.com
Toko
www.tokoam.com
Würth Elektronik
www.we-online.com
Coiltronics
www.cooperet.com
Murata
www.murata.com
The inductor value must be sufficient to supply the desired
maximum output current (IOUT(MAX)), which is a function
of the switch current limit (ILIM) and the ripple current.
IOUT(MAX) = ILIM –
∆IL
2
3975f
14
LT3975
APPLICATIONS INFORMATION
The LT3975 limits its peak switch current in order to protect
itself and the system from overload and short-circuit faults.
The LT3975’s switch current limit (ILIM) is typically 5.4A at
low duty cycles and decreases linearly to 4.4A at DC = 0.8.
continuous. Discontinuous operation occurs when IOUT
is less than ΔIL/2.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
The LT3975 has a large peak current limit to ensure a 2.5A
max output current across duty cycle and current limit
distribution, as well as allowing a reasonable inductor
ripple current. During a short-circuit fault, having a large
current limit can lead to excessive power dissipation and
temperature rise in the LT3975, as well as the inductor and
catch diode. To limit this power dissipation, the LT3975
starts to fold back the current limit when the FB pin falls
below 0.8V. The LT3975 typically lowers the peak current
limit about 40% from 5.4A to 3.3A.
∆IL =
(1–DC) • ( VOUT + VD )
L • fSW
where fSW is the switching frequency of the LT3975, DC is
the duty cycle and L is the value of the inductor. Therefore,
the maximum output current that the LT3975 will deliver
depends on the switch current limit, the inductor value,
and the input and output voltages. The inductor value may
have to be increased if the inductor ripple current does
not allow sufficient maximum output current (IOUT(MAX))
given the switching frequency, and maximum input voltage
used in the desired application.
The optimum inductor for a given application may differ
from the one indicated by this simple design guide. A larger
value inductor provides a higher maximum load current and
reduces the output voltage ripple. If your load is lower than
the maximum load current, than you can relax the value of
the inductor and operate with higher ripple current. This
allows you to use a physically smaller inductor, or one with
a lower DCR resulting in higher efficiency. Be aware that if
the inductance differs from the simple rule above, then the
maximum load current will depend on the input voltage. In
addition, low inductance may result in discontinuous mode
operation, which further reduces maximum load current.
For details of maximum output current and discontinuous
operation, see Linear Technology’s Application Note 44.
Finally, for duty cycles greater than 50% (VOUT/VIN > 0.5),
a minimum inductance is required to avoid sub-harmonic
oscillations, see Application Note 19.
One approach to choosing the inductor is to start with
the simple rule given above, look at the available inductors, and choose one to meet cost or space goals. Then
use the equations above to check that the LT3975 will be
able to deliver the required output current. Note again
that these equations assume that the inductor current is
Current Limit Foldback and Thermal Protection
During start-up, when the output voltage and FB pin are low,
current limit foldback could hinder the LT3975’s ability to
start up into a large load. To avoid this potential problem,
the LT3975’s current limit foldback will be disabled until
the SS pin has charged above 2V. Therefore, the use of
a soft-start capacitor will keep the current limit foldback
feature out of the way while the LT3975 is starting up.
The LT3975 has thermal shutdown to further protect the
part during periods of high power dissipation, particularly
in high ambient temperature environments. The thermal
shutdown feature detects when the LT3975 is too hot
and shuts the part down, preventing switching. When the
thermal event passes and the LT3975 cools, the part will
restart and resume switching. A thermal shutdown event
actively discharges the soft-start capacitor.
Input Capacitor
Bypass the input of the LT3975 circuit with a ceramic capacitor of X7R or X5R type. Y5V types have poor performance
over temperature and applied voltage, and should not be
used. A 4.7μF to 10μF ceramic capacitor is adequate to
bypass the LT3975 and will easily handle the ripple current. Note that larger input capacitance is required when
a lower switching frequency is used (due to longer on
times). If the input power source has high impedance, or
there is significant inductance due to long wires or cables,
additional bulk capacitance may be necessary. This can
be provided with a low performance electrolytic capacitor.
3975f
15
LT3975
APPLICATIONS INFORMATION
Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage
ripple at the LT3975 and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
A 4.7μF capacitor is capable of this task, but only if it is
placed close to the LT3975 (see the PCB Layout section).
A second precaution regarding the ceramic input capacitor
concerns the maximum input voltage rating of the LT3975.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank
circuit. If the LT3975 circuit is plugged into a live supply,
the input voltage can ring to twice its nominal value, possibly exceeding the LT3975’s voltage rating. If the input
supply is poorly controlled or the user will be plugging
the LT3975 into an energized supply, the input network
should be designed to prevent this overshoot. See Linear
Technology Application Note 88 for a complete discussion.
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by the
LT3975 to produce the DC output. In this role it determines
the output ripple, so low impedance (at the switching
frequency) is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LT3975’s control loop. Ceramic capacitors have very low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
COUT =
200
VOUT • fSW
where fSW is in MHz, and COUT is the recommended output
capacitance in μF. Use X5R or X7R types. This choice will
provide low output ripple and good transient response.
Transient performance can be improved with a higher value
capacitor if combined with a phase lead capacitor (typically
10pF) between the output and the feedback pin. A lower
value of output capacitor can be used to save space and
cost but transient performance will suffer.
When choosing a capacitor, look carefully through the
data sheet to find out what the actual capacitance is under
operating conditions (applied voltage and temperature).
A physically larger capacitor or one with a higher voltage
rating may be required. Table 3 lists several capacitor
vendors.
Table 3. Recommended Ceramic Capacitor Vendors
MANUFACTURER
URL
AVX
www.avxcorp.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay Siliconix
www.vishay.com
TDK
www.tdk.com
Ceramic Capacitors
When in dropout, the LT3975 can excite ceramic capacitors at audio frequencies. At high load, this could be
unacceptable. Simply adding bulk input capacitance to
the input and output will significantly reduce the voltage
ripple and the audible noise generated at these nodes to
acceptable levels.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LT3975. As previously mentioned, a ceramic input capacitor combined
with trace or cable inductance forms a high quality (under
damped) tank circuit. If the LT3975 circuit is plugged into a
live supply, the input voltage can ring to twice its nominal
value, possibly exceeding the LT3975’s rating. If the input
supply is poorly controlled or the user will be plugging
the LT3975 into an energized supply, the input network
should be designed to prevent this overshoot. See Linear
Technology Application Note 88 for a complete discussion.
Catch Diode Selection
The catch diode (D1 from the Block Diagram) conducts
current only during the switch off time. Average forward
current in normal operation can be calculated from:
 V –V 
ID(AVG) = IOUT  IN OUT 
VIN


where IOUT is the output load current. The current rating of
the diode should be selected to be greater than or equal to
the application’s output load current, so that the diode is
3975f
16
LT3975
APPLICATIONS INFORMATION
robust for a wide input voltage range. A diode with even
higher current rating can be selected for the worst-case
scenario of overload, where the max diode current can then
increase to the typical peak switch current. Short circuit is
not the worst-case condition due to current limit foldback.
Peak reverse voltage is equal to the regulator input voltage.
For inputs up to 40V, a 40V diode is adequate.
An additional consideration is reverse leakage current.
When the catch diode is reversed biased, any leakage
current will appear as load current. When operating under
light load conditions, the low supply current consumed
by the LT3975 will be optimized by using a catch diode
with minimum reverse leakage current. Low leakage
Schottky diodes often have larger forward voltage drops
at a given current, so a trade-off can exist between low
load and high load efficiency. Often Schottky diodes with
larger reverse bias ratings will have less leakage at a given
output voltage than a diode with a smaller reverse bias
rating. Therefore, superior leakage performance can be
achieved at the expense of diode size. Table 4 lists several
Schottky diodes and their manufacturers.
BOOST and OUT Pin Considerations
Capacitor C3 and the internal boost Schottky diode (see the
Block Diagram) are used to generate a boost voltage that
is higher than the input voltage. In most cases a 0.47μF
capacitor will work well. The BOOST pin must be more
than 1.8V above the SW pin for best efficiency and more
than 2.6V above the SW pin to allow the LT3975 to skip
off times to achieve very high duty cycles. For outputs
between 3.2V and 16V, the standard circuit with the OUT
pin connected to the output (Figure 4a) is best. Below 3.2V
the internal Schottky diode may not be able to sufficiently
charge the boost capacitor. Above 16V, the OUT pin abs
max is violated. For outputs between 2.5V and 3.2V, an
external Schottky diode to the output is sufficient because
an external Schottky will have much lower forward voltage
drop than the internal boost diode.
Table 4. Schottky Diodes. The Reverse Current Values Listed
Are Estimates Based Off of Typical Curves for Reverse Current
vs Reverse Voltage at 25°C
VF at
3A MAX
25°C
(mV)
IR at
VR = 20V
25°C
(µA)
VR (V)
IAVE (A)
VF at 3A
TYP 25°C
(mV)
MBRA340T3
40
3
410
450
10
MBRS340T3
40
3
410
500
10
MBRD340
40
3
450
600
4
B340A
40
3
485
500
2
B340LA
40
3
400
450
100
B360A
60
3
600
700
50
PDS340
40
3
450
490
4
PDS360
60
3
570
620
0.45
SBR3U40P1
40
3
420
470
40
SBR3U30P1
30
3
390
430
100
SBR3M30P1
30
3
460
500
12
SBR3U60P1
60
3
580
650
1.7
DFLS240L
40
2
500
4
DFLS240
40
2
700
1
PART NUMBER
On Semiconductor
Diodes Inc.
For output voltages less than 2.5V, there are two options.
An external Schottky diode can charge the boost capacitor from the input (Figure 4c) or from an external voltage
source (Figure 4d). Using an external voltage source is the
better option because it is more efficient than charging the
boost capacitor from the input. However, such a voltage
rail is not always available in all systems. For output voltages greater than 16V, an external Schottky diode from
an external voltage source should be used to charge the
boost capacitor (Figure 4e). In applications using an external voltage source, the supply should be between 3.1V
and 16V. When using the input, the input voltage may not
exceed 27V. In all cases, the maximum voltage rating of
the BOOST pin must not be exceeded.
3975f
17
LT3975
APPLICATIONS INFORMATION
When the output is above 16V, the OUT pin can not be tied
to the output or the OUT pin abs max will be violated. It
should instead be tied to GND (Figure 4e). This is to prevent the dropout circuitry from interfering with switching
behavior and to prevent the 100mA active pull-down from
drawing power. It is important to note that when the output
is above 16V and the OUT pin is grounded, the dropout
circuitry is not connected, so the minimum dropout will
be about 1.5V, rather than 500mV. If the output is less than
3.2V and an external Schottky is used to charge the boost
capacitor, the OUT pin should still be tied to the output
VIN
VIN
BOOST
SW
VIN
VIN
LT3975
GND
BOOST
even though the minimum input voltage of the LT3975 will
be limited by the 4.3V minimum rather than the minimum
dropout voltage.
With the OUT pin connected to the output, a 100mA active load will charge the boost capacitor during light load
start-up and an enforced 500mV minimum dropout voltage
will keep the boost capacitor charged across operating
conditions (see Minimum Dropout Voltage section). This
yields excellent start-up and dropout performance. Figure 5
shows the minimum input voltage for 3.3V and 5V outputs.
SW
VIN
VIN
LT3975
OUT
VOUT
GND
(4a) For 3.2V ≤ VOUT ≤ 16V
BOOST
SW
LT3975
OUT
VOUT
GND
(4b) For 2.5V ≤ VOUT ≤ 3.2V
OUT
(4c) For VOUT < 2.5V, VIN < 27V
VS
VIN
VIN
BOOST
VS
SW
VIN
VIN
LT3975
GND
VOUT
BOOST
SW
LT3975
OUT
VOUT
GND
OUT
VOUT
3875 F04
(4d) For VOUT < 2.5V, 3.1V ≤ VS ≤ 16V
(4e) For VOUT > 16V, 3.1V ≤ VS ≤ 16V
Figure 4. Five Circuits for Generating the Boost Voltage
6.5
5.0
VOUT = 5V
fSW = 800kHz
4.5
TO RUN/TO START
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
6.0
5.5
5.0
4.5
4.0
VOUT = 3.3V
FRONT PAGE APPLICATION
TO RUN/TO START
4.0
3.5
3.0
0
0.5
1.5
1
LOAD CURRENT (A)
2
2.5
2.5
0
0.5
1.5
1
LOAD CURRENT (A)
2
3975 F05a
2.5
3975 F05b
Figure 5. The Minimum Input Voltage Depends on Output Voltage and Load Current
3975f
18
LT3975
APPLICATIONS INFORMATION
Enable and Undervoltage Lockout
The LT3975 is in shutdown when the EN pin is low and
active when the pin is high. The falling threshold of the
EN comparator is 1.02V, with 60mV of hysteresis. The EN
pin can be tied to VIN if the shutdown feature is not used.
Undervoltage lockout (UVLO) can be added to the LT3975
as shown in Figure 6. Typically, UVLO is used in situations where the input supply is current limited, or has a
relatively high source resistance. A switching regulator
draws constant power from the source, so source current increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating
at source voltages where the problems might occur. The
UVLO threshold can be adjusted by setting the values R3
and R4 such that they satisfy the following equation:
When operating in Burst Mode operation for light load
currents, the current through the UVLO resistor network
can easily be greater than the supply current consumed
by the LT3975. Therefore, the UVLO resistors should be
large to minimize their effect on efficiency at low loads.
LT3975
1.02V
EN
+
–
IL
1A/DIV
VOUT
1V/DIV
1ms/DIV
where VEN(THRESH) is the falling threshold of the EN pin,
which is approximately 1.02V, and where switching should
stop when VIN falls below VUVLO. Note that due to the
comparator’s hysteresis, switching will not start until the
input is about 6% above VUVLO.
R3
The external SS capacitor is actively discharged when
the EN pin is low, or during thermal shutdown. The active
pull-down on the SS pin has a resistance of about 150Ω.
VSS
0.5V/DIV
 R3 +R4 
VUVLO = VEN(THRESH) 
 R4 
VIN
capacitor generating a voltage ramp on the SS pin. The
SS pin clamps the internal VC node, which slowly ramps
up the current limit. Maximum current limit is reached
when the SS pin is about 1.5V or higher. By selecting a
large enough capacitor, the output can reach regulation
without overshoot. Figure 7 shows start-up waveforms
for a typical application with a 10nF capacitor on SS for
a 1.65Ω load when the EN pin is pulsed high for 7ms.
SHDN
R4
LT3975 F06
Figure 6. Undervoltage Lockout
Soft-Start
The SS pin can be used to soft start the LT3975 by throttling the maximum input current during start-up and reset.
An internal 1.8μA current source charges an external
3975 F07
Figure 7. Soft-Start Waveforms for the Front-Page Application
with a 10nF Capacitor on SS. EN Is Pulsed High for About 7ms
with a 1.65Ω Load Resistor
Synchronization
To select low ripple Burst Mode operation, tie the SYNC
pin below 0.5V (this can be ground or a logic output).
Synchronizing the LT3975 oscillator to an external frequency can be done by connecting a square wave (with
20% to 80% duty cycle) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.5V
and peaks above 1.5V (up to 6V).
The LT3975 will pulse skip at low output loads while synchronized to an external clock to maintain regulation. At
very light loads, the part will go to sleep between groups of
pulses, so the quiescent current of the part will still be low,
but not as low as in Burst Mode operation. The quiescent
current in a typical application when synchronized with an
external clock is 11µA at no load. Holding the SYNC pin
DC high yields no advantages in terms of output ripple or
minimum load to full frequency, so is not recommended.
Never float the SYNC pin.
3975f
19
LT3975
APPLICATIONS INFORMATION
Power Good Flag
The PG pin is an open-drain output which is used to indicate
to the user when the output voltage is within regulation.
When the output is lower than the regulation voltage by
more than 8.4%, as determined from the FB pin voltage,
the PG pin will pull low to indicate the power is not good.
Otherwise, the PG pin will go high impedance and can
be pulled logic high with a resistor pull-up. The PG pin is
only comparing the output voltage to an accurate reference when the LT3975 is enabled and VIN is above 4.3V.
When the part is shutdown, the PG is actively pulled low to
indicate that the LT3975 is not regulating the output. The
input voltage must be greater than 1.4V to fully turn-on
the active pull-down device. Figure 8 shows the status of
the PG pin as the input voltage is increased.
Shorted and Reversed Input Protection
If the inductor is chosen so that it won’t saturate excessively,
a LT3975 buck regulator will tolerate a shorted output and
the power dissipation will be limited by current limit foldback (see Current Limit Foldback and Thermal Protection
section). There is another situation to consider in systems
where the output will be held high when the input to the
4
PG PIN VOLTAGE (V)
The LT3975 may be synchronized over a 250kHz to 2MHz
range. The RT resistor should be chosen to set the LT3975
switching frequency 20% below the lowest synchronization
input. For example, if the synchronization signal will be
250kHz and higher, the RT should be selected for 200kHz.
To assure reliable and safe operation the LT3975 will only
synchronize when the output voltage is near regulation
as indicated by the PG flag. It is therefore necessary to
choose a large enough inductor value to supply the required
output current at the frequency set by the RT resistor (see
Inductor Selection section). The slope compensation is set
by the RT value, while the minimum slope compensation
required to avoid subharmonic oscillations is established
by the inductor size, input voltage and output voltage.
Since the synchronization frequency will not change the
slopes of the inductor current waveform, if the inductor
is large enough to avoid subharmonic oscillations at the
frequency set by RT, than the slope compensation will be
sufficient for all synchronization frequencies.
3
2
1
0
0
0.5 1 1.5 2 2.5 3 3.5
INPUT VOLTAGE (V)
4 4.5
5
3975 F08
Figure 8. PG Pin Voltage Versus Input Voltage when PG
Is Connected to 3V Through a 150k Resistor. The FB Pin
Voltage Is 1.15V
LT3975 is absent. This may occur in battery charging applications or in battery backup systems where a battery
or some other supply is diode ORed with the LT3975’s
output. If the VIN pin is allowed to float and the EN/UVLO
pin is held high (either by a logic signal or because it is
tied to VIN), then the LT3975’s internal circuitry will pull its
quiescent current through its SW pin. This is fine if your
system can tolerate a few μA in this state. If you ground
the EN pin, the SW pin current will drop to essentially
zero. However, if the VIN pin is grounded while the output
is held high, regardless of EN, parasitic diodes inside the
LT3975 can pull current from the output through the SW
pin and the VIN pin. Figure 9 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 10 shows
a sample component placement with trace, ground plane
and via locations, which serves as a good PCB layout
example. Note that large, switched currents flow in the
LT3975’s VIN and SW pins, the catch diode (D1), and the
input capacitor (C1). The loop formed by these components should be as small as possible. These components,
along with the inductor and output capacitor, should be
placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
3975f
20
LT3975
APPLICATIONS INFORMATION
High Temperature Considerations
D4
B360A
VIN
BOOST
VIN
EN
LT3975
GND
VOUT
SW
OUT
FB
+
BACKUP
3975 F09
Figure 9. Diode D4 Prevents a Shorted Input from Discharging
a Backup Battery Tied to the Output. It Also Protects the Circuit
from a Reversed Input. The LT3975 Runs Only When the Input
Is Present
SS
SYNC
VOUT
FB
OUT BST
SW
17
•••
•••
•• •• ••
•• •• ••
•• •• ••
•••
•••
•••
VOUT
PG
RT
VIN
EN
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT3975. The exposed pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3975.
Placing additional vias can reduce the thermal resistance
further. When operating at high ambient temperatures, the
maximum load current should be derated as the ambient
temperature approaches the maximum junction rating.
Power dissipation within the LT3975 can be estimated by
calculating the total power loss from an efficiency measurement and subtracting the catch diode loss and inductor
loss. The die temperature is calculated by multiplying the
LT3975 power dissipation by the thermal resistance from
junction to ambient.
Also keep in mind that the leakage current of the power
Schottky diode goes up exponentially with junction temperature. When the power switch is off, the power Schottky
diode is in parallel with the power converter’s output
filter stage. As a result, an increase in a diode’s leakage
current results in an effective increase in the load, and a
corresponding increase in the input quiescent current.
Therefore, the catch Schottky diode must be selected
with care to avoid excessive increase in light load supply
current at high temperatures.
3975 F10
Figure 10. Layout Showing a Good PCB Design
unbroken ground plane below these components. The SW
and BOOST nodes should be as small as possible. Finally,
keep the FB and RT nodes small so that the ground traces
will shield it from the SW and BOOST nodes. The exposed
pad on the bottom of the package must be soldered to
ground so that the pad acts as a heat sink. To keep thermal
resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT3975 to
additional ground planes within the circuit board and on
the bottom side.
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
3975f
21
LT3975
TYPICAL APPLICATIONS
5V Step-Down Converter
4V Step-Down Converter with a High Impedance Input Source
VIN
5.7V TO 42V
+
VIN
OFF ON
V
EN
BOOST
PG
SW
10µF
0.47µF 4.7µH
SS
OUT
RT
SYNC
10nF
10pF
54.9k
VIN
5.49M
CBULK
100µF
SW
0.47µF 4.7µH
PDS360
LT3975
OUT
RT
SYNC
47nF
10µF
10pF
47µF
1210
432k
3975 TA05
f = 800kHz
L = IHLP-2525EZ-01
12V Step-Down Converter
VOUT
4V
2.5A
1M
FB
GND
54.9k
3975 TA02
f = 800kHz
L = IHLP-2020CZ-01
BOOST
EN
499k
47µF
1210
316k
PG
SS
VOUT
5V
2.5A
1M
FB
GND
24V
+
PDS360
LT3975
–
2.5V Step-Down Converter
VIN
12.9V TO 42V
DFLS160
VIN
4.3V TO 42V
VIN
OFF ON
EN
BOOST
SW
PG
10µF
10nF
RT
SYNC
OFF ON
FB
GND
54.9k
VOUT
12V
2.5A
22µF
1210
×2
1M
110k
PDS360
LT3975
OUT
RT
SYNC
10pF
100µF
1210
909k
3975 TA06
f = 400kHz
L = IHLP-2525EZ-01
VIN
5.9V TO 18V
(42V TRANSIENTS)
VIN
BOOST
EN
4.7µF
SS
RT
SYNC
f = 2MHz
L = IHLP-2525CZ-01
VIN
FB
GND
OFF ON
150k
PGOOD
PG
OUT
DFLS160
VIN
4.3V TO 27V
SW
LT3975
14.7k
1.8V Step-Down Converter
0.47µF
2.2µH
PDS360
VOUT
2.5V
2.5A
1M
FB
GND
130k
3975 TA03
5V, 2MHz Step-Down Converter with Power Good
10nF
6.8µH
SS
10nF
0.47µF
SW
PG
10pF
f = 800kHz
L = IHLP-3232CZ-01
OFF ON
EN
10µF
OUT
BOOST
VIN
10µH
PDS360
LT3975
SS
0.47µF
22µF
1210
316k
3975 TA04
BOOST
PG
SW
10µF
VOUT
5V
2.5A
1M
10pF
EN
10nF
PDS360
LT3975
SS
RT
SYNC
97.6k
f = 500kHz
L = IHLP-2020CZ-01
0.47µF 3.3µH
OUT
VOUT
1.8V
2.5A
499k
FB
GND
10pF
100µF
1210
1M
3975 TA07
3975f
22
LT3975
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev E)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.23
(.206)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
8
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
0.305 ±0.038
(.0120 ±.0015)
TYP
16
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 ±0.076
(.011 ±.003)
REF
16151413121110 9
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0911 REV E
3975f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3975
TYPICAL APPLICATION
1.2V Step-Down Converter
DFLS160
VIN
4.3V TO 27V
(42V TRANSIENT)
3.3V
VIN
OFF ON
EN
BOOST
PG
SW
10µF
10nF
PDS360
LT3975
SS
RT
SYNC
0.47µF 4.7µH
OUT
VOUT
1.2V
2.5A
FB
GND
100µF
1210
130k
3975 TA08
f = 400kHz
L = IHLP-2525EZ-01
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT3480
36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode® Operation
VIN = 3.6V to 38V, Transients to 60V, VOUT(MIN) = 0.78V,
IQ = 70µA, ISD < 1µA, 3mm × 3mm DFN-10, MSOP-10E
LT3980
58V with Transient Protection to 80V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
VIN = 3.6V to 58V, Transients to 80V, VOUT(MIN) = 0.79V,
IQ = 75µA, ISD < 1µA, 3mm × 4mm DFN-16, MSOP-16E
LT3971
38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.8µA of Quiescent Current
VIN = 4.2V to 38V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3991
55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.8µA of Quiescent Current
VIN = 4.2V to 55V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3970
40V, 350mA (IOUT), 2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.5µA of Quiescent Current
VIN = 4.2V to 40V, VOUT(MIN) = 1.2V, IQ = 2.5µA, ISD < 0.7µA,
2mm × 3mm DFN-10, MSOP-10E
LT3990
62V, 350mA (IOUT), 2.2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.5µA of Quiescent Current
VIN = 4.2V to 62V, VOUT(MIN) = 1.2V, IQ = 2.5µA, ISD < 0.7µA,
3mm × 3mm DFN-10, MSOP-16E
3975f
24 Linear Technology Corporation
LT 0812 • PRINTED IN USA
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