TI MSP430F6778IPZR Polyphase metering soc Datasheet

ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x
MSP430F676x
MSP430F674x
www.ti.com
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
POLYPHASE METERING SoCs
FEATURES
1
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•
Accuracy < 0.1% Over 2000:1 Dynamic Range
for Phase Current
Meets or Exceeds ANSI C12.20 and IEC 62053
Standards
Support for Multiple Sensors Such as Current
Transformers, Rogowski Coils, or Shunts
Power Measurement for up to Three Phases
Plus Neutral
Dedicated Pulse Output Pins for Active and
Reactive Energy for Calibration
Four-Quadrant Measurement per Phase or
Cumulative
Exact Phase Angle Measurements
Digital Phase Correction for Current
Transformers
Temperature Compensated Energy
Measurements
40-Hz to 70-Hz Line Frequency Range Using
Single Calibration
Flexible Power Supply Options With Automatic
Switching
Display Operates at Very Low Power During
AC Mains Failure: 3 µA in LPM3
LCD Driver With Contrast Control for up to 320
Segments
Password-Protected Real-Time Clock With
Crystal Offset Calibration and Temperature
Compensation
Integrated Security Modules to Support AntiTamper and Encryption
Multiple Communication Interfaces for Smart
Meter Implementations
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High-Performance 25-MHz CPU With 32-Bit
Multiplier
Wide Input Supply Voltage Range:
3.6 V Down to 1.8 V
Ultra-Low Power Consumption During Energy
Measurement
– 2.9 mW at 10-MHz Operation (3 V)
Multiple Low-Power Modes
– Standby Mode (LPM3): 2.1 µA at 3 V,
Wakeup in Less Than 5 µs
– RTC Mode (LPM3.5): 0.34 µA at 3 V
– Shutdown Mode (LPM4.5): 0.18 µA at 3 V
Up to 512-KB Single-Cycle Flash
Up to 32-KB RAM With Single-Cycle Access
Up to Seven Independent 24-Bit Sigma-Delta
ADCs With Differential Inputs and Variable
Gain
System 10-Bit 200-ksps ADC
– Six Channels Plus Supply and Temperature
Sensor Measurement
Integrated Hardware AES-128 Module for
Encryption
Six Enhanced Communications Ports
– Configurable Between Four UART, Six SPI,
and Two I²C Interfaces
Four 16-Bit Timers With Nine Total
Capture/Compare Registers
128-Pin LQFP (PEU) Package With 90 I/O Pins
100-Pin LQFP (PZ) Package With 62 I/O Pins
Industrial Temperature Range of -40°C to 85°C
3-Phase Electronic Watt-Hour Meter
Development Tools
– EVM430-F6779 With SLAA577 App Note
– MSP430™ Energy Library
For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
TOTAL
Load
kWh
Sx, COMx
Phase C
VCC
MSP430F677x
Phase A
R33
RST
Phase B
LCDCAP
VSS
Px.x
Neutral
+
IA
CT
STATUS LEDs
ΣΔ Modulator
–
+
IB
CT
Px.y
ΣΔ Modulator
–
PULSE LEDs
+
CT
IC
ΣΔ Modulator
–
XIN
+
Ineutral
CT
32,768Hz
ΣΔ Modulator
–
VA
XOUT
AFE
+
USCIA0
UART or SPI
USCIA1
UART or SPI
USCIA2
UART or SPI
USCIA3
UART or SPI
USCIB0
I2C or SPI
USCIB1
I2C or SPI
ΣΔ Modulator
–
VB
+
ΣΔ Modulator
–
VC
+
VN
ΣΔ Modulator
–
Vref
Neutral
Phase B
Phase A
Phase C
Source From Utility
Figure 1. 3-Phase 4-Wire Star Connection Using MSP430F677x
2
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
DESCRIPTION
The Texas Instruments F677x family of polyphase metering SoCs are powerful, highly integrated solutions for
revenue meters that offer accuracy and low system cost with few external components. The F677x uses the lowpower MSP430 CPU with a 32-bit multiplier to perform all energy calculations, metering applications such as
tariff rate management, and communications with AMR and AMI modules.
The F677x features Texas Instruments' 24-bit sigma delta converter technology which provides better than 0.1%
accuracy. Family members include up to 512KB flash and 32KB RAM and an LCD controller with support for up
to 320 segments.
The ultra-low-power nature of the F677x means that the system power supply can be minimized to reduce overall
cost. Lowest standby power means that backup energy storage can be minimized and critical data retained
longer in case of a mains power failure.
The F677x family executes the Texas Instruments energy measurement software library which calculates all
relevant energy and power results. The energy measurement software library is available with the F677x at no
cost. Industry standard development tools and hardware platforms are available to speed development of meters
that meet all of the ANSI and IEC standards globally.
Family members available are summarized in Table 1.
Copyright © 2012–2013, Texas Instruments Incorporated
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MSP430F677x
MSP430F676x
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SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Table 1. Family Members
eUSCI
Device
Flash
(KB)
SRAM
(KB)
SD24_B
Converters
ADC10_A
Channels
Timer_A (1)
Channel A:
UART, IrDA,
SPI
Channel B:
SPI, I2C
I/O
Package
Type
MSP430F6779IPEU
512
32
7
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6778IPEU
512
16
7
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6777IPEU
256
32
7
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6776IPEU
256
16
7
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6775IPEU
128
16
7
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6769IPEU
512
32
6
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6768IPEU
512
16
6
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6767IPEU
256
32
6
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6766IPEU
256
16
6
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6765IPEU
128
16
6
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6749IPEU
512
32
4
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6748IPEU
512
16
4
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6747IPEU
256
32
4
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6746IPEU
256
16
4
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6745IPEU
128
16
4
6 ext, 2 int
3, 2, 2, 2
4
2
90
128 PEU
MSP430F6779IPZ
512
32
7
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6778IPZ
512
16
7
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6777IPZ
256
32
7
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6776IPZ
256
16
7
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6775IPZ
128
16
7
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6769IPZ
512
32
6
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6768IPZ
512
16
6
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6767IPZ
256
32
6
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6766IPZ
256
16
6
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6765IPZ
128
16
6
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6749IPZ
512
32
4
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6748IPZ
512
16
4
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6747IPZ
256
32
4
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6746IPZ
256
16
4
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
MSP430F6745IPZ
128
16
4
6 ext, 2 int
3, 2, 2, 2
4
2
62
100 PZ
(1)
4
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
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Copyright © 2012–2013, Texas Instruments Incorporated
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 2. Ordering Information (1)
TA
–40°C to 85°C
(1)
(2)
PACKAGED DEVICES (2)
PLASTIC 128-PIN LQFP (PEU)
PLASTIC 100-PIN LQFP (PZ)
MSP430F6779IPEU
MSP430F6779IPZ
MSP430F6778IPEU
MSP430F6778IPZ
MSP430F6777IPEU
MSP430F6777IPZ
MSP430F6776IPEU
MSP430F6776IPZ
MSP430F6775IPEU
MSP430F6775IPZ
MSP430F6769IPEU
MSP430F6769IPZ
MSP430F6768IPEU
MSP430F6768IPZ
MSP430F6767IPEU
MSP430F6767IPZ
MSP430F6766IPEU
MSP430F6766IPZ
MSP430F6765IPEU
MSP430F6765IPZ
MSP430F6749IPEU
MSP430F6749IPZ
MSP430F6748IPEU
MSP430F6748IPZ
MSP430F6747IPEU
MSP430F6747IPZ
MSP430F6746IPEU
MSP430F6746IPZ
MSP430F6745IPEU
MSP430F6745IPZ
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2012–2013, Texas Instruments Incorporated
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Functional Block Diagram – MSP430F677xIPEU, MSP430F676xIPEU, and MSP430F674xIPEU
XIN
XOUT
DVCC DVSS
AVCC AVSS
AUX1 AUX2 AUX3
PA
P1.x P2.x
RST/NMI
PB
P3.x P4.x
PC
P5.x P6.x
P7.x
PD
P8.x
PE
P9.x P10.x
PF
P11.x
(32kHz)
ACLK
Unified
Clock
System
512kB
256kB
128kB
32kB
16kB
Flash
RAM
SMCLK
MCLK
SYS
Watchdog
Port
Mapping
Controller
MPY32
CRC16
AES128
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
2×8 I/Os
I/O Ports
P9/P10
2×8 I/O
I/O Ports
P11
1×6 I/O
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×16 I/O
PF
1×6 I/O
Ta0
TA1
TA2
TA3
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
eUSCI_B0
eUSCI_B1
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 8+2)
PMM
Auxiliary
Supplies
JTAG/
SBW
Interface/
LDO
SVM/SVS
BOR
Port PJ
SD24_B
7 Channel
6 Channel
4 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
REF
8MUX
Up to 320
Segments
Reference
1.5V, 2.0V,
2.5V
RTC_CE
Timer_A
3 CC
Registers
PJ.x
Timer_A
2 CC
Registers
(UART,
IrDA,SPI)
DMA
3 Channel
(SPI, I2C)
COMP_B
(External
Voltage
Monitoring)
Functional Block Diagram – MSP430F677xIPZ, MSP430F676xIPZ, and MSP430F674xIPZ
XIN
XOUT
DVCC DVSS
AVCC AVSS
AUX1 AUX2 AUX3
PA
P1.x P2.x
RST/NMI
PB
P3.x P4.x
PC
P5.x P6.x
P7.x
PD
P8.x
(32kHz)
ACLK
Unified
Clock
System
512kB
256kB
128kB
32kB
16kB
Flash
RAM
SMCLK
MCLK
SYS
Watchdog
Port
Mapping
Controller
CRC16
MPY32
AES128
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
1×8 I/Os
1×2 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×10 I/Os
Ta0
TA1
TA2
TA3
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
eUSCI_B0
eUSCI_B1
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 8+2)
JTAG/
SBW
Interface/
Port PJ
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
SD24_B
7 Channel
6 Channel
4 Channel
PJ.x
6
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ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
RTC_CE
Timer_A
3 CC
Registers
Timer_A
2 CC
Registers
(UART,
IrDA,SPI)
DMA
3 Channel
(SPI, I2C)
COMP_B
(External
Voltage
Monitoring)
Copyright © 2012–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA - Technology / Software Publicly Available
www.ti.com
MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
SD0N0
SD0P0
SD1P0
SD1N0
SD2N0
SD2P0
SD3P0
SD3N0
VASYS2
AVSS2
VREF
SD4P0
SD4N0
SD5P0
SD5N0
SD6P0
SD6N0
AVSS1
AVCC
VASYS1
AUXVCC2
AUXVCC1
VDSYS1
DVSS1
DVCC
VCORE
Pin Designation, MSP430F677xIPEU
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
1
102
RST/NMI/SBWTDIO
XOUT
2
101
PJ.3/TCK
AUXVCC3
3
100
RTCCAP1
4
99
PJ.1/TDI/TCLK
XIN
PJ.2/TMS
RTCCAP0
5
98
PJ.0/TDO
P1.5/SMCLK/CB0/A5
6
97
TEST/SBWTCK
P1.4/MCLK/CB1/A4
7
96
P2.3/PM_TA1.0
P1.3/ADC10CLK/A3
8
95
P2.2/PM_TA0.2
P1.2/ACLK/A2
9
94
P2.1/PM_TA0.1/BSL_RX
P1.1/TA2.1/VeREF+/A1
10
93
P2.0/PM_TA0.0/BSL_TX
P1.0/TA1.1/VeREF-/A0
11
92
P11.5/TACLK/RTCCLK
P2.4/PM_TA2.0
12
91
P11.4/CBOUT
P2.5/PM_UCB0SOMI/PM_UCB0SCL
13
90
P11.3/TA2.1
P2.6/PM_UCB0SIMO/PM_UCB0SDA
14
89
P11.2/TA1.1
P2.7/PM_UCB0CLK
15
88
P11.1/TA3.1/CB3
P3.0/PM_UCA0RXD/PM_UCA0SOMI
16
87
P11.0/S0
P3.1/PM_UCA0TXD/PM_UCA0SIMO
17
86
P10.7/S1
P3.2/PM_UCA0CLK
18
85
P10.6/S2
P3.3/PM_UCA1CLK
19
84
P10.5/S3
P3.4/PM_UCA1RXD/PM_UCA1SOMI
20
83
P10.4/S4
P3.5/PM_UCA1TXD/PM_UCA1SIMO
21
82
P10.3/S5
COM0
22
81
P10.2/S6
COM1
23
80
P10.1/S7
P1.6/COM2
24
79
P10.0/S8
P1.7/COM3
25
78
P9.7/S9
P5.0/COM4
26
77
P9.6/S10
P5.1/COM5
27
76
P9.5/S11
P5.2/COM6
28
75
P9.4/S12
P5.3/COM7
29
74
P9.3/S13
LCDCAP/R33
30
73
P9.2/S14
P5.4/SDCLK/R23
31
72
P9.1/S15
P5.5/SD0DIO/LCDREF/R13
32
71
P9.0/S16
P5.6/SD1DIO/R03
33
70
DVSS2
P5.7/SD2DIO/CB2
34
69
VDSYS2
P6.0/SD3DIO
35
68
P8.7/S17
P3.6/PM_UCA2RXD/PM_UCA2SOMI
36
67
P8.6/S18
P3.7/PM_UCA2TXD/PM_UCA2SIMO
37
66
P8.5/S19
38
65
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
P8.4/S20
P8.3/S21
P8.2/S22
P8.1/S23
P8.0/S24
P7.7/S25
P7.6/S26
P7.5/S27
P7.4/S28
P7.3/S29
P7.2/S30
P7.1/S31
P7.0/S32
P6.7/S33
P6.6/S34
P6.5/S35
P6.4/S36
P6.3/SD6DIO/S37
P6.2/SD5DIOS38
P6.1/SD4DIO/S39
P4.7/PM_TA3.0
P4.6/PM_UCB1CLK
P4.4/PM_UCB1SOMI/PM_UCB1SCL
P4.5/PM_UCB1SIMO/PM_UCB1SDA
P4.3/PM_UCA3CLK
P4.1/PM_UCA3RXD/M_UCA3SOMI
P4.2/PM_UCA3TXD/PM_UCA3SIMO
P4.0/PM_UCA2CLK
PEU PACKAGE
A.
The secondary digital functions on Ports P2, P3 and P4 are fully mappable. The pin designation shows only the
default mapping. See Table 16 for details.
B.
The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
C.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
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Table 3. Pinout Differences for MSP430F677xIPEU , MSP430F676xIPEU , and MSP430F674xIPEU
8
PIN NAME
PIN
NUMBER
MSP430F677xIPEU
MSP430F676xIPEU
MSP430F674xIPEU
46
P6.1/SD4DIO/S39
P6.1/SD4DIO/S39
P6.1/S39
47
P6.2/SD5DIO/S38
P6.2/SD5DIO/S38
P6.2/S38
48
P6.3/SD6DIO/S37
P6.3/S37
P6.3/S37
113
VREF
VREF
VREF
114
SD4P0
SD4P0
NC
115
SD4N0
SD4N0
NC
116
SD5P0
SD5P0
NC
117
SD5N0
SD5NO
NC
118
SD6P0
NC
NC
119
SD6N0
NC
NC
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
DVSS2
P6.0/S16
P6.1/S15
P6.3/S13
P6.2/S14
P6.4/S12
P6.5/S11
P6.6/S10
P6.7/S9
P7.0/S8
P7.1/S7
P7.2/S6
P7.3/S5
P7.4/S4
P7.5/S3
P7.6/S2
P7.7/S1
P8.0/S0
P8.1/TACLK/RTCCLKCB3
TEST/SBWTCK
PJ.0/TDO
PJ.1TDI/TCLK
PJ.3/TCK
PJ.2/TMS
RST/NMI/SBWTDIO
Pin Designation, MSP430F677xIPZ
SD0P0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
VDSYS2
SD0N0
2
74
P5.7/SD6DIO/S17
SD1P0
3
73
P5.6/SD5DIO/S18
SD1N0
4
72
P5.5/SD4DIO/S19
SD2P0
5
71
P5.4/SD3DIO/S20
SD2N0
6
70
P5.3/SD2DIO/S21
SD3P0
7
69
P5.2/SD1DIO/S22
SD3N0
8
68
P5.1/SD0DIO/S23
VASYS2
9
67
P5.0/SDCLK/S24
AVSS2
10
66
P4.7/PM_TA3.0/S25
VREF
11
65
P4.6/PM_UCB1CLK/S26
SD4P0
12
64
P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27
SD4N0
13
63
P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28
SD5P0
14
62
P4.3/PM_UCA3CLK/S29
SD5N0
15
61
P4.4/PM_UCA3TXD/PM_UCA3SIMO/S30
SD6P0
16
60
P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31
SD6N0
17
59
P4.0/PM_UCA2CLK/S32
AVSS1
18
58
P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33
AVCC
19
57
P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34
VASYS1
20
56
P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35
AUXVCC2
21
55
P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36
AUXVCC1
22
54
P3.3/PM_UCA1CLK/S37
VDSYS1
23
53
P3.2/PM_UCA0CLK/S38
DVCC
24
52
P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39
P3.0/PM_UCA0RXD/PM_UCA0SOMI
P2.7/PM_UCB0CLK/CB2
P2.6/PM_UCB0SIMO/PM_UCB0SDA/R03
P2.5/PM_UCB0SOMI/PM_UCB0SCL/LCDREF/R13
P2.4/PM_TA2.0/R23
LCDCAP/R33
P2.3/PM_TA1.0/COM7
P2.2/PM_TA0.2/COM6
P2.1/PM_TA0.1/BSL_RX/COM5
P2.0/PM_TA0.0/BSL_TX/COM4
P1.7/COM3
P1.6/COM2
COM1
COM0
P1.0/TA1.1/VeREF-/A0
P1.1/TA2.1/CBOUT/VeREF+/A1
P1.2/ACLK/A2
P1.3/ADC10CLK/A3
P1.4/MCLK/CB1/A4
P1.5/SMCLK/CB0/A5
RTCCAP0
RTCCAP1
AUXVCC3
XOUT
XIN
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VCORE
DVSS1
PZ PACKAGE
D.
The secondary digital functions on Ports P2, P3 and P4 are fully mappable. The pin designation shows only the
default mapping. See Table 16 for details.
E.
The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
F.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
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Table 4. Pinout Differences for MSP430F677xIPZ , MSP430F676xIPZ , and MSP430F674xIPZ
PIN
NUMBER
10
PIN NAME
MSP430F677xIPZ
MSP430F676xIPZ
MSP430F674xIPZ
11
VREF
VREF
VREF
12
SD4P0
SD4P0
NC
13
SD4N0
SD4N0
NC
14
SD5P0
SD5P0
NC
15
SD5N0
SD5NO
NC
16
SD6P0
NC
NC
17
SD6N0
NC
NC
72
P5.5/SD4DIO/S19
P5.5/SD4DIO/S19
P5.5/S19
73
P5.6/SD5DIO/S18
P5.6/SD5DIO/S18
P5.6/S18
74
P5.7/SD6DIO/S17
P5.7/S17
P5.7/S17
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MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 5. Terminal Functions – PEU Package
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PEU
XIN
1
I/O
Input terminal for crystal oscillator
XOUT
2
I/O
Output terminal for crystal oscillator
AUXVCC3
3
RTCCAP1
4
I
External time capture pin 1 for RTC_C
RTCCAP0
5
I
External time capture pin 0 for RTC_C
P1.5/SMCLK/CB0/A5
6
Auxiliary power supply AUXVCC3 for back up subsystem
I/O
General-purpose digital I/O with port interrupt
SMCLK clock output
Comparator_B input CB0
Analog input A5 - 10-bit ADC
P1.4/MCLK/CB1/A4
7
I/O
General-purpose digital I/O with port interrupt
MCLK clock output
Comparator_B input CB1
Analog input A4 - 10-bit ADC
P1.3/ADC10CLK/A3
8
I/O
General-purpose digital I/O with port interrupt
ADC10_A clock output
Analog input A3 - 10-bit ADC
P1.2/ACLK/A2
9
I/O
General-purpose digital I/O with port interrupt
ACLK clock output
Analog input A2 - 10-bit ADC
I/O
General-purpose digital I/O with port interrupt
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC's reference voltage for an external applied reference voltage
Analog input A1 - 10-bit ADC
P1.1/TA2.1/VeREF+/A1
10
P1.0/TA1.1/VeREF-/A0
11
I/O
General-purpose digital I/O with port interrupt
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
Negative terminal for the ADC's reference voltage for an external applied reference voltage
Analog input A0 - 10-bit ADC
P2.4/PM_TA2.0
12
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
P2.5/PM_UCB0SOMI/
PM_UCB0SCL
13
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave out master in
Default mapping: eUSCI_B0 I2C clock
P2.6/PM_UCB0SIMO/
PM_UCB0SDA
14
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave in master out
Default mapping: eUSCI_B0 I2C data
P2.7/PM_UCB0CLK
15
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 clock input/output
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
16
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A0 UART receive data
Default mapping: eUSCI_A0 SPI slave out master in
P3.1/PM_UCA0TXD/
PM_UCA0SIMO
17
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A0 UART transmit data
Default mapping: eUSCI_A0 SPI slave in master out
(1)
I = input, O = output
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Table 5. Terminal Functions – PEU Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PEU
P3.2/PM_UCA0CLK
18
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A0 clock input/output
P3.3/PM_UCA1CLK
19
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 clock input/output
P3.4/PM_UCA1RXD/
PM_UCA1SOMI
20
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 UART receive data
Default mapping: eUSCI_A1 SPI slave out master in
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
21
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 UART transmit data
Default mapping: eUSCI_A1 SPI slave in master out
COM0
22
O
LCD common output COM0 for LCD backplane
COM1
23
O
LCD common output COM1 for LCD backplane
P1.6/COM2
24
I/O
General-purpose digital I/O with port interrupt
LCD common output COM2 for LCD backplane
P1.7/COM3
25
I/O
General-purpose digital I/O with port interrupt
LCD common output COM3 for LCD backplane
P5.0/COM4
26
I/O
General-purpose digital I/O
LCD common output COM4 for LCD backplane
P5.1/COM5
27
I/O
General-purpose digital I/O
LCD common output COM5 for LCD backplane
P5.2/COM6
28
I/O
General-purpose digital I/O
LCD common output COM6 for LCD backplane
P5.3/COM7
29
I/O
General-purpose digital I/O
LCD common output COM7 for LCD backplane
LCDCAP/R33
30
I/O
LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
P5.4/SDCLK/R23
31
I/O
General-purpose digital I/O
SD24_B bit stream clock input/output
Input/Output port of second most positive analog LCD voltage (V2)
P5.5/SD0DIO/
LCDREF/R13
32
I/O
General-purpose digital I/O
SD24_B converter 0 bit stream data input/output
External reference voltage input for regulated LCD voltage
Input/Output port of third most positive analog LCD voltage (V3 or V4)
P5.6/SD1DIO/R03
33
I/O
General-purpose digital I/O
SD24_B converter 1 bit stream data input/output
Input/output port of lowest analog LCD voltage (V5)
P5.7/SD2DIO/CB2
34
I/O
General-purpose digital I/O
SD24_B converter 2 bit stream data input/output
Comparator_B input CB2
P6.0/SD3DIO
35
I/O
General-purpose digital I/O
SD24_B converter 3 bit stream data input/output
12
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MSP430F677x
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MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 5. Terminal Functions – PEU Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PEU
P3.6/PM_UCA2RXD/
PM_UCA2SOMI
36
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 UART receive data
Default mapping: eUSCI_A2 SPI slave out master in
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
37
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 UART transmit data
Default mapping: eUSCI_A2 SPI slave in master out
P4.0/PM_UCA2CLK
38
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 clock input/output
P4.1/PM_UCA3RXD/
PM_UCA3SOMI
39
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 UART receive data
Default mapping: eUSCI_A3 SPI slave out master in
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
40
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 UART transmit data
Default mapping: eUSCI_A3 SPI slave in master out
P4.3/PM_UCA3CLK
41
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 clock input/output
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
42
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 SPI slave out, master in
Default mapping: eUSCI_B1 I2C clock
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
43
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 SPI slave in, master out
Default mapping: eUSCI_B1 I2C data
P4.6/PM_UCB1CLK
44
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 clock input/output
P4.7/PM_TA3.0
45
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA3 capture CCR0: CCI0A input, compare: Out0 output
P6.1/SD4DIO/S39
46
I/O
General-purpose digital I/O
SD24_B converter 4 bit stream data input/output (not available in F674x devices)
LCD segment output S39
P6.2/SD5DIO/S38
47
I/O
General-purpose digital I/O
SD24_B converter 5 bit stream data input/output (not available in F674x devices)
LCD segment output S38
P6.3/SD6DIO/S37
48
I/O
General-purpose digital I/O
SD24_B converter 6 bit stream data input/output (not available in F674x, F676x devices)
LCD segment output S37
P6.4/S36
49
I/O
General-purpose digital I/O
LCD segment output S36
P6.5/S35
50
I/O
General-purpose digital I/O
LCD segment output S35
P6.6/S34
51
I/O
General-purpose digital I/O
LCD segment output S34
P6.7/S33
52
I/O
General-purpose digital I/O
LCD segment output S33
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Table 5. Terminal Functions – PEU Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PEU
P7.0/S32
53
I/O
General-purpose digital I/O
LCD segment output S32
P7.1/S31
54
I/O
General-purpose digital I/O
LCD segment output S31
P7.2/S30
55
I/O
General-purpose digital I/O
LCD segment output S30
P7.3/S29
56
I/O
General-purpose digital I/O
LCD segment output S29
P7.4/S28
57
I/O
General-purpose digital I/O
LCD segment output S28
P7.5/S27
58
I/O
General-purpose digital I/O
LCD segment output S27
P7.6/S26
59
I/O
General-purpose digital I/O
LCD segment output S26
P7.7/S25
60
I/O
General-purpose digital I/O
LCD segment output S25
P8.0/S24
61
I/O
General-purpose digital I/O
LCD segment output S24
P8.1/S23
62
I/O
General-purpose digital I/O
LCD segment output S23
P8.2/S22
63
I/O
General-purpose digital I/O
LCD segment output S22
P8.3/S21
64
I/O
General-purpose digital I/O
LCD segment output S21
P8.4/S20
65
I/O
General-purpose digital I/O
LCD segment output S20
P8.5/S19
66
I/O
General-purpose digital I/O
LCD segment output S19
P8.6/S18
67
I/O
General-purpose digital I/O
LCD segment output S18
P8.7/S17
68
I/O
General-purpose digital I/O
LCD segment output S17
VDSYS2 (2)
69
Digital power supply for I/Os
DVSS2
70
Digital ground supply
P9.0/S16
71
I/O
General-purpose digital I/O
LCD segment output S16
P9.1/S15
72
I/O
General-purpose digital I/O
LCD segment output S15
P9.2/S14
73
I/O
General-purpose digital I/O
LCD segment output S14
(2)
14
The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.
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MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 5. Terminal Functions – PEU Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PEU
P9.3/S13
74
I/O
General-purpose digital I/O
LCD segment output S13
P9.4/S12
75
I/O
General-purpose digital I/O
LCD segment output S12
P9.5/S11
76
I/O
General-purpose digital I/O
LCD segment output S11
P9.6/S10
77
I/O
General-purpose digital I/O
LCD segment output S10
P9.7/S9
78
I/O
General-purpose digital I/O
LCD segment output S9
P10.0/S8
79
I/O
General-purpose digital I/O
LCD segment output S8
P10.1/S7
80
I/O
General-purpose digital I/O
LCD segment output S7
P10.2/S6
81
I/O
General-purpose digital I/O
LCD segment output S6
P10.3/S5
82
I/O
General-purpose digital I/O
LCD segment output S5
P10.4/S4
83
I/O
General-purpose digital I/O
LCD segment output S4
P10.5/S3
84
I/O
General-purpose digital I/O
LCD segment output S3
P10.6/S2
85
I/O
General-purpose digital I/O
LCD segment output S2
P10.7/S1
86
I/O
General-purpose digital I/O
LCD segment output S1
P11.0/S0
87
I/O
General-purpose digital I/O
LCD segment output S0
P11.1/TA3.1/CB3
88
I/O
General-purpose digital I/O
Timer TA3 capture CCR1: CCI1A input, compare: Out1 output
Comparator_B input CB3
P11.2/TA1.1
89
I/O
General-purpose digital I/O
Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
P11.3/TA2.1
90
I/O
General-purpose digital I/O
Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
P11.4/CBOUT
91
I/O
General-purpose digital I/O
Comparator_B Output
P11.5/TACLK/RTCCLK
92
I/O
General-purpose digital I/O
Timer clock input TACLK for TA0, TA1, TA2, TA3
RTCCLK clock output
P2.0/PM_TA0.0/BSL_TX
93
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output
Bootstrap loader: Data transmit
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Table 5. Terminal Functions – PEU Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PEU
P2.1/PM_TA0.1/BSL_RX
94
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output
Bootstrap loader: Data receive
P2.2/PM_TA0.2
95
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
P2.3/PM_TA1.0
96
I/O
General-purpose digital I/O port interrupt and with mappable secondary function
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
TEST/SBWTCK
97
I
PJ.0/TDO
98
I/O
General-purpose digital I/O
Test data output
PJ.1/TDI/TCLK
99
I/O
General-purpose digital I/O
Test data input or Test clock input
PJ.2/TMS
100
I/O
General-purpose digital I/O
Test mode select
PJ.3/TCK
101
I/O
General-purpose digital I/O
Test clock
RST/NMI/SBWTDIO
102
I/O
Reset input active low
Non-maskable interrupt input
Spy-By-Wire data input/output
SD0P0
103
I
SD24_B positive analog input for converter 0 (3)
SD0N0
104
I
SD24_B negative analog input for converter 0 (3)
SD1P0
105
I
SD24_B positive analog input for converter 1 (3)
SD1N0
106
I
SD24_B negative analog input for converter 1 (3)
SD2P0
107
I
SD24_B positive analog input for converter 2 (3)
SD2N0
108
I
SD24_B negative analog input for converter 2 (3)
SD3P0
109
I
SD24_B positive analog input for converter 3 (3)
SD3N0
110
I
SD24_B negative analog input for converter 3 (3)
VASYS2
111
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of CVSYS
AVSS2
112
Analog ground supply
VREF
113
I
SD24_B external reference voltage
SD4P0
114
I
SD24_B positive analog input for converter 4 (3) (not available on F674x devices)
SD4N0
115
I
SD24_B negative analog input for converter 4 (3) (not available on F674x devices)
SD5P0
116
I
SD24_B positive analog input for converter 5 (3) (not available on F674x devices)
SD5N0
117
I
SD24_B negative analog input for converter 5 (3) (not available on F674x devices)
SD6P0
118
I
SD24_B positive analog input for converter 6 (3) (not available on F676x, F674x devices)
SD6N0
119
I
SD24_B negative analog input for converter 6 (3) (not available on F676x, F674x devices)
AVSS1
120
(3)
16
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Analog ground supply
It is recommended to short unused analog input pairs and connect them to analog ground.
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MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 5. Terminal Functions – PEU Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PEU
AVCC
121
Analog power supply
VASYS1
122
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of CVSYS
AUXVCC2
123
Auxiliary power supply AUXVCC2
AUXVCC1
124
Auxiliary power supply AUXVCC1
VDSYS1 (4)
125
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of CVSYS.
DVCC
126
Digital power supply
DVSS1
127
Digital ground supply
VCORE (5)
128
Regulated core power supply (internal use only, no external current loading)
(4)
(5)
The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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MSP430F674x
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Table 6. Terminal Functions – PZ Package
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
SD0P0
1
I
SD24_B positive analog input for converter 0 (2)
SD0N0
2
I
SD24_B negative analog input for converter 0 (2)
SD1P0
3
I
SD24_B positive analog input for converter 1 (2)
SD1N0
4
I
SD24_B negative analog input for converter 1 (2)
SD2P0
5
I
SD24_B positive analog input for converter 2 (2)
SD2N0
6
I
SD24_B negative analog input for converter 2 (2)
SD3P0
7
I
SD24_B positive analog input for converter 3 (2)
SD3N0
8
I
SD24_B negative analog input for converter 3 (2)
VASYS2
9
AVSS2
10
VREF
11
I
SD24_B external reference voltage
SD4P0
12
I
SD24_B positive analog input for converter 4 (2) (not available on F674x devices)
SD4N0
13
I
SD24_B negative analog input for converter 4 (2) (not available on F674x devices)
SD5P0
14
I
SD24_B positive analog input for converter 5 (2) (not available on F674x devices)
SD5N0
15
I
SD24_B negative analog input for converter 5 (2) (not available on F674x devices)
SD6P0
16
I
SD24_B positive analog input for converter 6 (2) (not available on F676x, F674x devices)
SD6N0
17
I
SD24_B negative analog input for converter 6 (2) (not available on F676x, F674x devices)
AVSS1
18
Analog ground supply
AVCC
19
Analog power supply
VASYS1
20
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of CVSYS
AUXVCC2
21
Auxiliary power supply AUXVCC2
AUXVCC1
22
Auxiliary power supply AUXVCC1
23
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of CVSYS.
24
Digital power supply
25
Digital ground supply
VDSYS1
(3)
DVCC
DVSS1
VCORE
(4)
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended
capacitor value of CVSYS.
Analog ground supply
26
Regulated core power supply (internal use only, no external current loading)
XIN
27
I/O
Input terminal for crystal oscillator
XOUT
28
I/O
Output terminal for crystal oscillator
AUXVCC3
29
RTCCAP1
30
I
External time capture pin 1 for RTC_C
RTCCAP0
31
I
External time capture pin 0 for RTC_C
P1.5/SMCLK/CB0/A5
P1.4/MCLK/CB1/A4
(1)
(2)
(3)
(4)
18
32
33
Auxiliary power supply AUXVCC3 for back up subsystem
I/O
General-purpose digital I/O with port interrupt
SMCLK clock output
Comparator_B input CB0
Analog input A5 - 10-bit ADC
I/O
General-purpose digital I/O with port interrupt
MCLK clock output
Comparator_B input CB1
Analog input A4 - 10-bit ADC
I = input, O = output
It is recommended to short unused analog input pairs and connect them to analog ground.
The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 6. Terminal Functions – PZ Package (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
P1.3/ADC10CLK/A3
34
I/O
General-purpose digital I/O with port interrupt
ADC10_A clock output
Analog input A3 - 10-bit ADC
P1.2/ACLK/A2
35
I/O
General-purpose digital I/O with port interrupt
ACLK clock output
Analog input A2 - 10-bit ADC
I/O
General-purpose digital I/O with port interrupt
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
Comparator_B Output
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 - 10-bit ADC
P1.1/TA2.1/CBOUT/
VeREF+/A1
36
P1.0/TA1.1/VeREF-/A0
37
I/O
General-purpose digital I/O with port interrupt
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
Negative terminal for the ADC's reference voltage for an external applied reference voltage
Analog input A0 - 10-bit ADC
COM0
38
I/O
LCD common output COM0 for LCD backplane
COM1
39
I/O
LCD common output COM1 for LCD backplane
P1.6/COM2
40
I/O
General-purpose digital I/O with port interrupt
LCD common output COM2 for LCD backplane
P1.7/COM3
41
I/O
General-purpose digital I/O with port interrupt
LCD common output COM3 for LCD backplane
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default Mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
Bootstrap loader: Data transmit
LCD common output COM4 for LCD backplane
P2.0/PM_TA0.0/
BSL_TX/COM4
42
P2.1/PM_TA0.1/
BSL_RX/COM5
43
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default Mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Bootstrap loader: Data receive
LCD common output COM5 for LCD backplane
P2.2/PM_TA0.2/COM6
44
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default Mapping: Timer TA0 CCR0 capture: CCI2A input, compare: Out2 output
LCD common output COM6 for LCD backplane
P2.3/PM_TA1.0/COM7
45
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
LCD common output COM7 for LCD backplane
LCDCAP/R33
46
I/O
LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
P2.4/PM_TA2.0/R23
47
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
Input/Output port of second most positive analog LCD voltage (V2)
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Table 6. Terminal Functions – PZ Package (continued)
TERMINAL
NAME
P2.5/PM_UCB0SOMI/
PM_UCB0SCL/LCDREF/
R13
NO.
I/O (1)
DESCRIPTION
PZ
48
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave out, master in
Default mapping: eUSCI_B0 I2C clock
External reference voltage input for regulated LCD voltage
Input/Output port of third most positive analog LCD voltage (V3 or V4)
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
49
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave in, master out
Default mapping: eUSCI_B0 I2C data
Input/output port of lowest analog LCD voltage (V5)
P2.7/PM_UCB0CLK/CB2
50
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 clock input/output
Comparator_B input CB2
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
51
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A0 UART receive data
Default mapping: eUSCI_A0 SPI slave out, master in
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
52
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A0 UART transmit data
Default mapping: eUSCI_A0 SPI slave in, master out
LCD segment output S39
P3.2/PM_UCA0CLK/S38
53
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A0 clock input/output
LCD segment output S38
P3.3/PM_UCA1CLK/S37
54
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 clock input/output
LCD segment output S37
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 UART receive data
Default mapping: eUSCI_A1 SPI slave out, master in
LCD segment output S36
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A1 UART transmit data
Default mapping: eUSCI_A1 SPI slave in, master out
LCD segment output S35
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 UART receive data
Default mapping: eUSCI_A2 SPI slave out, master in
LCD segment output S34
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/S36
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
55
56
57
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
58
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 UART transmit data
Default mapping: eUSCI_A2 SPI slave in, master out
LCD segment output S33
P4.0/PM_UCA2CLK/S32
59
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A2 clock input/output
LCD segment output S32
20
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MSP430F677x
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SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 6. Terminal Functions – PZ Package (continued)
TERMINAL
NAME
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/S31
NO.
I/O (1)
DESCRIPTION
PZ
60
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 UART receive data
Default mapping: eUSCI_A3 SPI slave out, master in
LCD segment output S31
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
61
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 UART transmit data
Default mapping: eUSCI_A3 SPI slave in, master out
LCD segment output S30
P4.3/PM_UCA3CLK/S29
62
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_A3 clock input/output
LCD segment output S29
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 SPI slave out, master in
Default mapping: eUSCI_B1 I2C clock
LCD segment output S28
P4.4/PM_UCB1SOMI/
PM_UCB1SCL/S28
63
P4.5/PM_UCB1SIMO/
PM_UCB1SDA/S27
64
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 SPI slave in, master out
Default mapping: eUSCI_B1 I2C data
LCD segment output S27
P4.6/PM_UCB1CLK/S26
65
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: eUSCI_B1 clock input/output
LCD segment output S26
P4.7/PM_TA3.0/S25
66
I/O
General-purpose digital I/O with mappable secondary function
Default Mapping: Timer TA3 CCR0 capture: CCI0A input, compare: Out0 output
LCD segment output S25
P5.0/SDCLK/S24
67
I/O
General-purpose digital I/O
SD24_B bit stream clock input/output
LCD segment output S24
P5.1/PM_SD0DIO/S23
68
I/O
General-purpose digital I/O
Default mapping: SD24_B converter 0 bit stream data input/output
LCD segment output S23
P5.2/PM_SD1DIO/S22
69
I/O
General-purpose digital I/O
Default mapping: SD24_B converter 1 bit stream data input/output
LCD segment output S22
P5.3/PM_SD2DIO/S21
70
I/O
General-purpose digital I/O
Default mapping: SD24_B converter 2 bit stream data input/output
LCD segment output S21
P5.4/PM_SD3DIO/S20
71
I/O
General-purpose digital I/O
Default mapping: SD24_B converter 3 bit stream data input/output
LCD segment output S20
I/O
General-purpose digital I/O
Default mapping: SD24_B converter 4 bit stream data input/output (not available on F674x
devices)
LCD segment output S19
P5.5/PM_SD4DIO/S19
72
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Table 6. Terminal Functions – PZ Package (continued)
TERMINAL
NAME
P5.6/PM_SD5DIO/S18
NO.
I/O (1)
DESCRIPTION
I/O
General-purpose digital I/O
Default mapping: SD24_B converter 5 bit stream data input/output (not available on F674x
devices)
LCD segment output S18
I/O
General-purpose digital I/O
Default mapping: SD24_B converter 4 bit stream data input/output (not available on F676x,
F674x devices)
LCD segment output S17
PZ
73
P5.7/PM_SD6DIO/S17
74
VDSYS2 (5)
75
Digital power supply for I/Os
DVSS2
76
Digital ground supply
P6.0/S16
77
I/O
General-purpose digital I/O
LCD segment output S16
P6.1/S15
78
I/O
General-purpose digital I/O
LCD segment output S15
P6.2/S14
79
I/O
General-purpose digital I/O
LCD segment output S14
P6.3/S13
80
I/O
General-purpose digital I/O
LCD segment output S13
P6.4/S12
81
I/O
General-purpose digital I/O
LCD segment output S12
P6.5/S11
82
I/O
General-purpose digital I/O
LCD segment output S11
P6.6/S10
83
I/O
General-purpose digital I/O
LCD segment output S10
P6.7/S9
84
I/O
General-purpose digital I/O
LCD segment output S9
P7.0/S8
85
I/O
General-purpose digital I/O
LCD segment output S8
P7.1/S7
86
I/O
General-purpose digital I/O
LCD segment output S7
P7.2/S6
87
I/O
General-purpose digital I/O
LCD segment output S6
P7.3/S5
88
I/O
General-purpose digital I/O
LCD segment output S5
P7.4/S4
89
I/O
General-purpose digital I/O
LCD segment output S4
P7.5/S3
90
I/O
General-purpose digital I/O
LCD segment output S3
P7.6/S2
91
I/O
General-purpose digital I/O
LCD segment output S2
P7.7/S1
92
I/O
General-purpose digital I/O
LCD segment output S1
(5)
22
The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 6. Terminal Functions – PZ Package (continued)
TERMINAL
NAME
P8.0/S0
NO.
I/O (1)
DESCRIPTION
PZ
93
I/O
General-purpose digital I/O
LCD segment output S0
General-purpose digital I/O
Timer clock input TACLK for TA0, TA1, TA2, TA3
RTCCLK clock output
Comparator_B input CB3
P8.1/TACLK/RTCCLK/CB3
94
I/O
TEST/SBWTCK
95
I
PJ.0/TDO
96
I/O
General-purpose digital I/O
Test data output
PJ.1/TDI/TCLK
97
I/O
General-purpose digital I/O
Test data input or Test clock input
PJ.2/TMS
98
I/O
General-purpose digital I/O
Test mode select
PJ.3/TCK
99
I/O
General-purpose digital I/O
Test clock
RST/NMI/SBWTDIO
100
I/O
Reset input active low
Non-maskable interrupt input
Spy-By-Wire data input/output
Test mode pin – select digital I/O on JTAG pins
Spy-By-Wire input clock
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SHORT-FORM DESCRIPTION
CPU (Link to User's Guide)
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
General-Purpose Register
R10
General-Purpose Register
R11
Instruction Set
General-Purpose Register
R12
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 7 shows examples of the three
types of instruction formats; Table 8 shows the
address modes.
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Table 7. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source-destination
EXAMPLE
ADD
Single operands, destination only
R4 + R5 → R5
R8
PC → (TOS), R8 → PC
CALL
Relative jump, un/conditional
OPERATION
R4,R5
JNE
Jump-on-equal bit = 0
Table 8. Address Mode Descriptions
(1)
24
ADDRESS MODE
S (1)
D (1)
Register
+
+
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
+
+
MOV EDE,TONI
Absolute
+
+
MOV & MEM, & TCDAT
Indirect
+
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
+
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
+
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
SYNTAX
EXAMPLE
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
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MSP430F677x
MSP430F676x
MSP430F674x
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Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the five low-power modes, service the request, and restore back to the lowpower mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– I/O pad state retention
– RTC clocked by low-frequency oscillator
– Wakeup from RST/NMI, RTC_C events, Ports P1 and P2
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– RTC is disabled
– I/O pad state retention
– Wakeup from RST/NMI, Ports P1 and P2
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-Up
External Reset
Watchdog Timeout, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV) (1)
(2)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
Supply Switched
NMIIFG, OFIFG, ACCVIFG, AUXSWGIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
61
Watchdog Timer_A Interval Timer
Mode
WDTIFG
Maskable
0FFF8h
60
(4)
Maskable
0FFF6h
59
(1) (4)
Maskable
0FFF4h
58
Maskable
0FFF2h
57
Maskable
0FFF0h
56
Maskable
0FFEEh
55
Maskable
0FFECh
54
Maskable
0FFEAh
53
Maskable
0FFE8h
52
AUXSWGIFG, AUXIFG0, AUXIFG1, AUXIFG2
(AUXIV) (1) (4)
Maskable
0FFE6h
51
(1) (4)
Maskable
0FFE4h
50
Maskable
0FFE2h
49
eUSCI_A0 Receive or Transmit
eUSCI_B0 Receive or Transmit
ADC10_A
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1)
UCB0RXIFG, UCB0TXIFG (UCB0IV)
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV) (1) (4)
SD24_B Interrupt Flags (SD24IV) (1)
SD24_B
Timer TA0
TA0CCR0 CCIFG0
(4)
(4)
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV) (1) (4)
Timer TA0
(1) (4)
eUSCI_A1 Receive or Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV)
eUSCI_A2 Receive or Transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV) (1)
Auxiliary Supplies
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)
Timer TA1
TA1CCR0 CCIFG0 (4)
Timer TA1
TA1CCR1 CCIFG1,
TA1IFG (TA1IV) (1) (4)
eUSCI_A3 Receive or Transmit
eUSCI_B1 Receive or Transmit
Maskable
0FFE0h
48
UCA3RXIFG, UCA3TXIFG (UCA3IV)
(1) (4)
Maskable
0FFDEh
47
UCB1RXIFG, UCB1TXIFG (UCB1IV)
(1) (4)
Maskable
0FFDCh
46
Maskable
0FFDAh
45
Maskable
0FFD8h
44
Maskable
0FFD6h
43
Maskable
0FFD4h
42
Maskable
0FFD2h
41
Maskable
0FFD0h
40
Maskable
0FFCEh
39
Maskable
0FFCCh
38
P1IFG.0 to P1IFG.7 (P1IV) (1)
I/O Port P1
Timer TA2
TA2CCR0 CCIFG0 (4)
Timer TA2
TA2CCR1 CCIFG1,
TA2IFG (TA2IV) (1) (4)
I/O Port P2
P2IFG.0 to P2IFG.7 (P2IV)
Timer TA3
TA3CCR0 CCIFG0 (4)
Timer TA3
TA3CCR1 CCIFG1,
TA3IFG (TA3IV) (1) (4)
LCD_C
RTC_C
(1)
(2)
(3)
(4)
26
(4)
(4)
(1) (4)
LCD_C Interrupt Flags (LCDCIV)
(1) (4)
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1)
(4)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
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Table 9. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
Comparator_B
INTERRUPT FLAG
Comparator_B Interrupt Flags (CBIV)
AES
AESRDYIFG
Reserved
(5)
(1)
Reserved
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Maskable
0FFCAh
37
Maskable
0FFC8h
36
0FFC6h
35
(5)
⋮
⋮
0FF80h
0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and can be accessed via word or byte formats.
Legend
rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
rw-(0,1):
rw-[0,1]:
–
Bit can be read and written. It is reset or set by POR.
Bit can be read and written. It is reset or set by BOR.
SFR bit is not present in device.
Table 10. Interrupt Enable 1
15
14
13
12
11
10
9
8
–
–
–
–
–
–
AUXSWNMIE
–
rw-0
7
6
5
4
3
2
1
0
JMBOUTIE
JMBINIE
ACCVIE
NMIIE
VMAIE
–
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
WDTIE
OFIE
VMAIE
NMIIE
ACCVIE
JMBINIE
JMBOUTIE
AUXSWNMIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a
general-purpose timer.
Oscillator fault interrupt enable
Vacant memory access interrupt enable
Nonmaskable interrupt enable
Flash access violation interrupt enable
JTAG mailbox input interrupt enable
JTAG mailbox output interrupt enable
Supply switched non-maskable interrupt enable
Table 11. Interrupt Flag 1
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
JMBOUTIFG
JMBINIFG
–
NMIIFG
VMAIFG
–
OFIFG
WDTIFG
rw-[0]
rw-[0]
rw-0
rw-0
rw-0
rw-0
WDTIFG
OFIFG
VMAIFG
NMIIFG
JMBINIFG
JMBOUTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
Flag set on oscillator fault
Set on vacant memory access
Set via RST/NMI pin
Set on JTAG mailbox input message
Set on JTAG mailbox output register ready for next message
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Memory Organization
Table 12. Memory Organization
Main Memory
(flash)
MSP430F6779
MSP430F6769
MSP430F6749
MSP430F6778
MSP430F6768
MSP430F6748
MSP430F6777
MSP430F6767
MSP430F6747
512kB
512kB
256kB
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
Bank 3
128kB
08BFFFh to 06C000h
128kB
08BFFFh to 06C000h
not available
Bank 2
128kB
06BFFFh to 04C000h
128kB
06BFFFh to 04C000h
not available
Bank 1
128kB
04BFFFh to 02C000h
128kB
04BFFFh to 02C000h
128kB
04BFFFh to 02C000h
Bank 0
128kB
02BFFFh to 00C000h
128kB
02BFFFh to 00C000h
128kB
02BFFFh to 00C000h
Total Size
Main: Interrupt
vector
Main: code
memory
RAM
Total Size
32kB
16kB
32kB
Sector 7
4kB
009BFFh to 008C00h
not available
4kB
009BFFh to 008C00h
Sector 6
4kB
008BFFh to 007C00h
not available
4kB
008BFFh to 007C00h
Sector 5
4kB
007BFFh to 006C00h
not available
4kB
007BFFh to 006C00h
Sector 4
4kB
006BFFh to 005C00h
not available
4kB
006BFFh to 005C00h
Sector 3
4kB
005BFFh to 004C00h
4kB
005BFFh to 004C00h
4kB
005BFFh to 004C00h
Sector 2
4kB
004BFFh to 003C00h
4kB
004BFFh to 003C00h
4kB
004BFFh to 003C00h
Sector 1
4kB
003BFFh to 002C00h
4kB
003BFFh to 002C00h
4kB
003BFFh to 002C00h
Sector 0
4kB
002BFFh to 001C00h
4kB
002BFFh to 001C00h
4kB
002BFFh to 001C00h
128 B
001AFFh to 001A80h
128 B
001AFFh to 001A80h
128 B
001AFFh to 001A80h
128 B
001A7Fh to 001A00h
128 B
001A7Fh to 001A00h
128 B
001A7Fh to 001A00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
Device Descriptor
Information
memory (flash)
Bootstrap loader
(BSL) memory
(flash)
Peripherals
28
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MSP430F6776
MSP430F6766
MSP430F6746
Main Memory (flash)
Main: code memory
Main: Interrupt vector
Total Size
256kB
128kB
00FFFFh to 00FF80h
Bank 3
not available
not available
Bank 2
not available
not available
Bank 1
128kB
04BFFFh to 02C000h
not available
Bank 0
128kB
02BFFFh to 00C000h
128kB
02BFFFh to 00C000h
16kB
16kB
Sector 7
not available
not available
Sector 6
not available
not available
Sector 5
not available
not available
Sector 4
not available
not available
Sector 3
4kB
005BFFh to 004C00h
4kB
005BFFh to 004C00h
Sector 2
4kB
004BFFh to 003C00h
4kB
004BFFh to 003C00h
Sector 1
4kB
003BFFh to 002C00h
4kB
003BFFh to 002C00h
Sector 0
4kB
002BFFh to 001C00h
4kB
002BFFh to 001C00h
128 B
001AFFh to 001A80h
128 B
001AFFh to 001A80h
128 B
001A7Fh to 001A00h
128 B
001A7Fh to 001A00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
Device Descriptor
Information memory (flash)
Bootstrap loader (BSL)
memory (flash)
MSP430F6775
MSP430F6765
MSP430F6745
00FFFFh to 00FF80h
Total Size
RAM
MSP430F677x
MSP430F676x
MSP430F674x
Peripherals
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Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the
BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).
Table 13. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Data transmit
P2.1
Data receive
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 14. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 14. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 15. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 15. Spy-Bi-Wire Pin Requirements and Functions
30
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
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Flash Memory (Link to User's Guide)
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A can be locked separately.
RAM Memory (Link to User's Guide)
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data is lost. Features of the RAM memory include:
• RAM memory has n sectors of 4K bytes each.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
Backup RAM Memory (Link to User's Guide)
The Backup RAM provides a limited number of bytes of RAM that are retained during LPM3.5. This Backup RAM
is part of the Backup subsystem that operates on dedicated power supply AUXVCC3.There are 8 bytes of
Backup RAM available in this device. It can be wordwise accessed via the registers BAKMEM0, BAKMEM1,
BAKMEM2, and BAKMEM3. The Backup RAM registers cannot be accessed by CPU when the high-side SVS is
disabled by the user application.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Oscillator and System Clock (Link to User's Guide)
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal
very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), and an
integrated internal digitally controlled oscillator (DCO). The UCS module is designed to meet the requirements of
both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple
of the selected FLL reference frequency. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 5 µs. The UCS module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator (VLO), or
the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM) (Link to User's Guide)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
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Auxiliary Supply System (Link to User's Guide)
The auxiliary supply system provides the option to operate the device from auxiliary supplies when the primary
supply fails. There are two auxiliary supplies (AUXVCC1 and AUXVCC2) supported in MSP430F67xx. This
module supports automatic and manual switching from primary supply to auxiliary supplies while maintaining full
functionality. It allows threshold-based monitoring of primary and auxiliary supplies. The device can be started
from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system enables internal monitoring of
voltage levels on primary and auxiliary supplies using ADC10_A. This module also implements a simple charger
for backup capacitors.
Backup Subsystem (Link to User's Guide)
The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes lowfrequency oscillator, Real-Time Clock module, and Backup RAM. The functionality of Backup subsystem is
retained during LPM3.5. The Backup subsystem module registers cannot be accessed by CPU when the high
side SVS is disabled by user.
Digital I/O (Link to User's Guide)
There are up to eleven 8-bit I/O ports implemented. For 128-pin options, Ports P1 to P10 are complete, and Port
P11 is 6 bits wide. For 100-pin options, Ports P1 to P7 are complete, Port P8 is 2 bits wide, and ports P9, P10,
and P11 are completely removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are
individually programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt and LPM3.5, LPM4.5 wakeup input capability available for all bits of ports P1 and
P2.
• Read-write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 Through P11) or word-wise in pairs (PA Through PF).
Port Mapping Controller (Link to User's Guide)
The port mapping controller allows flexible and reconfigurable mapping of digital functions to Ports P2, P3, and
P4.
Table 16. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
1
2
3
4
5
6
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
PM_UCA0SOMI
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
PM_UCA0TXD
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
PM_UCA0SIMO
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
PM_UCA0STE
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA1RXD
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
PM_UCA1SOMI
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
PM_UCA1SIMO
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
7
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
8
PM_UCA1STE
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
9
10
11
32
PM_UCA0RXD
PM_UCA2RXD
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
PM_UCA2SOMI
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
PM_ UCA2SIMO
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
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Table 16. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
12
PM_UCA2STE
13
14
OUTPUT PIN FUNCTION
PM_UCA3RXD
eUSCI_A3 UART RXD (direction controlled by eUSCI – Input)
PM_UCA3SOMI
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)
PM_UCA3TXD
eUSCI_A3 UART TXD (direction controlled by eUSCI – Output)
PM_ UCA3SIMO
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)
15
PM_UCA3CLK
eUSCI_A3 clock input/output (direction controlled by eUSCI)
16
PM_UCA3STE
eUSCI_A3 SPI slave transmit enable (direction controlled by eUSCI)
17
18
PM_UCB0SIMO
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0SDA
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SOMI
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
PM_UCB0SCL
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
19
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
20
PM_UCB0STE
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCB1SIMO
eUSCI_B1 SPI slave in master out (direction controlled by eUSCI)
PM_UCB1SDA
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)
21
22
PM_UCB1SOMI
eUSCI_B1 SPI slave out master in (direction controlled by eUSCI)
PM_UCB1SCL
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)
23
PM_UCB1CLK
eUSCI_B1 clock input/output (direction controlled by eUSCI)
24
PM_UCB1STE
eUSCI_B1 SPI slave transmit enable (direction controlled by eUSCI)
25
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
26
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
27
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
28
PM_TA1.0
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
29
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
30
PM_TA3.0
31(0FFh)
(1)
INPUT PIN FUNCTION
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
(1)
PM_ANALOG
Disables the output driver and the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
which results in a read value of 31.
Table 17. Default Port Mapping
PIN NAME
PEU
PZ
PxMAPy
MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P2.0/PM_TA0.0
P2.0/PM_TA0.0/COM4
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
P2.1/PM_TA0.1
P2.1/PM_TA0.1/COM5
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
P2.2/PM_TA0.2
P2.2/PM_TA0.2/COM6
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
P2.3/PM_TA1.0
P2.3/PM_TA1.0/COM7
PM_TA1.0
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
P2.4/PM_TA2.0
P1.1/PM_TA2.0/R23
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
P2.5/PM_UCB0SOMI/
PM_UCB0SCL
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/R13
PM_UCB0SOMI/
PM_UCB0SCL
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
P2.6/PM_UCB0SIMO/
PM_UCB0SDA
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
PM_UCB0SIMO/
PM_UCB0SDA
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
P2.7/PM_UCB0CLK
P2.7/PM_UCB0CLK/CB2
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
PM_UCA0RXD/
PM_UCA0SOMI
eUSCI_A0 UART RXD (direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
P3.1/PM_UCA0TXD/
PM_UCA0SIMO
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
PM_UCA0TXD/
PM_UCA0SIMO
eUSCI_A0 UART TXD (direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
P3.2/PM_UCA0CLK
P3.2/PM_UCA0CLK/S38
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
P3.3/PM_UCA1CLK
P3.3/PM_UCA1CLK/S37
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/
P3.4/PM_UCA1RXD/
PM_UCA1SOMI/S36
PM_UCA1RXD/
PM_UCA1SOMI
eUSCI_A1 UART RXD (direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
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Table 17. Default Port Mapping (continued)
PIN NAME
PEU
PxMAPy
MNEMONIC
PZ
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
PM_UCA1TXD/
PM_UCA1SIMO
eUSCI_A1 UART TXD (direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/
P3.6/PM_UCA2RXD/
PM_UCA2SOMI/S34
PM_UCA2RXD/
PM_UCA2SOMI
eUSCI_A2 UART RXD (direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
PM_UCA2TXD/
PM_UCA2SIMO
eUSCI_A2 UART TXD (direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
P4.0/PM_UCA2CLK
P4.0/PM_UCA2CLK/S32
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/
P4.1/PM_UCA3RXD/
PM_UCA3SOMI/S31
PM_UCA3RXD/
PM_UCA3SOMI
eUSCI_A3 UART RXD (direction controlled by eUSCI – input),
eUSCI_A3 SPI slave out master in (direction controlled by eUSCI)
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
PM_UCA3TXD/
PM_UCA3SIMO
eUSCI_A3 UART TXD (direction controlled by eUSCI – output),
eUSCI_A3 SPI slave in master out (direction controlled by eUSCI)
P4.3/PM_UCA3CLK
P4.3/PM_UCA3CLK/S29
PM_UCA3CLK
eUSCI_A3 clock input/output (direction controlled by eUSCI)
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
P4.4/PM_UCB1SOMI/
PM_UCB1SCL/S28
PM_UCB1SOMI/
PM_UCB1SCL
eUSCI_B1 SPI slave out master in (direction controlled by eUSCI),
eUSCI_B1 I2C clock (open drain and direction controlled by eUSCI)
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
P4.5/PM_UCB1SIMO/
PM_UCB1SDA/S27
PM_UCB1SIMO/
PM_UCB1SDA
eUSCI_B1 SPI slave in master out (direction controlled by eUSCI),
eUSCI_B1 I2C data (open drain and direction controlled by eUSCI)
P4.6/PM_UCB1CLK
P4.6/PM_UCB1CLK/S26
PM_UCB1CLK
eUSCI_B1 clock input/output (direction controlled by eUSCI)
P4.7/PM_TA3.0
P4.7/PM_TA3.0/S25
PM_TA3.0
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
System Module (SYS) (Link to User's Guide)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 18. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
SYSRSTIV , System Reset
019Eh
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
DoBOR (BOR)
06h
Wakeup from LPMx.5
08h
SYSSNIV , System NMI
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019Ch
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
10h
SVMH_OVP (POR)
12h
DoPOR (POR)
14h
WDT timeout (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
08h
PRIORITY
Highest
Lowest
Highest
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Table 18. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTER
SYSUNIV, User NMI
ADDRESS
019Ah
INTERRUPT EVENT
VALUE
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIFG
02h
OFIFG
04h
ACCVIFG
06h
AUXSWGIFG
08h
Reserved
0Ah to 1Eh
PRIORITY
Lowest
Highest
Lowest
Watchdog Timer (WDT_A) (Link to User's Guide)
The primary function of the watchdog timer is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the timer can be configured as an interval timer and can generate interrupts at selected time
intervals.
DMA Controller (Link to User's Guide)
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
Table 19. DMA Trigger Assignments (1)
TRIGGER
(1)
CHANNEL
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
Reserved
Reserved
Reserved
5
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
6
Reserved
Reserved
Reserved
7
TA3CCR0 CCIFG
TA3CCR0 CCIFG
TA3CCR0 CCIFG
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
SD24IFG
SD24IFG
SD24IFG
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
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Table 19. DMA Trigger Assignments(1) (continued)
CHANNEL
TRIGGER
0
1
2
18
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
19
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
20
UCA2RXIFG
UCA2RXIFG
UCA2RXIFG
21
UCA2TXIFG
UCA2TXIFG
UCA2TXIFG
22
UCB0RXIFG0
UCB0RXIFG0
UCB0RXIFG0
23
UCB0TXIFG0
UCB0TXIFG0
UCB0TXIFG0
24
ADC10IFG0
ADC10IFG0
ADC10IFG0
25
UCA3RXIFG
UCA3RXIFG
UCA3RXIFG
26
UCA3TXIFG
UCA3TXIFG
UCA3TXIFG
27
UCB1RXIFG0
UCB1RXIFG0
UCB1RXIFG0
28
UCB1TXIFG0
UCB1TXIFG0
UCB1TXIFG0
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
Reserved
Reserved
Reserved
CRC16 (Link to User's Guide)
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
Hardware Multiplier (Link to User's Guide)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
AES128 Accelerator (Link to User's Guide)
The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to
the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
Enhanced Universal Serial Communication Interface (eUSCI) (Links to User's Guide: UART Mode,
SPI Mode, I2C Mode)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3 or 4 pin) and I2C.
Four eUSCI_A and two eUSCI_B module are implemented in MSP430F677x devices.
ADC10_A (Link to User's Guide)
The ADC10_A module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and a conversion results buffer. A window comparator with a
lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags.
SD24_B (Link to User's Guide)
The SD24_B module integrates up to seven independent 24-bit sigma-delta A/D converters. Each converter is
designed with a fully differential analog input pair and programmable gain amplifier input stage. Also the
converters are based on second-order over-sampling sigma-delta modulators and digital decimation filters. The
decimation filters are comb type filters with selectable oversampling ratios of up to 1024.
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TA0 (Link to User's Guide)
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 20. TA0 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA0.0
CCI0A
CBOUT (Internal)
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT SIGNAL
Timer
NA
NA
PM_TA0.0
CCR0
TA0
DVCC
VCC
PM_TA0.1
CCI1A
PM_TA0.1
ACLK (internal)
CCI1B
ADC10_A (internal)
ADC10SHSx = 001b
DVSS
GND
CCR1
DVCC
VCC
PM_TA0.2
CCI2A
DVSS
CCI2B
DVSS
GND
DVCC
VCC
TA1
SD24_B (internal)
SD24CHx.SD24SCSx = 001b
PM_TA0.2
CCR2
TA2
TA1 (Link to User's Guide)
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 21. TA1 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA1.0
CCI0A
CBOUT (Internal)
CCI0B
DVSS
GND
DVCC
VCC
PM_TA1.1
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
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MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
NA
DEVICE OUTPUT
SIGNAL
PZ
NA
PM_TA1.0
CCR0
TA0
PM_TA1.1
CCR1
TA1
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TA2 (Link to User's Guide)
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing. TA2 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 22. TA2 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA2.0
CCI0A
CBOUT (Internal)
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT SIGNAL
Timer
NA
NA
PM_TA2.0
CCR0
TA0
DVCC
VCC
PM_TA2.1
CCI1A
PM_TA2.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24CHx.SD24SCSx = 010b
DVSS
GND
DVCC
VCC
CCR1
TA1
TA3 (Link to User's Guide)
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing. TA3 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 23. TA3 Signal Connections
38
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
PM_TACLK
TACLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
DEVICE OUTPUT SIGNAL
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA3.0
CCI0A
PM_TA3.0
CBOUT (Internal)
CCI0B
TA0
ADC10_A (internal)
ADC10SHSx = 010b
DVSS
GND
TA1
CCR0
DVCC
VCC
PM_TA3.1
CCI1A
PM_TA3.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24CHx.SD24SCSx = 011b
DVSS
GND
DVCC
VCC
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SD24_B Triggers
Table 24 shows the input trigger connections to SD24_B converters from Timer_A modules and output trigger
pulse connection from SD24_B to ADC10_A.
Table 24. SD24_B Input/Output Trigger Connections
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL
TA0.1 (internal)
SD24_B
SD24CHx.SD24SCSx =
001b
TA2.1 (internal)
SD24_B
SD24CHx.SD24SCSx =
010b
TA3.1 (internal)
SD24_B
SD24CHx.SD24SCSx =
011b
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Trigger Pulse
ADC10_A (internal)
ADC10SHSx = 011b
SD24_B
ADC10_A Triggers
Table 25 shows input trigger connections to ADC10_A from Timer_A modules and SD24_B.
Table 25. ADC10_A Input Trigger Connections
DEVICE INPUT SIGNAL
MODULE INPUT SIGNAL
TA0.1 (internal)
ADC10_A
ADC10SHSx = 001b
TA3.0 (internal)
ADC10_A
ADC10SHSx = 010b
SD24_B
trigger pulse (internal)
ADC10_A
ADC10SHSx = 011b
MODULE BLOCK
ADC10_A
Real-Time Clock (RTC_C) (Link to User's Guide)
The RTC_C module can be configured for real-time clock (RTC) and calendar mode providing seconds, hours,
day of week, day of month, month, and year. The RTC_C control and configuration registers are password
protected to ensure clock integrity against run away code. Calendar mode integrates an internal calendar that
compensates for months with less than 31 days and includes leap year correction. The RTC_C also supports
flexible alarm functions, offset calibration, temperature compensation and time capture on two external events.
The RTC_C on this device operates on dedicated AUXVCC3 supply and supports operation in LPM3.5.
REF Voltage Reference (Link to User's Guide)
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules.
LCD_C (Link to User's Guide)
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display (LCD).
The LCD_C controller has dedicated data memories to hold segment drive information. Common and segment
signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux LCDs are supported.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage and thus contrast by software. The module also provides an
automatic blinking capability for individual segments in static, 2-mux, 3-mux, and 4-mux modes.
Comparator_B (Link to User's Guide)
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
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Embedded Emulation Module (EEM) (Link to User's Guide)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM
implemented on all devices has the following features:
• Eight hardware triggers or breakpoints on memory access
• Two hardware triggers or breakpoints on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers or breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
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Peripheral File Map
Table 26. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 27)
0100h
000h-01Fh
PMM (see Table 28)
0120h
000h-01Fh
Flash Control (see Table 29)
0140h
000h-00Fh
CRC16 (see Table 30)
0150h
000h-007h
RAM Control (see Table 31)
0158h
000h-001h
Watchdog (see Table 32)
015Ch
000h-001h
UCS (see Table 33)
0160h
000h-01Fh
SYS (see Table 34)
0180h
000h-01Fh
Shared Reference (see Table 35)
01B0h
000h-001h
Port Mapping Control (see Table 36)
01C0h
000h-007h
Port Mapping Port P2 (see Table 37)
01D0h
000h-007h
Port Mapping Port P3 (see Table 38)
01D8h
000h-007h
Port Mapping Port P4 (see Table 39)
01E0h
000h-007h
Port P1, P2 (see Table 40)
0200h
000h-01Fh
Port P3, P4 (see Table 41)
0220h
000h-00Bh
Port P5, P6 (see Table 42)
0240h
000h-00Bh
Port P7, P8 (see Table 43)
0260h
000h-00Bh
Port P9, P10 (see Table 44)
(Ports P9 and P10 not available in PZ package)
0280h
000h-00Bh
Port P11 (see Table 45)
(Port P11 not available in PZ package)
02A0h
000h-00Bh
Port PJ (see Table 46)
0320h
000h-01Fh
Timer TA0 (see Table 47)
0340h
000h-03Fh
Timer TA1 (see Table 48)
0380h
000h-03Fh
Timer TA2 (see Table 49)
0400h
000h-03Fh
Timer TA3 (see Table 50)
0440h
000h-03Fh
Backup Memory (see Table 51)
0480h
000h-00Fh
32-Bit Hardware Multiplier (see Table 53)
04C0h
000h-02Fh
DMA General Control (see Table 54)
0500h
000h-00Fh
DMA Channel 0 (see Table 55)
0500h
010h-01Fh
DMA Channel 1 (see Table 56)
0500h
020h-02Fh
DMA Channel 2 (see Table 57)
0500h
030h-03Fh
RTC_C (see Table 52)
0C80h
000h-03Fh
eUSCI_A0 (see Table 58)
05C0h
000h-01Fh
eUSCI_A1 (see Table 59)
05E0h
000h-01Fh
eUSCI_A2 (see Table 60)
0600h
000h-01Fh
eUSCI_A3 (see Table 61)
0620h
000h-01Fh
eUSCI_B0 (see Table 62)
0640h
000h-02Fh
eUSCI_B1 ( see Table 63 )
0680h
000h-02Fh
ADC10_A (see Table 64)
0740h
000h-01Fh
SD24_B(see Table 65)
0800h
000h-06Fh
Comparator_B (see Table 66 )
08C0h
000h-00Fh
AES Accelerator (see Table 67)
09C0h
000h-00Fh
Auxiliary Supply (see Table 68)
09E0h
000h-01Fh
LCD_C (see Table 69)
0A00h
000h-05Fh
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Table 27. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 28. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high side control
SVSMHCTL
04h
SVS low side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM Power Mode 5 control register 0
PM5CTL0
10h
Table 29. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 30. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC result
CRCINIRES
04h
Table 31. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 32. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 33. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
42
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Table 34. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootstrap loader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 35. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 36. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password register
PMAPPWD
00h
Port mapping control register
PMAPCTL
02h
Table 37. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2.0 mapping register
P2MAP0
00h
Port P2.1 mapping register
P2MAP1
01h
Port P2.2 mapping register
P2MAP2
02h
Port P2.3 mapping register
P2MAP3
03h
Port P2.4 mapping register
P2MAP4
04h
Port P2.5 mapping register
P2MAP5
05h
Port P2.6 mapping register
P2MAP6
06h
Port P2.7 mapping register
P2MAP7
07h
Table 38. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3.0 mapping register
P3MAP0
00h
Port P3.1 mapping register
P3MAP1
01h
Port P3.2 mapping register
P3MAP2
02h
Port P3.3 mapping register
P3MAP3
03h
Port P3.4 mapping register
P3MAP4
04h
Port P3.5 mapping register
P3MAP5
05h
Port P3.6 mapping register
P3MAP6
06h
Port P3.7 mapping register
P3MAP7
07h
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Table 39. Port Mapping for Port P4 (Base Address: 01E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P4.0 mapping register
P4MAP0
00h
Port P4.1 mapping register
P4MAP1
01h
Port P4.2 mapping register
P4MAP2
02h
Port P4.3 mapping register
P4MAP3
03h
Port P4.4 mapping register
P4MAP4
04h
Port P4.5 mapping register
P4MAP5
05h
Port P4.6 mapping register
P4MAP6
06h
Port P4.7 mapping register
P4MAP7
07h
Table 40. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1 (1)
P2SEL1
0Dh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
(1)
44
P2SEL1 is an empty control register to be consistent with P1SEL1 in 16-bit access.
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Table 41. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection 0
P3SEL0
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection 0
P4SEL0
0Bh
Table 42. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection 0
P5SEL0
0Ah
Port P5 selection 1
P5SEL1
0Ch
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection 0
P6SEL0
0Bh
Port P6 selection 1 (1)
P6SEL1
0Dh
(1)
P6SEL1 is an empty control register to be consistent with P5SEL1 in 16-bit access.
Table 43. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pullup/pulldown enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection 0
P7SEL0
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 pullup/pulldown enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection 0
P8SEL0
0Bh
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Table 44. Port P9, P10 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 pullup/pulldown enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection 0
P9SEL0
0Ah
Port P10 input
P10IN
01h
Port P10 output
P10OUT
03h
Port P10 direction
P10DIR
05h
Port P10 pullup/pulldown enable
P10REN
07h
Port P10 drive strength
P10DS
09h
Port P10 selection 0
P10SEL0
0Bh
Table 45. Port 11 Registers (Base Address: 02A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P11 input
P11IN
00h
Port P11 output
P11OUT
02h
Port P11 direction
P11DIR
04h
Port P11 pullup/pulldown enable
P11REN
06h
Port P11 drive strength
P11DS
08h
Port P11 selection 0
P11SEL0
0Ah
Table 46. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Port PJ selection
PJSEL
0Ah
Table 47. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
46
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Table 48. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 49. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
TA2 counter register
TA2R
10h
Capture/compare register 0
TA2CCR0
12h
Capture/compare register 1
TA2CCR1
14h
TA2 expansion register 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Table 50. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA3 control
TA3CTL
00h
Capture/compare control 0
TA3CCTL0
02h
Capture/compare control 1
TA3CCTL1
04h
TA3 counter register
TA3R
10h
Capture/compare register 0
TA3CCR0
12h
Capture/compare register 1
TA3CCR1
14h
TA3 expansion register 0
TA3EX0
20h
TA3 interrupt vector
TA3IV
2Eh
Table 51. Backup Memory Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Backup Memory 0
BAKMEM0
00h
Backup Memory 1
BAKMEM1
02h
Backup Memory 2
BAKMEM2
04h
Backup Memory 3
BAKMEM3
06h
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Table 52. RTC_C Registers (Base Address: 0C80h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC password
RTCPWD
01h
RTC control 1
RTCCTL1
02h
RTC control 3
RTCCTL3
03h
RTC offset calibration
RTCOCAL
04h
RTC temperature compensation
RTCTCMP
06h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds
RTCSEC
10h
RTC minutes
RTCMIN
11h
RTC hours
RTCHOUR
12h
RTC day of week
RTCDOW
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year
RTCYEAR
16h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion register
BIN2BCD
1Ch
BCD-to-Binary conversion register
BCD2BIN
1Eh
Real-Time Clock Time Capture Control Register
RTCTCCTL
20h
Tamper Detect Pin 0 Control Register
RTCCAP0CTL
21h
Tamper Detect Pin 1 Control Register
RTCCAP1CTL
22h
RTC seconds Backup Register 0
RTCSECBAK0
30h
RTC minutes Backup Register 0
RTCMINBAK0
31h
RTC hours Backup Register 0
RTCHOURBAK0
32h
RTC days Backup Register 0
RTCDAYBAK0
33h
RTC month Backup Register 0
RTCMONBAK0
34h
RTC year Backup Register 0
RTCYEARBAK0
36h
RTC seconds Backup Register 1
RTCSECBAK1
38h
RTC minutes Backup Register 1
RTCMINBAK1
39h
RTC hours Backup Register 1
RTCHOURBAK1
3Ah
RTC days Backup Register 1
RTCDAYBAK1
3Bh
RTC month Backup Register 1
RTCMONBAK1
3Ch
RTC year Backup Register 1
RTCYEARBAK1
3Eh
48
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Table 53. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
Table 54. DMA General Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 55. DMA Channel 0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
10h
DMA channel 0 source address low
DMA0SAL
12h
DMA channel 0 source address high
DMA0SAH
14h
DMA channel 0 destination address low
DMA0DAL
16h
DMA channel 0 destination address high
DMA0DAH
18h
DMA channel 0 transfer size
DMA0SZ
1Ah
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Table 56. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 1 control
DMA1CTL
20h
DMA channel 1 source address low
DMA1SAL
22h
DMA channel 1 source address high
DMA1SAH
24h
DMA channel 1 destination address low
DMA1DAL
26h
DMA channel 1 destination address high
DMA1DAH
28h
DMA channel 1 transfer size
DMA1SZ
2Ah
Table 57. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 2 control
DMA2CTL
30h
DMA channel 2 source address low
DMA2SAL
32h
DMA channel 2 source address high
DMA2SAH
34h
DMA channel 2 destination address low
DMA2DAL
36h
DMA channel 2 destination address high
DMA2DAH
38h
DMA channel 2 transfer size
DMA2SZ
3Ah
Table 58. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI_A control word 0
UCA0CTLW0
00h
USCI _A control word 1
UCA0CTLW1
02h
USCI_A baud rate 0
UCA0BR0
06h
USCI_A baud rate 1
UCA0BR1
07h
USCI_A modulation control
UCA0MCTLW
08h
USCI_A status
UCA0STAT
0Ah
USCI_A receive buffer
UCA0RXBUF
0Ch
USCI_A transmit buffer
UCA0TXBUF
0Eh
USCI_A LIN control
UCA0ABCTL
10h
USCI_A IrDA transmit control
UCA0IRTCTL
12h
USCI_A IrDA receive control
UCA0IRRCTL
13h
USCI_A interrupt enable
UCA0IE
1Ah
USCI_A interrupt flags
UCA0IFG
1Ch
USCI_A interrupt vector word
UCA0IV
1Eh
50
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Table 59. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI_A control word 0
UCA1CTLW0
00h
USCI _A control word 1
UCA1CTLW1
02h
USCI_A baud rate 0
UCA1BR0
06h
USCI_A baud rate 1
UCA1BR1
07h
USCI_A modulation control
UCA1MCTLW
08h
USCI_A status
UCA1STAT
0Ah
USCI_A receive buffer
UCA1RXBUF
0Ch
USCI_A transmit buffer
UCA1TXBUF
0Eh
USCI_A LIN control
UCA1ABCTL
10h
USCI_A IrDA transmit control
UCA1IRTCTL
12h
USCI_A IrDA receive control
UCA1IRRCTL
13h
USCI_A interrupt enable
UCA1IE
1Ah
USCI_A interrupt flags
UCA1IFG
1Ch
USCI_A interrupt vector word
UCA1IV
1Eh
Table 60. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI_A control word 0
UCA2CTLW0
00h
USCI _A control word 1
UCA2CTLW1
02h
USCI_A baud rate 0
UCA2BR0
06h
USCI_A baud rate 1
UCA2BR1
07h
USCI_A modulation control
UCA2MCTLW
08h
USCI_A status
UCA2STAT
0Ah
USCI_A receive buffer
UCA2RXBUF
0Ch
USCI_A transmit buffer
UCA2TXBUF
0Eh
USCI_A LIN control
UCA2ABCTL
10h
USCI_A IrDA transmit control
UCA2IRTCTL
12h
USCI_A IrDA receive control
UCA2IRRCTL
13h
USCI_A interrupt enable
UCA2IE
1Ah
USCI_A interrupt flags
UCA2IFG
1Ch
USCI_A interrupt vector word
UCA2IV
1Eh
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Table 61. eUSCI_A3 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI_A control word 0
UCA2CTLW0
00h
USCI _A control word 1
UCA2CTLW1
02h
USCI_A baud rate 0
UCA2BR0
06h
USCI_A baud rate 1
UCA2BR1
07h
USCI_A modulation control
UCA2MCTLW
08h
USCI_A status
UCA2STAT
0Ah
USCI_A receive buffer
UCA2RXBUF
0Ch
USCI_A transmit buffer
UCA2TXBUF
0Eh
USCI_A LIN control
UCA2ABCTL
10h
USCI_A IrDA transmit control
UCA2IRTCTL
12h
USCI_A IrDA receive control
UCA2IRRCTL
13h
USCI_A interrupt enable
UCA2IE
1Ah
USCI_A interrupt flags
UCA2IFG
1Ch
USCI_A interrupt vector word
UCA2IV
1Eh
Table 62. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI_B control word 0
UCB0CTLW0
00h
USCI_B control word 1
UCB0CTLW1
02h
USCI_B bit rate 0
UCB0BR0
06h
USCI_B bit rate 1
UCB0BR1
07h
USCI_B status word
UCB0STATW
08h
USCI_B byte counter threshold
UCB0TBCNT
0Ah
USCI_B receive buffer
UCB0RXBUF
0Ch
USCI_B transmit buffer
UCB0TXBUF
0Eh
USCI_B I2C own address 0
UCB0I2COA0
14h
USCI_B I2C own address 1
UCB0I2COA1
16h
USCI_B I2C own address 2
UCB0I2COA2
18h
USCI_B I2C own address 3
UCB0I2COA3
1Ah
USCI_B received address
UCB0ADDRX
1Ch
USCI_B address mask
UCB0ADDMASK
1Eh
USCI I2C slave address
UCB0I2CSA
20h
USCI interrupt enable
UCB0IE
2Ah
USCI interrupt flags
UCB0IFG
2Ch
USCI interrupt vector word
UCB0IV
2Eh
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Table 63. eUSCI_B1 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI_B control word 0
UCB0CTLW0
00h
USCI_B control word 1
UCB0CTLW1
02h
USCI_B bit rate 0
UCB0BR0
06h
USCI_B bit rate 1
UCB0BR1
07h
USCI_B status word
UCB0STATW
08h
USCI_B byte counter threshold
UCB0TBCNT
0Ah
USCI_B receive buffer
UCB0RXBUF
0Ch
USCI_B transmit buffer
UCB0TXBUF
0Eh
USCI_B I2C own address 0
UCB0I2COA0
14h
USCI_B I2C own address 1
UCB0I2COA1
16h
USCI_B I2C own address 2
UCB0I2COA2
18h
USCI_B I2C own address 3
UCB0I2COA3
1Ah
USCI_B received address
UCB0ADDRX
1Ch
USCI_B address mask
UCB0ADDMASK
1Eh
USCI I2C slave address
UCB0I2CSA
20h
USCI interrupt enable
UCB0IE
2Ah
USCI interrupt flags
UCB0IFG
2Ch
USCI interrupt vector word
UCB0IV
2Eh
Table 64. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A Control register 0
ADC10CTL0
00h
ADC10_A Control register 1
ADC10CTL1
02h
ADC10_A Control register 2
ADC10CTL2
04h
ADC10_A Window Comparator Low Threshold
ADC10LO
06h
ADC10_A Window Comparator High Threshold
ADC10HI
08h
ADC10_A Memory Control Register 0
ADC10MCTL0
0Ah
ADC10_A Conversion Memory Register
ADC10MCTL0
12h
ADC10_A Interrupt Enable
ADC10IE
1Ah
ADC10_A Interrupt Flags
ADC10IGH
1Ch
ADC10_A Interrupt Vector Word
ADC10IV
1Eh
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Table 65. SD24_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SD24_B Control 0 register
SD24BCTL0
00h
SD24_B Control 1 register
SD24BCTL1
02h
SD24_B Trigger Control register
SD24BTRGCTL
04h
SD24_B Trigger OSR Control register
SD24BTRGOSR
06h
SD24_B Trigger Preload register
SD24BTRGPRE
08h
SD24_B interrupt flag register
SD24BIFG
0Ah
SD24_B interrupt enable register
SD24BIE
0Ch
SD24_B Interrupt Vector register
SD24BIV
0Eh
SD24_B converter 0 Control register
SD24BCCTL0
10h
SD24_B converter 0 Input Control register
SD24BINCTL0
12h
SD24_B converter 0 OSR Control register
SD24BOSR0
14h
SD24_B converter 0 Preload register
SD24BPRE0
16h
SD24_B converter 1 Control register
SD24BCCTL1
18h
SD24_B Converter 1 Input Control register
SD24BINCTL1
1Ah
SD24_B Converter 1 OSR Control register
SD24BOSR1
1Ch
SD24_B Converter 1 Preload register
SD24BPRE1
1Eh
SD24_B Converter 2 Control register
SD24BCCTL2
20h
SD24_B Converter 2 Input Control register
SD24BINCTL2
22h
SD24_B Converter 2 OSR Control register
SD24BOSR2
24h
SD24_B Converter 2 Preload register
SD24BPRE2
26h
SD24_B converter 3 Control register
SD24BCCTL3
28h
SD24_B converter 3 Input Control register
SD24BINCTL3
2Ah
SD24_B converter 3 OSR Control register
SD24BOSR3
2Ch
SD24_B converter 3 Preload register
SD24BPRE3
2Eh
SD24_B converter 4 Control register
SD24BCCTL4
30h
SD24_B Converter 4 Input Control register
SD24BINCTL4
32h
SD24_B Converter 4 OSR Control register
SD24BOSR4
34h
SD24_B Converter 4 Preload register
SD24BPRE4
36h
SD24_B Converter 5 Control register
SD24BCCTL5
38h
SD24_B Converter 5 Input Control register
SD24BINCTL5
3Ah
SD24_B Converter 5 OSR Control register
SD24BOSR5
3Ch
SD24_B Converter 5 Preload register
SD24BPRE5
3Eh
SD24_B Converter 6 Control register
SD24BCCTL6
40h
SD24_B Converter 6 Input Control register
SD24BINCTL6
42h
SD24_B Converter 6 OSR Control register
SD24BOSR6
44h
SD24_B Converter 6 Preload register
SD24BPRE6
46h
SD24_B Converter 0 Conversion Memory Low Word register
SD24BMEML0
50h
SD24_B Converter 0 Conversion Memory High Word register
SD24BMEMH0
52h
SD24_B Converter 1 Conversion Memory Low Word register
SD24BMEML1
54h
SD24_B Converter 1 Conversion Memory High Word register
SD24BMEMH1
56h
SD24_B Converter 2 Conversion Memory Low Word register
SD24BMEML2
58h
SD24_B Converter 2 Conversion Memory High Word register
SD24BMEMH2
5Ah
SD24_B Converter 3 Conversion Memory Low Word register
SD24BMEML3
5Ch
SD24_B Converter 3 Conversion Memory High Word register
SD24BMEMH3
5Eh
SD24_B Converter 4 Conversion Memory Low Word register
SD24BMEML4
60h
SD24_B Converter 4 Conversion Memory High Word register
SD24BMEMH4
62h
SD24_B Converter 5 Conversion Memory Low Word register
SD24BMEML5
64h
54
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MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 65. SD24_B Registers (Base Address: 0800h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
SD24_B Converter 5 Conversion Memory High Word register
SD24BMEMH5
66h
SD24_B Converter 6 Conversion Memory Low Word register
SD24BMEML6
68h
SD24_B Converter 6 Conversion Memory High Word register
SD24BMEMH6
6Ah
Table 66. Comparator_B Register (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control register 0
CBCTL0
00h
Comp_B control register 1
CBCTL1
02h
Comp_B control register 2
CBCTL2
04h
Comp_B control register 3
CBCTL3
06h
Comp_B interrupt register
CBINT
0Ch
Comp_B interrupt vector word
CBIV
0Eh
Table 67. AES Accelerator Registers (Base Address: 09C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
AES accelerator control register 0
AESACTL0
00h
AES accelerator status register
AESASTAT
04h
AES accelerator key register
AESAKEY
06h
AES accelerator data in register
AESADIN
08h
AES accelerator data out register
AESADOUT
0Ah
Table 68. Auxiliary Supply Registers (Base Address: 09E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Auxiliary Supply Control 0 register
AUXCTL0
00h
Auxiliary Supply Control 1 register
AUXCTL1
02h
Auxiliary Supply Control 2 register
AUXCTL2
04h
AUX2 Charger Control
AUX2CHCTL
12h
AUX3 Charger Control
AUX3CHCTL
14h
AUX ADC Control
AUXADCCTL
16h
AUX Interrupt Flag
AUXIFG
1Ah
AUX Interrupt Enable
AUXIE
1Ch
AUX Interrupt Vector Word
AUXIV
1Eh
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Table 69. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C control register 0
LCDCCTL0
000h
LCD_C control register 1
LCDCCTL1
002h
LCD_C blinking control register
LCDCBLKCTL
004h
LCD_C memory control register
LCDCMEMCTL
006h
LCD_C voltage control register
LCDCVCTL
008h
LCD_C port control 0
LCDCPCTL0
00Ah
LCD_C port control 1
LCDCPCTL1
00Ch
LCD_C port control 2
LCDCPCTL2
00Eh
LCD_C charge pump control register
LCDCCPCTL
012h
LCD_C interrupt vector
LCDCIV
01Eh
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
Static and 2 to 4 mux modes
⋮
⋮
⋮
LCD_C memory 20
LCDM20
033h
LCD_C blinking memory 1
LCDBM1
040h
LCD_C blinking memory 2
LCDBM2
041h
⋮
⋮
LCD_C blinking memory 20
⋮
LCDBM20
053h
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
5 to 8 mux modes
⋮
⋮
LCD_C memory 40
56
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LCDM40
047h
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SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC to DVSS
Voltage applied to any pin (excluding VCORE)
–0.3 V to 4.1 V
(2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
±2 mA
(3)
–55°C to 105°C
Maximum junction temperature, TJ
(1)
(2)
(3)
95°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
V
PMMCOREVx = 0, 1
2.0
3.6
V
PMMCOREVx = 0, 1, 2
2.2
3.6
V
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
V
85
°C
VSS
Supply voltage VAVSS = VDVSS = VSS
TA
Operating free-air temperature
I version
–40
TJ
Operating junction temperature
I version
–40
CVCORE
Recommended capacitor at VCORE
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
ILOAD,
UNIT
3.6
Supply voltage during program execution and flash
programming. VAVCC = VDVCC = VCC (1) (2)
Processor frequency (maximum MCLK frequency) (3)
(see Figure 2)
MAX
1.8
VCC
fSYSTEM
NOM
PMMCOREVx = 0
0
V
85
470
°C
nF
10
(4)
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1,
2 V ≤ VCC ≤ 3.6 V
0
12.0
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
20.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
25.0
MHz
Maximum load current that can be drawn from DVCC
for core and IO (ILOAD = ICORE + IIO)
20
mA
Maximum load current that can be drawn from
AUXVCC1 for core and IO (ILOAD = ICORE + IIO)
20
mA
Maximum load current that can be drawn from
AUXVCC2 for core and IO (ILOAD = ICORE + IIO)
20
mA
Maximum load current that can be drawn from AVCC
for analog modules (ILOAD = IModules)
10
mA
Maximum load current that can be drawn from
AUXVCC1 for analog modules (ILOAD = IModules)
5
mA
Maximum load current that can be drawn from
AUXVCC2 for analog modules (ILOAD = IModules)
5
mA
AUX2A
PINT
Internal power dissipation
DVCCD
ILOAD,
AUX1D
ILOAD,
AUX2D
ILOAD,
AVCCA
ILOAD,
AUX1A
ILOAD,
(1)
(2)
(3)
(4)
VCC x I(DVCC)
W
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC)
can be tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
PIO
I/O power dissipation of the I/O pins powered by DVCC
(VCC - VIOH) x IIOH +
VIOL x IIOL
W
PMAX
Maximum allowed power dissipation, PMAX > PIO + PINT
(TJ - TA)/θJA
W
25
System Frequency - MHz
3
20
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 2. Maximum System Frequency
Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
PMMCOREV
x
1 MHz
TYP
IAM,
IAM,
(1)
(2)
(3)
(4)
(5)
58
Flash
RAM
(4)
(5)
Flash
RAM
3V
3V
8 MHz
MAX
0.50
TYP
2.08
MAX
12 MHz
TYP
MAX
20 MHz
TYP
0
0.32
1
0.35
2.35
3.50
2
0.39
2.68
3.99
6.61
3
0.41
2.83
4.22
6.98
0
0.19
1.04
1
0.21
1.20
1.77
2
0.23
1.38
2.04
3.35
3
0.24
1.47
2.18
3.58
25 MHz
MAX
TYP
UNIT
MAX
2.84
4.76
mA
8.3
8.67
11.75
mA
4.44
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
Active mode supply current when program executes in flash at a nominal supply voltage of 3.0V.
Active mode supply current when program executes in RAM at a nominal supply voltage of 3.0V.
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
Temperature (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP
ILPM0,1MHz
Low-power mode 0 (3)
(4)
ILPM2
Low-power mode 2 (5)
(4)
ILPM3,XT1LF
ILPM3,XT1LF
ILPM3,VLO
ILPM4
Low-power mode 3, crystal
mode (6) (4)
Low-power mode 3, crystal
mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
Low-power mode 4 (8)
25°C
TYP
85°C
MAX
TYP
2.2 V
0
70
75
3V
3
81
87
2.2 V
0
5.9
6.5
3V
3
6.7
7.3
0
1.50
2.0
7.8
1
1.65
2.2
8.3
2
1.80
2.4
8.6
3
1.84
2.4
8.6
0
2.0
2.5
8.5
1
2.1
2.7
9.0
2
2.3
2.9
9.3
3
2.3
2.9
9.3
0
1.3
1.7
7.5
1
1.3
1.8
7.9
2
1.4
1.9
8.2
3
1.4
1.9
8.2
0
1.2
1.6
7.4
1
1.2
1.7
7.8
2
1.3
1.7
7.9
3
2.2 V
3V
3V
(4)
MAX
3V
UNIT
MAX
86
105
100
130
12.5
18
13.8
1.3
1.7
8.0
0.7
0.9
1.4
30
µA
µA
µA
µA
25
µA
25.0
µA
23.0
ILPM3.5
Low-power mode 3.5, RTC
active on AUXVCC3 (9)
2.2V
3.0V
1.0
1.2
1.5
1.8
3.0
ILPM4.5
Low-power mode 4.5 (10)
3.0V
0.6
0.7
1.0
1.2
2.0
µA
µA
(1)
(2)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting
= 1 MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer and RTC clocked by low frequency clock included. ACLK = low frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer and RTC clocked by low frequency clock included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply
(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
Temperature (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP
ILPM3
LCD,
ext. bias
ILPM3
LCD,
int. bias
Low-power mode 3 (LPM3)
current, LCD 4-mux mode,
external biasing (3) (4)
Low-power mode 3 (LPM3)
current, LCD 4-mux mode,
internal biasing, charge
pump disabled (3) (5)
3V
3V
2.2 V
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
(5)
(6)
60
Low-power mode 3 (LPM3)
current, LCD 4-mux mode,
internal biasing, charge
pump enabled (3) (6)
3V
MAX
25°C
TYP
85°C
MAX
TYP
0
2.5
3.1
9.1
1
2.6
3.3
9.5
2
2.8
3.5
9.9
3
2.8
3.5
0
2.9
3.5
9.7
1
3.1
3.7
10.1
2
3.2
4.0
10.5
3
3.3
4.0
0
2.2
2.8
8.8
1
2.3
3.0
9.1
2
2.5
3.2
9.5
0
2.6
3.2
9.3
1
2.8
3.4
9.7
2
2.9
3.6
10.1
3
3.0
3.7
10.2
6.0
5.5
10.0
10.5
UNIT
MAX
µA
25.0
µA
25.0
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0,S2,... = 0, odd segments S1,S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0,S2,... = 0, odd segments S1,S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3V,typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0,S2,... = 0, odd segments S1,S3,... = 1. No LCD panel load.
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MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Schmitt-Trigger Inputs – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.85
3V
0.4
1.0
20
TYP
35
MAX
UNIT
V
V
V
50
kΩ
5
pF
Inputs – Ports P1 and P2 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t(int)
(1)
(2)
PARAMETER
TEST CONDITIONS
VCC
External interrupt timing (2)
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
2.2 V, 3 V
MIN
MAX
UNIT
20
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Leakage Current – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
High-impedance leakage current
TEST CONDITIONS
(1) (2)
VCC
MIN
MAX
UNIT
1.8 V, 3 V
-50
+50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
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Outputs – General Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA
VOH
High-level output voltage
VCC
(1)
1.8 V
I(OHmax) = –10 mA (1)
I(OHmax) = –5 mA (1)
3V
I(OHmax) = –15 mA (1)
I(OLmax) = 3 mA
VOL
Low-level output voltage
(2)
1.8 V
I(OLmax) = 10 mA (3)
I(OLmax) = 5 mA (2)
3V
I(OLmax) = 15 mA (3)
(1)
(2)
(3)
MIN
MAX
1.55
1.80
1.20
1.80
2.75
3.00
2.40
3.00
0.00
0.25
0.00
0.60
0.00
0.25
0.00
0.60
UNIT
V
V
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Recommended Operating Conditions for more details.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.
Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA
VOH
High-level output voltage
VCC
(2)
1.8 V
I(OHmax) = –3 mA (2)
I(OHmax) = –2 mA (2)
3V
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA
VOL
Low-level output voltage
(3)
1.8 V
I(OLmax) = 3 mA (4)
I(OLmax) = 2 mA (3)
3V
I(OLmax) = 6 mA (4)
(1)
(2)
(3)
(4)
MIN
MAX
1.55
1.80
1.20
1.80
2.75
3.00
2.40
3.00
0.00
0.25
0.00
0.60
0.00
0.25
0.00
0.60
UNIT
V
V
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Recommended Operating Conditions for more details.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
Output Frequency – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(1) (2)
fPx.y
Port output frequency (with load)
fPort_CLK
(1)
(2)
62
Clock output frequency
ACLK
SMCLK
MCLK
CL = 20 pF (2)
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
VCC = 1.8 V,
PMMCOREVx = 0
16
VCC = 3 V,
PMMCOREVx = 3
25
MHz
MHz
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
8
20
18
7
IOL – Low-Level Output Current – mA
IOL – Low-Level Output Current – mA
TA = 25°C
16
TA = 85°C
14
12
10
8
6
4
TA = 85°C
5
4
3
2
1
VCC = 3 V
Reduced Drive Strength
2
TA = 25°C
6
VCC = 1.8 V
Reduced Drive Strength
0
0
0
0.5
1
1.5
2
2.5
0
3
0.2
VOL – Low-Level Output Voltage – V
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VOL – Low-Level Output Voltage – V
Figure 3.
Figure 4.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 1.8 V
Reduced Drive Strength
VCC = 3 V
Reduced Drive Strength
IOH – High-Level Output Current – mA
IOH – High-Level Output Current – mA
-1
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-2
-3
-4
-5
TA = 85°C
-6
-7
TA = 25°C
-8
-25
0
0.5
1
1.5
2
VOH – High-Level Output Voltage – V
Figure 5.
Copyright © 2012–2013, Texas Instruments Incorporated
2.5
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VOH – High-Level Output Voltage – V
Figure 6.
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Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
60
IOL – Low-Level Output Current – mA
IOL – Low-Level Output Current – mA
50
TA = 25°C
TA = 85°C
40
30
20
10
20
TA = 25°C
TA = 85°C
15
10
5
VCC = 1.8 V
Full Drive Strength
VCC = 3 V
Full Drive Strength
0
0
0
0.5
1
1.5
2
2.5
3
0
0.2
VOL – Low-Level Output Voltage – V
0.6
0.8
1
1.2
1.4
1.6
1.8
VOL – Low-Level Output Voltage – V
Figure 7.
Figure 8.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 1.8 V
Full Drive Strength
VCC = 3 V
Full Drive Strength
IOH – High-Level Output Current – mA
-10
IOH – High-Level Output Current – mA
0.4
-20
-30
-40
TA = 85°C
-50
-5
-10
-15
TA = 85°C
-20
TA = 25°C
TA = 25°C
-25
-60
0
0.5
1
1.5
2
VOH – High-Level Output Voltage – V
Figure 9.
64
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2.5
3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VOH – High-Level Output Voltage – V
Figure 10.
Copyright © 2012–2013, Texas Instruments Incorporated
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ΔIDVCC.LF
Differential XT1 oscillator
crystal current consumption
from lowest drive setting, LF
mode
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 2, TA = 25°C
3V
0.170
0.290
XTS = 0, XT1BYPASS = 0
32768
XT1 oscillator crystal
frequency, LF mode
fXT1,LF,SW
XT1 oscillator logic-level
square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2)
LF mode
OALF
Oscillation allowance for
LF crystals (4)
(3)
10
fFault,LF
tSTART,LF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
32.768
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
UNIT
µA
Hz
50
kHz
kΩ
XTS = 0, XCAPx = 0 (6)
CL,eff
MAX
0.075
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
fXT1,LF0
Integrated effective load
capacitance, LF mode (5)
TYP
2
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
pF
Duty cycle, LF mode
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
30
70
%
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
10
10000
Hz
Startup time, LF mode
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
1000
3V
ms
500
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
(d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
Measured at ACLK
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
MIN
TYP
MAX
6
9.6
15
0.5
kHz
%/°C
4
40
UNIT
%/V
50
60
TYP
MAX
%
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
TEST CONDITIONS
VCC
MIN
TA = 25°C
1.8 V to 3.6 V
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
Full temperature range
1.8 V to 3.6 V
-3.5
+3.5
%
3V
-1.5
+1.5
%
REFO absolute tolerance calibrated
TA = 25°C
3
µA
32768
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK
1.8 V to 3.6 V
0.01
dfREFO/dVCC
REFO frequency supply voltage drift
Measured at ACLK
1.8 V to 3.6 V
1.0
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO startup time
40%/60% duty cycle
1.8 V to 3.6 V
tSTART
UNIT
REFO oscillator current consumption
40
50
Hz
%/°C
%/V
60
25
%
µs
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fDCO(0,0)
TEST CONDITIONS
DCO frequency (0, 0) (1)
(1)
MAX
UNIT
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
MIN
TYP
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0) (1)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31) (1)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
(1)
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31) (1)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0) (1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31) (1)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
(1)
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31) (1)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0) (1)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
(1)
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0) (1)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31) (1)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
(1)
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31) (1)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
DCO frequency temperature drift
fDCO = 1 MHz
dfDCO/dT
(1)
66
40
50
0.1
60
%
%/°C
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap
31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
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MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
DCO Frequency (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
dfDCO/dVCORE
TEST CONDITIONS
DCO frequency voltage drift
MIN
fDCO = 1 MHz
TYP
MAX
1.9
UNIT
%/V
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 11. Typical DCO Frequency
PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage,
DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage,
DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET
Pulse duration required at RST/NMI pin to
accept a reset
MIN
0.80
TYP
1.20
50
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.91
V
VCORE2(AM)
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.81
V
VCORE1(AM)
Core voltage, active mode,
PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V
1.61
V
VCORE0(AM)
Core voltage, active mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.41
V
VCORE3(LPM)
Core voltage, low-current
mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.94
V
VCORE2(LPM)
Core voltage, low-current
mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.92
V
VCORE1(LPM)
Core voltage, low-current
mode, PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V
1.73
V
VCORE0(LPM)
Core voltage, low-current
mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.52
V
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PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT–)
V(SVSH_IT+)
SVSH on voltage level
SVSH off voltage level
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on or off delay time
dVDVCC/dt
DVCC rise time
68
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TYP
MAX
0
UNIT
nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
200
nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.60
1.65
1.75
SVSHE = 1, SVSHRVL = 1
1.77
1.84
1.95
SVSHE = 1, SVSHRVL = 2
1.93
2.00
2.12
SVSHE = 1, SVSHRVL = 3
2.09
2.16
2.29
SVSHE = 1, SVSMHRRL = 0
1.65
1.75
1.85
SVSHE = 1, SVSMHRRL = 1
1.85
1.95
2.05
SVSHE = 1, SVSMHRRL = 2
2.05
2.15
2.25
SVSHE = 1, SVSMHRRL = 3
2.15
2.25
2.35
SVSHE = 1, SVSMHRRL = 4
2.30
2.40
2.55
SVSHE = 1, SVSMHRRL = 5
2.57
2.70
2.83
SVSHE = 1, SVSMHRRL = 6
2.90
3.05
3.20
SVSHE = 1, SVSMHRRL = 7
2.90
3.05
3.20
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
20
SVSHE = 0 → 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
12.5
SVSHE = 0 → 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
100
0
V
V
µs
µs
1000
V/s
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
V(SVMH)
SVMH current consumption
SVMH on or off voltage level
(1)
t(SVMH)
(1)
SVMH propagation delay
SVMH on or off delay time
MAX
UNIT
0
nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
200
nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
1.5
µA
SVMHE = 1, SVSMHRRL = 0
1.63
1.73
1.83
SVMHE = 1, SVSMHRRL = 1
1.83
1.93
2.03
SVMHE = 1, SVSMHRRL = 2
2.03
2.13
2.23
SVMHE = 1, SVSMHRRL = 3
2.13
2.23
2.33
SVMHE = 1, SVSMHRRL = 4
2.28
2.40
2.53
SVMHE = 1, SVSMHRRL = 5
2.55
2.70
2.81
SVMHE = 1, SVSMHRRL = 6
2.88
3.02
3.18
SVMHE = 1, SVSMHRRL = 7
2.88
3.02
3.18
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
TYP
V
3.77
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
SVMHE = 0 → 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
12.5
SVMHE = 0 → 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
100
µs
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.
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PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on or off delay time
TYP
MAX
0
UNIT
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
µA
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
20
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
12.5
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
100
µs
µs
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
t(SVML)
SVML propagation delay
SVML on or off delay time
TYP
MAX
UNIT
0
nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
1.5
µA
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
12.5
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
100
µs
µs
Wake-Up From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tWAKE-UP-FAST
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode (1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-SLOW
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode (2)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-LPM4.5
tWAKE-UP-RESET
(1)
(2)
(3)
70
MIN
TYP
MAX
fMCLK ≥ 4.0 MHz
5
fMCLK < 4.0 MHz
10
UNIT
µs
150
165
µs
Wake-up time from LPM4.5 to
active mode (3)
2
3
ms
Wake-up time from RST or
BOR event to active mode (3)
2
3
ms
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
This value represents the time from the wakeup event to the reset vector execution.
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Auxiliary Supplies Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
NOM
MAX
Supply voltage range for all supplies at pins DVCC, AVCC, AUX1, AUX2, AUX3
1.8
3.6
PMMCOREVx = 0
1.8
3.6
PMMCOREVx = 1
2.0
3.6
PMMCOREVx = 2
2.2
3.6
PMMCOREVx = 3
2.4
3.6
UNIT
V
VDSYS
Digital system supply voltage range,
VDSYS = VCC – RON × ILOAD
VASYS
Analog system supply voltage range, VASYS = VCC – RON × ILOAD
TA
Ambient temperature range
TA,HTOL
Ambient temperature during HTOL (module should be functional during HTOL)
CVCC,CAUX1/2
Recommended capacitor at pins DVCC, AVCC, AUX1, AUX2
4.7
µF
CVSYS
Recommended capacitor at pins VDSYS1, VDSYS2 and VASYS1, VASYS2
4.7
µF
CVCORE
Recommended capacitance at pin VCORE
0.47
µF
CAUX3
Recommended capacitor at pin AUX3
0.47
µF
See modules
-40
V
V
85
150
°C
°C
Auxiliary Supplies - AUX3 (Backup Subsystem) Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IAUX3,RTCon
AUX3 current with RTC
enabled
RTC and 32-kHz oscillator in
backup subsystem enabled
3V
IAUX3,RTCoff
AUX3 current with RTC
disabled
RTC and 32-kHz oscillator in
backup subsystem disabled
3V
TA
MIN
TYP
MAX
25°C
0.86
85°C
1.2
25°C
120
85°C
220
UNIT
µA
nA
Auxiliary Supplies - Auxiliary Supply Monitor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC,Monitor
Average supply current
for monitoring circuitry
drawn from VDSYS
LOCKAUX = 0, AUXMRx = 0
AUX0MD = 0, AUX1MD = 0, AUX2MD
= 1,
VDSYS = DVCC, VASYS = AVCC,
Current measured at VDSYS
1.10
µA
IMeas,Montior
Average current drawn
from monitored supply
during measurement
cycle
LOCKAUX = 0, AUXMRx = 0
AUX0MD = 0, AUX1MD = 0, AUX2MD
= 1,
VDSYS = DVCC, VASYS = AVCC,
Current measured at AUXVCC1
0.13
µA
General
VSVMH
(SVSMHRRLx
= AUXLVLx)
VSVMH
(SVSMHRRLx
= AUXLVLx)
X - 5%
VMonitor
Auxiliary supply
threshold level (same as
high-side SVM)
VSVMH
(SVSMHRRLx
= AUXLVLx)
X + 5%
AUXLVLx = 0
1.65
1.75
1.85
AUXLVLx = 1
1.85
1.95
2.05
AUXLVLx = 2
2.05
2.15
2.25
AUXLVLx = 3
2.15
2.25
2.35
AUXLVLx = 4
2.30
2.40
2.55
AUXLVLx = 5
2.57
2.70
2.83
AUXLVLx = 6
2.90
3.00
3.20
AUXLVLx = 7
2.90
3.00
3.20
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Auxiliary Supplies - Switch On-Resistance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RON,DVCC
On-resistance of switch
between DVCC and VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
Ω
RON,DAUX1
On-resistance of switch
between AUX1 and VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
Ω
RON,DAUX2
On-resistance of switch
between AUX2 and VDSYS
ILOAD = ICORE + IIO = 10 mA + 10 mA = 20 mA
5
Ω
RON,AVCC
On-resistance of switch
between AVCC and VASYS
ILOAD = IModules = 10 mA
5
Ω
RON,AAUX1
On-resistance of switch
between AUX1 and VASYS
ILOAD = IModules = 5 mA
20
Ω
RON,AAUX2
On-resistance of switch
between AUX2 and VASYS
ILOAD = IModules = 5 mA
20
Ω
Auxiliary Supplies - Switching Time
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tSwitch
Time from occurrence of trigger (SVM or software)
to "new" supply connected to system supplies
tRecover
"Recovery time" after a switch over took place.
During that time no further switching takes place.
VCC
MIN
TYP
170
MAX
UNIT
100
ns
480
µs
Auxiliary Supplies - Switch Leakage
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISW,Lkg
Current into DVCC, AVCC, AUX1, or
AUX2 if not selected
IVmax
Current drawn from highest supply
VCC
MIN
Per supply (but not the highest
supply)
TYP
MAX
UNIT
75
250
nA
500
700
nA
UNIT
Auxiliary Supplies - Auxiliary Supplies to ADC10_A
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Supply voltage divider
V3 = VSupply/3
V3
RV3
Load resistance
tSample,V3
Sampling time required if V3
selected.
Error of conversion
result ≤ 1 LSB
VCC
MIN
TYP
MAX
1.8 V
0.57
0.6
0.63
3V
0.95
1.0
1.05
3.6 V
1.14
1.2
1.26
V
AUXADCRx = 0
15
kΩ
AUXADCRx = 1
1.5
kΩ
AUXADCRx = 2
0.6
kΩ
AUXADCRx = 0
1000
ns
AUXADCRx = 1
1000
ns
AUXADCRx = 2
1000
ns
Auxiliary Supplies - Charge Limiting Resistor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RCHARGE
72
Charge limiting resistor
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TEST CONDITIONS
VCC
MIN
TYP
MAX
CHCx = 1
3V
5
CHCx = 2
3V
10
CHCx = 3
3V
20
UNIT
kΩ
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ± 10%
1.8 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse duration required for
capture.
1.8 V, 3 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
5
MHz
UNIT
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
UCGLITx = 0
UCGLITx = 1
UART receive deglitch time (1)
tt
UCGLITx = 2
2 V, 3 V
UCGLITx = 3
(1)
MIN
TYP
MAX
10
15
25
30
50
85
50
80
150
70
120
200
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
feUSCI
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK or ACLK,
Duty cycle = 50% ± 10%
eUSCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
MAX
UNIT
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
tSTE,LEAD
STE lead time, STE low to clock
tSTE,LAG
STE lag time, Last clock to STE
high
VCC
MIN
UCSTEM = 0, UCMODEx = 01 or 10
TEST CONDITIONS
2 V, 3 V
150
UCSTEM = 1, UCMODEx = 01 or 10
2 V, 3 V
150
UCSTEM = 0, UCMODEx = 01 or 10
2 V, 3 V
200
UCSTEM = 1, UCMODEx = 01 or 10
2 V, 3 V
200
UCSTEM = 0, UCMODEx = 01 or 10
tSTE,ACC
STE access time, STE low to
SIMO data out
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
tSTE,DIS
STE disable time, STE high to
SIMO high impedance
UCSTEM = 1, UCMODEx = 01 or 10
tSU,MI
(1)
SOMI input data setup time
TYP
ns
ns
2V
50
3V
30
2V
50
3V
30
2V
40
3V
25
2V
40
3V
ns
ns
25
2V
50
3V
30
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
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eUSCI (SPI Master Mode) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(2)
(3)
VCC
MIN
2V
0
3V
0
TYP
MAX
ns
2V
9
3V
5
2V
0
3V
0
UNIT
ns
ns
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 12 and Figure 13.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 12 and Figure 13.
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 12. SPI Master Mode, CKPH = 0
74
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 13. SPI Master Mode, CKPH = 1
eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE low to clock
tSTE,LAG
STE lag time, Last clock to STE high
tSTE,ACC
STE access time, STE low to SOMI data out
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
2V
4
3V
3
2V
0
3V
0
TYP
MAX
ns
ns
2V
46
3V
24
2V
38
3V
25
2V
2
3V
1
2V
2
3V
2
55
32
3V
16
ns
ns
3V
24
ns
ns
2V
2V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 14 and Figure 15.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 14
and Figure 15.
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 14. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 15. SPI Slave Mode, CKPH = 1
76
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eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
VCC
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2 V, 3 V
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
2 V, 3 V
2 V, 3 V
2 V, 3 V
fSCL = 100 kHz
tSU,DAT
Data setup time
tSU,STO
Setup time for STOP
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
2 V, 3 V
2 V, 3 V
UCGLITx = 0
Pulse duration of spikes suppressed by input
filter
tSP
TYP
UCGLITx = 1
UCGLITx = 2
2 V, 3 V
UCGLITx = 3
0
Clock low timeout
UCCLTOx = 2
tSU,STA
fSYSTEM
MHz
400
kHz
µs
1.5
5.1
µs
1.4
0.4
µs
5.0
µs
1.3
5.2
µs
1.7
75
220
ns
35
120
ns
30
60
ns
20
35
ns
2 V, 3 V
UCCLTOx = 3
tHD,STA
UNIT
5.1
UCCLTOx = 1
tTIMEOUT
MAX
tHD,STA
30
ms
33
ms
37
ms
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 16. I2C Mode Timing
Schmitt-Trigger Inputs – RTC Tamper Detect Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN =
AUXVCC3
CI
Input capacitance
VIN = VSS or AUXVCC3
Copyright © 2012–2013, Texas Instruments Incorporated
AUXVCC3
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.85
3V
0.4
1.0
20
TYP
35
MAX
50
5
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UNIT
V
V
V
kΩ
pF
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Inputs – RTC Tamper Detect Pin (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t(int)
(1)
(2)
PARAMETER
TEST CONDITIONS
AUXVCC3
MIN
External interrupt timing (2)
Port P1, P2: P1.x to P2.x, External trigger pulse duration
to set interrupt flag
2.2 V, 3 V
20
MAX
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Leakage Current – RTC Tamper Detect Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AUXVCC3
MIN
MAX
UNIT
-50
+50
nA
(1) (2)
Ilkg(Px.y)
(1)
(2)
1.8 V,
3V
High-impedance leakage current
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Outputs – RTC Tamper Detect Pin
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –100 µA (1)
VOH
High-level output voltage
I(OHmax) = –200µA (1)
I(OHmax) = –100µA (1)
I(OHmax) = –200µA (1)
I(OLmax) = 100µA
VOL
Low-level output voltage
78
1.8 V
3V
(1)
I(OLmax) = 200µA (1)
I(OLmax) = 100µA (1)
I(OLmax) = 200µA (1)
(1)
AUXVCC3
1.8 V
3V
MIN
MAX
1.50
1.80
1.20
1.80
2.70
3.00
2.40
3.00
0.00
0.25
0.00
0.60
0.00
0.25
0.00
0.60
UNIT
V
V
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Recommended Operating Conditions for more details.
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LCD_C Recommended Operating Conditions
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
VCC,LCD_C,CP en,3.6
Supply voltage range,
LCDCPEN = 1, 0000 < VLCDx ≤ 1111 (charge
charge pump enabled,
pump enabled, VLCD ≤ 3.6 V)
VLCD ≤ 3.6 V
2.2
3.6
V
VCC,LCD_C,CP en,3.3
Supply voltage range,
LCDCPEN = 1, 0000 < VLCDx ≤ 1100 (charge
charge pump enabled,
pump enabled, VLCD ≤ 3.3 V)
VLCD ≤ 3.3 V
2.0
3.6
V
VCC,LCD_C,int. bias
Supply voltage range,
internal biasing,
LCDCPEN = 0, VLCDEXT = 0
charge pump disabled
2.4
3.6
V
VCC,LCD_C,ext.
Supply voltage range,
external biasing,
LCDCPEN = 0, VLCDEXT = 0
charge pump disabled
2.4
3.6
V
VCC,LCD_C,VLCDEXT
Supply voltage range,
external LCD voltage,
internal or external
biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage
at LCDCAP/R33,
internal or external
biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor on LCDCAP
LCDCPEN = 1, VLCDx > 0000 (charge pump
when charge pump
enabled)
enabled
10
µF
fFrame
LCD frame frequency
range
100
Hz
fACLK,in
ACLK input frequency
range
40
kHz
CPanel
Panel capacitance
100-Hz frame frequency
10000
pF
VR33
Analog input voltage
at R33
LCDCPEN = 0, VLCDEXT = 1
VCC+0.2
V
VR23,1/3bias
Analog input voltage
at R23
LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0
VR03 +
VR13 2/3*(VR33
-VR03)
VR33
V
VR13,1/3bias
Analog input voltage
at R13 with 1/3
biasing
LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0
VR03 +
VR03 1/3*(VR33
-VR03)
VR23
V
VR13,1/2bias
Analog input voltage
at R13 with 1/2
biasing
LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1
VR03 +
VR03 1/2*(VR33
-VR03)
VR33
V
VR03
Analog input voltage
at R03
R0EXT = 1
VSS
VLCD-VR03
Voltage difference
between VLCD and
R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF/R13
External LCD
reference voltage
applied at
LCDREF/R13
VLCDREFx = 01
0.8
bias
fLCD = 2 × mux × fFRAME with mux = 1 (static), 2,
3, 4.
4.7
0
30
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4.7
32
2.4
V
1.2
VCC+0.2
V
1.5
V
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LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLCD
LCD voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VLCDx = 0000, VLCDEXT = 0
2.4 V to 3.6 V
VCC
V
LCDCPEN = 1, VLCDx = 0001
2 V to 3.6 V
2.60
V
LCDCPEN = 1, VLCDx = 0010
2 V to 3.6 V
2.66
V
LCDCPEN = 1, VLCDx = 0011
2 V to 3.6 V
2.72
V
LCDCPEN = 1, VLCDx = 0100
2 V to 3.6 V
2.78
V
LCDCPEN = 1, VLCDx = 0101
2 V to 3.6 V
2.84
V
LCDCPEN = 1, VLCDx = 0110
2 V to 3.6 V
2.90
V
LCDCPEN = 1, VLCDx = 0111
2 V to 3.6 V
2.96
V
LCDCPEN = 1, VLCDx = 1000
2 V to 3.6 V
3.02
V
LCDCPEN = 1, VLCDx = 1001
2 V to 3.6 V
3.08
V
LCDCPEN = 1, VLCDx = 1010
2 V to 3.6 V
3.14
V
LCDCPEN = 1, VLCDx = 1011
2 V to 3.6 V
3.20
V
LCDCPEN = 1, VLCDx = 1100
2 V to 3.6 V
3.26
V
LCDCPEN = 1, VLCDx = 1101
2.2 V to 3.6 V
3.32
V
LCDCPEN = 1, VLCDx = 1110
2.2 V to 3.6 V
3.38
LCDCPEN = 1, VLCDx = 1111
2.2 V to 3.6 V
3.50
V
3.72
V
ICC,Peak,CP
Peak supply currents due to charge
pump activities
LCDCPEN = 1, VLCDx = 1111
2.2 V
200
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
100
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000, ILOAD
= ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000, ILOAD
= ±10 µA
2.2 V
10
kΩ
80
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µA
500
50
ms
µA
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SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
SD24_B Power Supply and Recommended Operating Conditions
MIN
AVCC
Analog supply voltage
TA
Ambient temperature
fSD
Modulator clock frequency
VI
VIC
VID,FS
AVCC = DVCC, AVSS = DVSS = 0 V
(1)
(2)
V
85
°C
0.03
2.3
MHz
Absolute input voltage range
AVSS - 1V
AVCC
V
Common-mode input voltage range
AVSS - 1V
AVCC
V
VREF/GAIN
+VREF/GAIN
0
+VREF/GAIN
Differential full scale input voltage
VREF load capacitance (2)
Bipolar Mode, VID = VI,A+ - VI,AUnipolar Mode, VID = VI,A+ - VI,A-
REFON = 1
SD24GAINx = 1
±900
±930
SD24GAINx = 2
±450
±460
SD24GAINx = 4
±225
±230
SD24GAINx = 8
±112
±120
SD24GAINx = 16
±56
±60
SD24GAINx = 32
±28
±30
SD24GAINx = 64
±14
±14
±7
±7.25
SD24REFS = 1
100
(1)
nF
Input capacitance
TEST CONDITIONS
VCC
MIN
Input impedance
(pin A+ or A- to AVSS)
Differential input impedance
(pin A+ to pin A-)
TYP
SD24GAINx = 1
5.0
SD24GAINx = 2
5.0
SD24GAINx = 4
5.0
SD24GAINx = 8
5.0
SD24GAINx = 16
5.0
SD24GAINx = 32, 64, 128
ZID
mV
(1)
PARAMETER
ZI
mV
The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS-= -VREF/GAIN: FSR = VFS+ - VFS-= 2*VREF/GAIN. If VREF is sourced
externally, the analog input range should not exceed 80% of VFS+ or VFS-; that is, VID = 0.8 VFS- to 0.8 VFS+. If VREF is sourced internally,
the given VID ranges apply. MIN values are calculated based on a VREF of 1.125V. TYP values are calculated based on a VREF of 1.16
V.
There is no capacitance required on VREF. However, a capacitance of 100nF is recommended to reduce any reference voltage noise.
SD24_B Analog Input
CI
UNIT
-40
SD24GAINx =
128
CREF
MAX
3.6
Differential input voltage for specified
performance (1)
VID
TYP
2.4
fSD24 = 1MHz
fSD24 = 1MHz
MAX
UNIT
pF
5.0
SD24GAINx = 1
3V
200
SD24GAINx = 8
3V
200
SD24GAINx = 32
3V
SD24GAINx = 1
3V
SD24GAINx = 8
3V
SD24GAINx = 32
3V
kΩ
200
300
400
400
300
kΩ
400
All parameters pertain to each SD24_B converter.
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1600
Input Leakage Current – nA
1400
1200
1000
800
600
400
200
0
-200
-1
-0.5
0
0.5
1
1.5
2
2.5
3
Input Voltage – V
Figure 17. Input Leakage Current vs Input Voltage (Modulator OFF)
SD24_B Supply Currents
PARAMETER
ISD,256
ISD,512
TEST CONDITIONS
Analog plus digital supply current per
converter (reference not included)
Analog plus digital supply current per
converter (reference not included)
fSD24 = 1 MHz,
SD24OSR = 256
fSD24 = 2 MHz,
SD24OSR = 512
TYP
MAX
SD24GAIN: 1
VCC
3V
MIN
490
600
SD24GAIN: 2
3V
490
600
SD24GAIN: 4
3V
490
600
SD24GAIN: 8
3V
559
700
SD24GAIN: 16
3V
559
700
SD24GAIN: 32
3V
627
800
SD24GAIN: 64
3V
627
800
SD24GAIN: 128
3V
627
800
SD24GAIN: 1
3V
600
700
SD24GAIN: 8
3V
677
800
SD24GAIN: 32
3V
740
900
UNIT
µA
µA
SD24_B Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
PARAMETER
INL
Gnom
82
Integral nonlinearity, endpoint fit
Nominal gain
TEST CONDITIONS
MIN
TYP
MAX
SD24GAIN: 1
3V
-0.01
+0.01
SD24GAIN: 8
3V
-0.01
+0.01
SD24GAIN: 32
3V
-0.01
+0.01
SD24GAIN: 1
3V
1
SD24GAIN: 2
3V
2
SD24GAIN: 4
3V
4
SD24GAIN: 8
3V
8
SD24GAIN: 16
3V
16
SD24GAIN: 32
3V
32
SD24GAIN: 64
3V
64
SD24GAIN: 128
3V
128
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UNIT
% of FSR
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SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
PARAMETER
TEST CONDITIONS
Gain error (1)
EG
ΔEG/ΔT
Gain error temperature
coefficient (2), internal
reference
ΔEG/ΔT
Gain error temperature
coefficient (2), external
reference
ΔEG/ΔVCC
EOS[V]
EOS[FS]
ΔEOS/ΔT
ΔEOS/ΔVCC
CMRR,DC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Gain error vs VCC
(3)
Offset error (4)
Offset error (4)
Offset error temperature
coefficient (5)
Offset error vs VCC
(6)
Common mode rejection at
DC (7)
MIN
TYP
MAX
UNIT
SD24GAIN: 1, with external reference (1.2 V)
3V
-1
+1
SD24GAIN: 8, with external reference (1.2 V)
3V
-2
+2
SD24GAIN: 32, with external reference (1.2 V)
3V
-2
+2
SD24GAIN: 1, 8, or 32 (with internal reference)
3V
80
SD24GAIN: 1 (with external reference)
3V
15
SD24GAIN: 8 (with external reference)
3V
15
SD24GAIN: 32 (with external reference)
3V
15
SD24GAIN: 1
3V
0.1
SD24GAIN: 8
3V
0.1
SD24GAIN: 32
3V
0.4
SD24GAIN: 1 (with Vdiff = 0V)
3V
SD24GAIN: 8
3V
1
SD24GAIN: 32
3V
0.5
SD24GAIN: 1 (with Vdiff = 0V)
3V
-0.2
+0.2
% FS
SD24GAIN: 8
3V
-0.7
+0.7
% FS
SD24GAIN: 32
3V
-1.4
+1.4
% FS
SD24GAIN: 1
3V
2
SD24GAIN: 8
3V
0.25
SD24GAIN: 32
3V
0.1
SD24GAIN: 1
3V
500
SD24GAIN: 8
3V
125
SD24GAIN: 32
3V
50
SD24GAIN: 1
3V
-120
SD24GAIN: 8
3V
-110
SD24GAIN: 32
3V
-100
%
ppm/°C
ppm/°C
%/V
2.3
mV
µV/°C
µV/V
dB
The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact - Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
The gain error temperature coefficient ΔEG/ ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) Gnom)/Gnom) using the box method (that is, minimum and maximum values):
ΔEG/ ΔT = (MAX(EG(T)) - MIN(EG(T) ) / (MAX(T) - MIN(T)) = (MAX(Gact(T)) - MIN(Gact(T)) / Gnom / (MAX(T) - MIN(T))
with T ranging from -40°C to +85°C.
The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) Gnom)/Gnom) using the box method (that is, minimum and maximum values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) - MIN(EG(VCC) ) / (MAX(VCC) - MIN(VCC)) = (MAX(Gact(VCC)) - MIN(Gact(VCC)) / Gnom / (MAX(VCC) MIN(VCC))
with VCC ranging from 2.4V to 3.6V.
The offset error EOS is measured with shorted inputs in 2s complement mode with +100% FS = VREF/G and -100% FS = -VREF/G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]×G/VREF; EOS [V] = EOS [FS]×VREF/G.
The offset error temperature coefficient ΔEOS/ ΔT specifies the variation of the offset error EOS over temperature using the box method
(that is, minimum and maximum values):
ΔEOS/ ΔT = (MAX(EOS(T)) - MIN(EOS(T) ) / (MAX(T) - MIN(T))
with T ranging from -40°C to +85°C.
The offset error vs VCC ΔEOS/ ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is,
minimum and maximum values):
ΔEOS/ ΔVCC = (MAX(EOS(VCC)) - MIN(EOS(VCC) ) / (MAX(VCC) - MIN(VCC))
with VCC ranging from 2.4V to 3.6V.
The DC CMRR specifies the change in the measured differential input voltage value when the common mode voltage varies:
DC CMRR = -20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when
sweeping the common mode voltage.
The DC CMRR is measured with both inputs connected to the common mode voltage (that is, no differential input signal is applied), and
the common mode voltage is swept from -1V to VCC.
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SD24_B Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
PARAMETER
CMRR,50Hz
AC
PSRR,ext
AC
PSRR,int
XT
Common mode rejection at
50 Hz (8)
AC power supply rejection
ratio, external reference (9)
AC power supply rejection
ratio, internal reference (9)
Crosstalk between
converters (10)
TEST CONDITIONS
MIN
TYP
SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV
3V
-120
SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV
3V
-110
SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV
3V
-100
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz
-61
SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz
-75
SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz
-79
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz
-61
SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz
-75
SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC ×
t), fVCC = 50 Hz
-79
Crosstalk source: SD24GAIN: 1, Sine-wave with
maximum possible Vpp, fIN = 50 Hz, 100 Hz,
Converter under test: SD24GAIN: 1
3V
-120
Crosstalk source: SD24GAIN: 1, Sine-wave with
maximum possible Vpp, fIN = 50 Hz, 100 Hz,
Converter under test: SD24GAIN: 8
3V
-115
Crosstalk source: SD24GAIN: 1, Sine-wave with
maximum possible Vpp, fIN = 50 Hz, 100 Hz,
Converter under test: SD24GAIN: 32
3V
-110
MAX
UNIT
dB
dB
dB
dB
(8)
The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common mode ripple
applied to the inputs of the ADC and the actual common mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] - 20log(VCM/1.2V/G) [dBFS] with a common mode signal of VCM × sin(2π × fCM × t) applied to the analog
inputs.
The AC CMRR is measured with the both inputs connected to the common mode signal; that is, no differential input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple
applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] - 20log(50mV/1.2V/G) [dBFS] with a signal of 50mV × sin(2π × fVCC × t) added to VCC.
The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50mV/1.2V/1) = -27.6 dBFS
SD24GAIN: 8 → Hypothetical signal: 20log(50mV/1.2V/8) = -9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50mV/1.2V/32) = 2.5 dBFS
(10) The crosstalk XT is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under
test. It is measured with the inputs of the converter under test being grounded.
84
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SD24_B, AC Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
PARAMETER
SINAD
THD
Signal-to-noise +
distortion ratio
Total harmonic distortion
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1
3V
84
86
SD24GAIN: 2
3V
SD24GAIN: 4
3V
SD24GAIN: 8
3V
fIN = 50Hz (1)
SD24GAIN: 16
3V
83
dB
80
3V
3V
67
SD24GAIN: 128
3V
61
SD24GAIN: 1
3V
95
3V
90
3V
86
SD24GAIN: 32
(1)
84
81
SD24GAIN: 64
fIN = 50Hz (1)
UNIT
85
SD24GAIN: 32
SD24GAIN: 8
MAX
71
73
dB
The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t) and VI,A-(t) = 0 V - VPP/2 × sin(2π ×
fIN × t)
resulting in a differential voltage of VID = VI,A+(t) - VI,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed
for a given range (according to SD24_B recommended operating conditions).
SD24_B, AC Performance
fSD24 = 2 MHz, SD24OSRx = 512, SD24REFON = 1
PARAMETER
SINAD
(1)
Signal-to-noise +
distortion ratio
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1
3V
87
SD24GAIN: 2
3V
85
SD24GAIN: 4
3V
84
3V
83
3V
81
SD24GAIN: 32
3V
76
SD24GAIN: 64
3V
71
SD24GAIN: 128
3V
65
SD24GAIN: 8
fIN = 50Hz (1)
SD24GAIN: 16
MAX
UNIT
dB
The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t) and VI,A-(t) = 0 V - VPP/2 × sin(2π ×
fIN × t)
resulting in a differential voltage of VID = VI,A+(t) - VI,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed
for a given range (according to SD24_B recommended operating conditions).
SD24_B, AC Performance
fSD24 = 32 kHz, SD24OSRx = 512, SD24REFON = 1
PARAMETER
SINAD
(1)
Signal-to-noise +
distortion ratio
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1
3V
89
SD24GAIN: 2
3V
85
SD24GAIN: 4
3V
84
SD24GAIN: 8
3V
82
3V
80
SD24GAIN: 32
3V
76
SD24GAIN: 64
3V
67
SD24GAIN: 128
3V
61
SD24GAIN: 16
fIN = 50Hz (1)
MAX
UNIT
dB
The following voltages were applied to the SD24_B inputs: VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t) and VI,A-(t) = 0 V - VPP/2 × sin(2π ×
fIN × t)
resulting in a differential voltage of VID = VI,A+(t) - VI,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed
for a given range (according to SD24_B recommended operating conditions).
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110.0
theoretical limit
(2nd order)
100.0
SINAD − dB
90.0
80.0
70.0
60.0
50.0
10
100
1000
OSR
Figure 18. SINAD vs OSR
(fSD24 = 1MHz, SD24REFON = 1, SD24GAIN: 1)
100.0
SINAD − dB
80.0
60.0
40.0
20.0
0.0
0
0.2
0.4
0.6
Vpp/Vref/Gain
0.8
1
Figure 19. SINAD vs VPP
SD24_B External Reference Input
ensure correct input voltage range according to VREF
VCC
MIN
TYP
MAX
VREF(I) Input voltage
PARAMETER
SD24REFS = 0
3V
1.0
1.20
1.5
V
IREF(I)
SD24REFS = 0
3V
50
nA
86
Input current
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TEST CONDITIONS
UNIT
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10-Bit ADC Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (1)
All ADC10_A pins
Operating supply current into
AVCC terminal, REF module
and reference buffer off
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 00
Operating supply current into
AVCC terminal, REF module
on, reference buffer on
VCC
MIN
TYP
MAX
UNIT
1.8
3.6
V
0
AVCC
V
2.2 V
68
100
3V
78
110
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 01
3V
124
180
µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 10, VEREF = 2.5 V
3V
105
160
µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0,
ADC10SREF = 11, VEREF = 2.5 V
3V
72
110
µA
CI
Input capacitance
Only one terminal Ax can be selected at one time
from the pad to the ADC10_A capacitor array
including wiring and pad.
2.2 V
3.5
RI
Input MUX ON resistance
IADC10_A
(1)
µA
pF
AVCC > 2.0V, 0 V ≤ VAx ≤ AVCC
36
1.8V < AVCC < 2.0V, 0 V ≤ VAx ≤ AVCC
96
kΩ
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to
decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and
MSP430x6xx Family User's Guide (SLAU208).
10-Bit ADC Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC10_A linearity
parameters
2.2 V, 3 V
0.45
5
5.5
MHz
Internal ADC10_A
oscillator (1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
4.4
4.9
5.6
MHz
2.2 V, 3 V
2.4
Conversion time
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4 MHz to 5 MHz
fADC10CLK
fADC10OSC
tCONVERT
TEST CONDITIONS
µs
External fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSEL ≠ 0
tADC10ON
Turn on settling time of
the ADC
tSample
Sampling time
(1)
(2)
(3)
(4)
See
3.0
See
(2)
(3)
100
ns
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (4)
1.8 V
3
µs
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (4)
3V
1
µs
The ADC10OSC is sourced directly from MODOSC inside the UCS.
12 × ADC10DIV × 1/fADC10CLK
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately eight Tau (τ) are needed to get an error of less than ±0.5 LSB
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10-Bit ADC Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
EI
Integral
linearity error
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
ED
Differential
linearity error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
EO
Offset error
EG
ET
VCC
MIN
TYP
MAX
UNIT
-1.0
+1.0
-1.0
+1.0
2.2 V, 3 V
-1.0
+1.0
LSB
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF
2.2 V, 3 V
-1.0
+1.0
LSB
Gain error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V
-1.0
+1.0
LSB
Total unadjusted
error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 20 pF
2.2 V, 3 V
-2.0
+2.0
LSB
MAX
UNIT
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
2.2 V, 3 V
LSB
10-Bit ADC External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VeREF+
Positive external reference
VeREF+ > VREF–/VeREF–
voltage input
(2)
1.4
AVCC
V
VeREF–
Negative external
reference voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
(VeREF+ –
VeREF–)
Differential external
reference voltage input
VeREF+ > VREF–/VeREF–
(4)
1.4
AVCC
V
IVeREF+
IVeREF–
CVREF+
(1)
(2)
(3)
(4)
(5)
88
Static input current
Capacitance at VREF+
terminal
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
-26
+26
µA
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
2.2 V, 3 V
-1
+1
µA
(5)
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
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REF Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF+
Positive built-in reference
voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
REFVSEL = {2} for 2.5 V, REFON = 1
3V
2.47
2.51
2.55
REFVSEL = {1} for 2 V, REFON = 1
3V
1.96
1.99
2.02
2.2 V, 3 V
1.48
1.5
1.52
REFVSEL = {0} for 1.5 V, REFON = 1
AVCC(min)
IREF+
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal (1)
REFVSEL = {0} for 1.5 V
2.2
REFVSEL = {1} for 2 V
2.2
REFVSEL = {2} for 2.5 V
2.7
UNIT
V
V
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3V
18
24
µA
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2 V
3V
16.1
21
µA
fADC10CLK = 5.0 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
3V
14.4
21
µA
< 18
50
ppm/
°C
TCREF+
Temperature coefficient of
built-in reference (2)
IVREF+ = 0 A,
REFVSEL = (0, 1, 2}, REFON = 1
ISENSOR
Operating supply current
into AVCC terminal (3)
REFON = 0, INCH = 0Ah,
ADC10ON = N/A, TA = 30°C
2.2 V
17
22
3V
17
22
VSENSOR
See
ADC10ON = 1, INCH = 0Ah,
TA = 30°C
2.2 V
770
3V
770
VMID
AVCC divider at channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is approximately 0.5 × VAVCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tSENSOR(sample)
Sample time required if
channel 10 is selected (5)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
30
µs
tVMID(sample)
Sample time required if
channel 11 is selected (6)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
1
µs
PSRR_DC
Power supply rejection ratio
(dc)
AVCC = AVCC (min) - AVCC(max),
TA = 25°C,
REFVSEL = (0, 1, 2}, REFON = 1
120
µV/V
PSRR_AC
Power supply rejection ratio
(ac)
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = (0, 1, 2}, REFON = 1
6.4
mV/V
tSETTLE
Settling time of reference
voltage (7)
AVCC = AVCC (min) - AVCC(max),
REFVSEL = (0, 1, 2}, REFON = 0 → 1
75
µs
VSD24REF
SD24_B internal reference
voltage
SD24REFS = 1
3V
1.151 1.1623
tON
SD24_B internal reference
turn-on time
SD24REFS = 0->1, CREF = 100 nF
3V
200
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(4)
µA
mV
1.174
V
V
µs
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
MAX
1.8
3.6
1.8 V
IAVCC_COMP
IAVCC_REF
CBPWRMD = 00, CBON = 1, CBRSx = 00
Comparator operating
supply current into
AVCC, Excludes
CBPWRMD = 01, CBON = 1, CBRSx = 00
reference resistor ladder
Quiescent current of
resistor ladder into
AVCC, Includes REF
module current
VIC
Common mode input
range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
Propagation delay,
response time
tPD
Propagation delay with
filter active
tPD,filter
tEN_CMP
Comparator enable time
tEN_REF
Resistor reference
enable time
TCREF
Temperature coefficient
reference
VCB_REF
Reference voltage for a
given tap
V
40
2.2 V
22
50
3V
32
65
2.2 V, 3
V
10
30
CBPWRMD = 10, CBON = 1, CBRSx = 00
2.2 V, 3
V
0.2
0.85
CBREFACC = 0, CBREFLx = 01, CBRSx = 10,
REFON = 0, CBON = 0
2.2 V, 3
V
10
22
µA
CBREFACC = 1, CBREFLx = 01, CBRSx = 10,
REFON = 0, CBON = 0
2.2 V, 3
V
33
40
µA
0
VCC-1
V
CBPWRMD = 00
-20
+20
mV
CBPWRMD = 01, 10
-20
+20
mV
4
kΩ
µA
5
Series input resistance
UNIT
ON - switch closed
pF
3
OFF - switch opened
50
MΩ
CBPWRMD = 00, CBF = 0
450
ns
CBPWRMD = 01, CBF = 0
600
ns
CBPWRMD = 10, CBF = 0
50
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.30
0.6
1.5
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
0.5
1.0
1.8
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
0.8
1.8
3.4
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
1.5
3.4
6.5
µs
CBON = 0 to CBON = 1, CBPWRMD = 00, 01
1
CBON = 0 to CBON = 1, CBPWRMD = 10
CBON = 0 to CBON = 1
1.0
VIN ×
(n+1.5)
/32
VIN = reference into resistor ladder,
n = 0 to 31
VIN ×
(n+1)
/32
2
µs
50
µs
1.5
µs
50
ppm/
°C
VIN ×
(n+0.5)
/32
V
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DVCC(PGM/ERASE) Program and erase supply voltage
TEST
CONDITIONS
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
15
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank
erase
6
15
mA
90
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Flash Memory (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tCPT
Cumulative program time
TEST
CONDITIONS
See
Data retention duration
TYP
104
105
(1)
MAX
16
Program and erase endurance
tRetention
MIN
TJ = 25°C
UNIT
ms
cycles
100
years
Word or byte program time
See
(2)
64
85
µs
0
Block program time for first byte or word
See
(2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
tBlock,
N
Block program time for last byte or word
See
(2)
55
73
µs
See
(2)
23
32
ms
0
1
MHz
tWord
tBlock,
tErase
Erase time for segment erase, mass erase, and bank erase when
available
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1)
(2)
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V, 3 V
0.025
15
µs
tSBW,
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V/3 V
1
µs
En
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency for 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
2.2 V
15
100
0
5
MHz
10
MHz
80
kΩ
3V
0
2.2 V, 3 V
45
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 Through P1.3 Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
A0..A3
From ADC
P1REN.x
P1DIR.x
DVSS
0
DVCC
1
00
01
10
11
P1OUT.x
00
From Timer_A,
ACLK, ADC10CLK
01
DVSS
11
10
(MSP430F677xIPEU only)
P1.0/TA1.1/VeREF-/A0
P1.1/TA2.1/VeREF+/A1
P1.2/ACLK/A2
P1.3/ADC10CLK/A3
P1DS.x
P1SEL0.x
P1SEL1.x
P1IN.x
EN
To Timer_A
D
Bus
Keeper
P1IE.x
P1IRQ.x
EN
P1IFG.x
SET
P1SEL.x
Interrupt
Edge
Select
P1IES.x
92
Q
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 70. Port P1 (P1.0 Through P1.3) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/TA1.1/VeREF-/A0
0
1
2
(1)
3
P1SEL0.x
0
0
0
0
1
TA1.1
1
0
1
N/A
0
1
0
DVSS
1
1
0
VeREF-/A0
X
1
1
I:0; O:1
0
0
TA2.CCI1A
0
0
1
TA2.1
1
0
1
N/A
0
1
0
DVSS
1
1
0
VeREF+/A1
X
1
1
I:0; O:1
0
0
ACLK
1
0
1
N/A
0
1
0
DVSS
1
1
0
A2
X
1
1
P1.3 (I/O)
P1.3/ADC10CLK/A3
P1SEL1.x
I:0; O:1
P1.2 (I/O)
P1.2/ACLK/A2
P1DIR.x
TA1.CCI1A
P1.1 (I/O)
P1.1/TA2.1/VeREF+/A1
CONTROL BITS OR SIGNALS (1)
I:0; O:1
0
0
ADC10CLK
1
0
1
N/A
0
1
0
DVSS
1
1
0
A3
X
1
1
X = don't care
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MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Port P1, P1.0 Through P1.3 Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
A0..A3
From ADC
P1REN.x
P1DIR.x
DVSS
0
DVCC
1
00
01
10
11
P1OUT.x
00
From Comparator_B
From Timer_A,
ACLK, ADC10CLK
DVSS
01
10
11
(MSP430F677xIPZ only)
P1.0/TA1.1/VeREF-/A0
P1.1/TA2.1/CBOUT/VeREF+/A1
P1.2/ACLK/A2
P1.3/ADC10CLK/A3
P1DS.x
P1SEL0.x
P1SEL1.x
P1IN.x
EN
To Timer_A
D
Bus
Keeper
P1IE.x
P1IRQ.x
EN
SET
P1SEL.x
Interrupt
Edge
Select
P1IES.x
94
Q
P1IFG.x
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 71. Port P1 (P1.0, P1.1, P1.2, and P1.3) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/TA1.1/VeREF-/A0
0
1
2
(1)
3
P1SEL0.x
0
0
0
0
1
TA1.1
1
0
1
N/A
0
1
0
DVSS
1
1
0
VeREF-/A0
X
1
1
I:0; O:1
0
0
TA2.CCI1A
0
0
1
TA2.1
1
0
1
N/A
0
1
0
CBOUT
1
1
0
VeREF+/A1
X
1
1
I:0; O:1
0
0
ACLK
1
0
1
N/A
0
1
0
DVSS
1
1
0
A2
X
1
1
P1.3 (I/O)
P1.3/ADC10CLK/A3
P1SEL1.x
I:0; O:1
P1.2 (I/O)
P1.2/ACLK/A2
P1DIR.x
TA1.CCI1A
P1.1 (I/O)
P1.1/TA2.1/CBOUT/VeREF+/A1
CONTROL BITS OR SIGNALS (1)
I:0; O:1
0
0
ADC10CLK
1
0
1
N/A
0
1
0
DVSS
1
1
0
A3
X
1
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Port P1, P1.4 and P1.5 Input/Output With Schmitt Trigger (MSP430F677xIPEU and
MSP430F677xIPZ)
to Comparator_B
from Comparator_B
CBPD.z
A0..A3
From ADC
P1REN.x
P1DIR.x
DVSS
0
DVCC
1
00
01
10
11
P1OUT.x
00
01
From MCLK, SMCLK
10
DVSS
11
P1.4/MCLK/CB1/A4
P1.5/SMCLK/CB0/A5
P1DS.x
P1SEL0.x
P1SEL1.x
P1IN.x
EN
Not Used
D
Bus
Keeper
P1IE.x
P1IRQ.x
EN
SET
P1SEL.x
Interrupt
Edge
Select
P1IES.x
96
Q
P1IFG.x
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 72. Port P1 (P1.4 and P1.5) Pin Functions (MSP430F677xIPEU and MSP430F677xIPZ)
PIN NAME (P1.x)
x
FUNCTION
P1.4 (I/O)
P1.4/MCLK/CB1/A4
4
(1)
5
P1DIR.x
P1SEL1.x
P1SEL0.x
CPBD.z
I:0; O:1
0
0
0
MCLK
1
0
1
0
N/A
0
1
0
0
DVSS
1
1
0
0
A4
X
1
1
0
CB1
X
X
X
1 (z = 1)
I:0; O:1
0
0
0
SMCLK
1
0
1
0
N/A
0
1
0
0
DVSS
1
1
0
0
A5
X
1
1
0
CB0
X
X
X
1 (z = 0)
P1.5 (I/O)
P1.5/SMCLK/CB0/A5
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F677x
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MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Port P1, P1.6 and P1.7 Input/Output With Schmitt Trigger (MSP430F677xIPEU and
MSP430F677xIPZ)
COM2 to COM3
From LCD_C
P1REN.x
P1DIR.x
DVSS
0
DVCC
1
00
01
10
11
P1OUT.x
00
01
DVSS
10
11
P1.6/COM2
P1.7/COM3
P1DS.x
P1SEL0.x
P1SEL1.x
P1IN.x
EN
Not Used
D
Bus
Keeper
P1IE.x
P1IRQ.x
Q
EN
P1IFG.x
SET
P1SEL.x
Interrupt
Edge
Select
P1IES.x
Table 73. Port P1 (P1.6 and P1.7) Pin Functions (MSP430F677xIPEU and MSP430F677xIPZ)
PIN NAME (P1.x)
x
FUNCTION
P1.6 (I/O)
P1.6/COM2
6
(1)
98
7
P1DIR.x
P1SEL1.x
P1SEL0.x
COM Enable
I:0; O:1
X
0
0
N/A
0
X
1
0
DVSS
1
X
1
0
COM2
X
X
X
1
P1.7 (I/O)
P1.7/COM3
CONTROL BITS OR SIGNALS (1)
I:0; O:1
X
0
0
N/A
0
X
1
0
DVSS
1
X
1
0
COM3
X
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P2, P2.0 Through P2.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPEU only)
P2.0/PM_TA0.0
P2.1/PM_TA0.1
P2.2/PM_TA0.2
P2.3/PM_TA1.0
P2.4/PM_TA2.0
P2.5/PM_UCB0SOMI/PM_UCB0SCL
P2.6/PM_UCB0SIMO/PM_UCB0SDA
P2.7/PM_UCB0CLK
P2DS.x
P2SEL0.x
P2IN.x
EN
to Port Mapping
D
Bus
Keeper
P2IE.x
P2IRQ.x
Q
EN
P2IFG.x
SET
P2SEL.x
Interrupt
Edge
Select
P2IES.x
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MSP430F677x
MSP430F676x
MSP430F674x
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www.ti.com
Table 74. Port P2 (P2.0 Through P2.7) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
P2.0/PM_TA0.0
0
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
1
2
3
4
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
X
1
≤ 30
= 31
Mapped Secondary digital function
Mapped Secondary digital function
P2.6 (I/O)
6
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
(1)
100
7
X
1
I:0; O:1
0
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
P2.7 (I/O)
P2.7/PM_UCB0CLK
≤ 30
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
P2.6/PM_UCB0SIMO/
PM_UCB0SDA
X
1
X
P2.5 (I/O)
5
0
X
= 31
Output driver and input Schmitt trigger disabled
P2.5/PM_UCB0SOMI/
PM_UCB0SCL
I:0; O:1
0
P2.4 (I/O)
P2.4/PM_TA2.0
P2MAP.x
1
P2.3 (I/O)
P2.3/PM_TA1.0
P2SEL0.x
X
P2.2 (I/O)
P2.2/PM_TA0.2
P2DIR.x
I:0; O:1
P2.1 (I/O)
P2.1/PM_TA0.1
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P2, P2.0 Through P2.3, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
COM4 to COM7
from LCD_C
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPZ only)
P2.0/PM_TA0.0/COM4
P2.1/PM_TA0.1/COM5
P2.2/PM_TA0.2/COM6
P2.3/PM_TA1.0/COM7
P2DS.x
P2SEL0.x
P2IN.x
EN
to Port Mapping
D
Bus
Keeper
P2IE.x
P2IRQ.x
Q
EN
P2IFG.x
SET
P2SEL.x
Interrupt
Edge
Select
P2IES.x
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Table 75. Port P2 (P2.0 Through P2.3) Pin Functions (MSP430F677xIPZ Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
P2.0/PM_TA0.0/
COM4
0
2
0
X
0
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
COM5
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
COM6
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
COM7
X
X
X
1
P2.3 (I/O)
P2.3/PM_TA1.0/
COM7
(1)
102
3
COM
Enable
X
P2.2 (I/O)
P2.2/PM_TA0.2/
COM6
P2MAP.x
I:0; O:1
P2.1 (I/O)
1
P2SEL0.x
Mapped secondary digital function
COM4
P2.1/PM_TA0.1/
COM5
P2DIR.x
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P2, P2.4 Through P2.6, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPZ only)
P2.4/PM_TA2.0
P2.5/PM_UCB0SOMI/PM_UCB0SCL
P2.6/PM_UCB0SIMO/PM_UCB0SDA
P2DS.x
P2SEL0.x
P2IN.x
EN
to Port Mapping
D
Bus
Keeper
P2IE.x
P2IRQ.x
Q
EN
P2IFG.x
SET
P2SEL.x
Interrupt
Edge
Select
P2IES.x
Table 76. Port P2 (P2.4 and P2.6) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P2.x)
x
FUNCTION
P2.4 (I/O)
P2.4/PM_TA2.0/R23
4
Mapped secondary digital function
R23
P2.5 (I/O)
P2.5/PM_UCB0SOMI/
PM_UCB0SCL/R13
5
Mapped secondary digital function
R13
(1)
6
P2DIR.x
P2SEL0.x
I:0; O:1
0
P2MAP.x
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
Mapped secondary digital function
X
1
≤ 30
R03
X
1
= 31
P2.6 (I/O)
P2.6/PM_UCB0SIMO/
PM_UCB0SDA/R03
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F676x
MSP430F674x
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www.ti.com
Port P2, P2.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
Comparator_B
CBPD.z
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPZ only)
P2.7/PM_UCB0CLK/CB2
P2DS.x
P2SEL0.x
P2IN.x
EN
to Port Mapping
D
Bus
Keeper
P2IE.x
P2IRQ.x
Q
EN
P2IFG.x
SET
P2SEL.x
Interrupt
Edge
Select
P2IES.x
Table 77. Port P2 (P2.7) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL0.x
P2MAP.x
CBPD.z
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
CB2
X
X
X
1 (z = 2)
P2.7 (I/O)
P2.7/PM_UCB0CLK/
CB2
(1)
104
7
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P3, P3.0 Through P3.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPEU only)
P3.0/PM_UCA0RXD/PM_UCA0SOMI
P3.1/PM_UCA0TXD/PM_UCA0SIMO
P3.2/PM_UCA0CLK
P3.3/PM_UCA1CLK
P3.4/PM_UCA1RXD/PM_UCA1SOMI
P3.5/PM_UCA1TXD/PM_UCA1SIMO
P3.6/PM_UCA2RXD/PM_UCA2SOMI
P3.7/PM_UCA2TXD/PM_UCA2SIMO
P3DS.x
P3SEL0.x
P3IN.x
EN
to Port Mapping
D
Bus
Keeper
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Table 78. Ports P3 (P3.0 Through P3.7) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P3.x)
x
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
0
FUNCTION
P3.0 (I/O)
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
1
2
3
4
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
X
1
≤ 30
= 31
Mapped Secondary digital function
Mapped Secondary digital function
P3.6 (I/O)
6
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
(1)
106
7
X
1
I:0; O:1
0
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
P3.7 (I/O)
P3.7/PM_UCA2TXD/
PM_UCA2SIMO
≤ 30
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
P3.6/PM_UCA2RXD/
PM_UCA2SOMI
X
1
X
P3.5 (I/O)
5
0
X
= 31
Output driver and input Schmitt trigger disabled
P3.5/PM_UCA1TXD/
PM_UCA1SIMO
I:0; O:1
0
P3.4 (I/O)
P3.4/PM_UCA1RXD/
PM_UCA1SOMI
P3MAP.x
1
P3.3 (I/O)
P3.3/PM_UCA1CLK
P3SEL0.x
X
P3.2 (I/O)
P3.2/PM_UCA0CLK
P3DIR.x
I:0; O:1
P3.1 (I/O)
P3.1/PM_UCA0TXD/
PM_UCA0SIMO
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P3, P3.0, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPZ only)
P3.0/PM_UCA0RXD/PM_UCA0SOMI
P3DS.x
P3SEL0.x
P3IN.x
EN
to Port Mapping
D
Bus
Keeper
Table 79. Ports P3 (P3.0) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL0.x
P3MAP.x
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
P3.0 (I/O)
P3.0/PM_UCA0RXD/
PM_UCA0SOMI
(1)
0
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F676x
MSP430F674x
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Port P3, P3.1 Through P3.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
S39..S33
LCDS39..LCDS33
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPZ only)
P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39
P3.2/PM_UCA0CLK/S38
P3.3/PM_UCA1CLK/S37
P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36
P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35
P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34
P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33
P3DS.x
P3SEL0.x
P3IN.x
EN
to Port Mapping
D
Bus
Keeper
108
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 80. Ports P3 (P3.1 Through P3.7) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P3.x)
x
FUNCTION
P3.1 (I/O)
P3.1/PM_UCA0TXD/
PM_UCA0SIMO/S39
1
2
4
X
0
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S39
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S37
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S36
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S35
X
X
X
1
P3.5 (I/O)
P3.5/PM_UCA1TXD/
PM_UCA1SIMO/S35
5
P3.6 (I/O)
P3.6/PM_UCA2RXD
/
PM_UCA2SOMI/S34
6
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S34
X
X
X
1
P3.7 (I/O)
P3.7/PM_UCA2TXD/
PM_UCA2SIMO/S33
(1)
7
LCD39..33
0
P3.4 (I/O)
P3.4/PM_UCA1RXD
/
PM_UCA1SOMI/S36
P3MAP.x
X
P3.3 (I/O)
3
P3SEL0.x
I:0; O:1
S38
P3.3/PM_UCA1CLK/
S37
P3DIR.x
Mapped secondary digital function
P3.2 (I/O)
P3.2/PM_UCA0CLK/
S38
CONTROL BITS OR SIGNALS (1)
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S33
X
X
X
1
X = don't care
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MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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www.ti.com
Port P4, P4.0 Through P4.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
P4REN.x
P4MAP.x = PMAP_ANALOG
P4DIR.x
0
from Port Mapping
1
P4OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPEU only)
P4.0/PM_UCA2CLK
P4.1/PM_UCA3RXD/PM_UCA3SOMI
P4.2/PM_UCA3TXD/PM_UCA3SIMO
P4.3/PM_UCA3CLK
P4.4/PM_UCB1SOMI/PM_UCB1SCL
P4.5/PM_UCB1SIMO/PM_UCB1SDA
P4.6/PM_UCB1CLK
P4.7/PM_TA3.0
P4DS.x
P4SEL0.x
P4IN.x
EN
to Port Mapping
D
Bus
Keeper
110
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 81. Port P4 (P4.0 Through P4.7) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/PM_UCA2CLK
0
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
1
2
3
4
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
I:0; O:1
0
X
X
1
≤ 30
= 31
Mapped Secondary digital function
Mapped Secondary digital function
P4.6 (I/O)
6
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
(1)
7
X
1
I:0; O:1
0
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
X
1
≤ 30
= 31
X
1
I:0; O:1
0
X
Mapped Secondary digital function
X
1
≤ 30
Output driver and input Schmitt trigger disabled
X
1
= 31
P4.7 (I/O)
P4.7/PM_TA3.0
≤ 30
Mapped Secondary digital function
Output driver and input Schmitt trigger disabled
P4.6/PM_UCB1CLK
X
1
X
P4.5 (I/O)
5
0
X
= 31
Output driver and input Schmitt trigger disabled
P4.5/PM_UCB1SIMO/
PM_UCB1SDA
I:0; O:1
0
P4.4 (I/O)
P4.4/PM_UCB1SOMI/
PM_UCB1SCL
P4MAP.x
1
P4.3 (I/O)
P4.3/PM_UCA3CLK
P4SEL0.x
X
P4.2 (I/O)
P4.2/PM_UCA3TXD/
PM_UCA3SIMO
P4DIR.x
I:0; O:1
P4.1 (I/O)
P4.1/PM_UCA3RXD/
PM_UCA3SOMI
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Port P4, P4.0 Through P4.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
S32..S25
LCDS32..LCDS25
P4REN.x
P4MAP.x = PMAP_ANALOG
P4DIR.x
0
from Port Mapping
1
P4OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
(MSP430F677xIPZ only)
P4.0/PM_UCA2CLK/S32
P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31
P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30
P4.3/PM_UCA3CLK/S29
P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28
P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27
P4.6/PM_UCB1CLK/S26
P4.7/PM_TA3.0/S25
P4DS.x
P4SEL0.x
P4IN.x
EN
to Port Mapping
D
Bus
Keeper
112
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 82. Port P4 (P4.0 Through P4.7) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/PM_UCA2CLK/
S32
0
1
3
X
0
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S32
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S30
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S29
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S28
X
X
X
1
P4.4 (I/O)
P4.4/
PM_UCB1SOMI/
PM_UCB1SCL/S28
4
P4.5 (I/O)
P4.5/
PM_UCB1SIMO/
PM_UCB1SDA/S27
5
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S27
X
X
X
1
P4.6 (I/O)
P4.6/PM_UCB1CLK/
S26
6
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S26
X
X
X
1
I:0; O:1
0
X
0
Mapped secondary digital function
X
1
≤ 30
0
Output driver and input Schmitt trigger disabled
X
1
= 31
0
S25
X
X
X
1
P4.7 (I/O)
P4.7/PM_TA3.0/S25
(1)
7
LCD32..25
0
P4.3 (I/O)
P4.3/PM_UCA3CLK/
S29
P4MAP.x
X
P4.2 (I/O)
2
P4SEL0.x
I:0; O:1
S31
P4.2/PM_UCA3TXD/
PM_UCA3SIMO/S30
P4DIR.x
Mapped secondary digital function
P4.1 (I/O)
P4.1/PM_UCA3RXD
/
PM_UCA3SOMI/S31
CONTROL BITS OR SIGNALS (1)
X = don't care
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MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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www.ti.com
Port P5, P5.0 Through P5.3, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
COM4 to COM7
From LCD_C
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
00
01
10
11
P5OUT.x
00
01
DVSS
10
11
(MSP430F677xIPEU only)
P5.0/COM4
P5.1/COM5
P5.2/COM6
P5.3/COM7
P5DS.x
P5SEL0.x
P5SEL1.x
P5IN.x
EN
Not Used
D
Bus
Keeper
114
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 83. Port P5 (P5.0 Through P5.3) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P5.x)
x
FUNCTION
P5.0 (I/O)
P5.0/COM4
0
1
(1)
3
COM Enable
X
0
0
X
1
0
DVSS
1
X
1
0
COM4
X
X
X
1
I:0; O:1
X
0
0
N/A
0
X
1
0
DVSS
1
X
1
0
X
X
X
1
I:0; O:1
X
0
0
0
X
1
0
DVSS
1
X
1
0
COM6
X
X
X
1
I:0; O:1
X
0
0
0
X
1
0
DVSS
1
X
1
0
COM7
X
X
X
1
N/A
P5.3 (I/O)
P5.3/COM7
P5SEL0.x
0
P5.2 (I/O)
2
P5SEL1.x
I:0; O:1
COM5
P5.2/COM6
P5DIR.x
N/A
P5.1 (I/O)
P5.1/COM5
CONTROL BITS OR SIGNALS (1)
N/A
X = don't care
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MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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www.ti.com
Port P5, P5.4 Through P5.6, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
R23, R13, R03, LCDREF
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
00
01
from SD24_B
10
11
P5OUT.x
00
01
from SD24_B
10
DVSS
11
(MSP430F677xIPEU only)
P5.4/SDCLK/R23
P5.5/SD0DIO/LCDREF/R13
P5.6/SD1DIO/R03
P5DS.x
P5SEL0.x
P5SEL1.x
P5IN.x
EN
to SD24_B
D
Bus
Keeper
116
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 84. Port P5 (P5.4 Through P5.6) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P5.x)
x
FUNCTION
P5.4 (I/O)
P5.4/SDCLK/R23
4
(1)
6
P5SEL0.x
0
0
X
0
1
N/A
0
1
0
DVSS
1
1
0
X
1
1
I:0; O:1
0
0
Secondary digital function
X
0
1
N/A
0
1
0
DVSS
1
1
0
LCDREF/R13
X
1
1
P5.6 (I/O)
PT.6/SD1DIO/R03
P5SEL1.x
I:0; O:1
P5.5 (I/O)
5
P5DIR.x
Secondary digital function
R23
P5.5/SD0DIO/LCDREF/R13
CONTROL BITS OR SIGNALS (1)
I:0; O:1
0
0
Secondary digital function
X
0
1
N/A
0
1
0
DVSS
1
1
0
R03
X
1
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Port P5, P5.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
to Comparator_B
CBPD.z
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
00
01
from SD24_B
10
11
P5OUT.x
00
01
10
from SD24_B
11
(MSP430F677xIPEU only)
P5.7/SD2DIO/CB2
P5DS.x
P5SEL0.x
P5SEL1.x
P5IN.x
EN
to SD24_B
D
Bus
Keeper
Table 85. Port P5 (P5.7) Pin Function (MSP430F677xIPEU Only)
PIN NAME (P5.x)
x
FUNCTION
P5.7 (I/O)
P5.7/SD2DIO/CB2
7 Secondary digital function
CB2
(1)
118
CONTROL BITS OR SIGNALS (1)
P5DIR.x
P5SEL1.x
P5SEL0.x
CBPD.z
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1 (z = 2)
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P5, P5.0 Through P5.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
S24..S17
LCDS24..LCDS17
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
00
01
from SD24_B
10
11
P5OUT.x
00
01
from SD24_B
10
11
(MSP430F677xIPZ only)
P5.0/SDCLK/S24
P5.1/SD0DIO/S23
P5.2/SD1DIO/S22
P5.3/SD2DIO/S21
P5.4/SD3DIO/S20
P5.5/SD4DIO/S19
P5.6/SD5DIO/S18
P5.7/SD6DIO/S17
P5DS.x
P5SEL0.x
P5SEL1.x
P5IN.x
EN
to SD24_B
D
Bus
Keeper
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Table 86. Port P5 (P5.0 Through P5.7) Pin Function (MSP430F677xIPZ Only)
PIN NAME (P5.x)
x
FUNCTION
P5.0 (I/O)
P5.0/SDCLK/S24
0 Secondary digital function
S24
P5.1 (I/O)
P5.1/SD0DIO/S23
1 Secondary digital function
S23
P5.2 (I/O)
P5.2/SD1DIO/S22
2 Secondary digital function
S22
P5.3 (I/O)
P5.3/SD2DIO/S21
3 Secondary digital function
S21
P5.4 (I/O)
P5.4/SD3DIO/S20
4 Secondary digital function
S20
P5.5 (I/O)
P5.5/SD4DIO/S19
5 Secondary digital function
S19
P5.6 (I/O)
P5.6/SD5DIO/S18
6 Secondary digital function
S18
P5.7 (I/O)
P5.7/SD6DIO/S17
7 Secondary digital function
S17
(1)
120
CONTROL BITS OR SIGNALS (1)
P5DIR.x
P5SEL1.x
P5SEL0.x
LCD24..17
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
I:0; O:1
X
0
0
X
X
1
0
X
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P6, P6.0, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
P6REN.x
P6DIR.x
0
from SD24_B
1
P6OUT.x
0
from SD24_B
1
DVSS
0
DVCC
1
(MSP430F677xIPEU only)
P6.0/SD3DIO
P6DS.x
P6SEL0.x
P6IN.x
EN
to SD24_B
D
Bus
Keeper
Table 87. Port P6 (P6.0) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P6.x)
P6.0/SD3DIO
(1)
x
0
FUNCTION
P6.0 (I/O)
Secondary digital function
CONTROL BITS OR SIGNALS (1)
P6DIR.x
P6SEL0.x
I:0; O:1
0
X
1
X = don't care
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MSP430F676x
MSP430F674x
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Port P6, P6.1 Through P6.3, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
S39...S37
LCDS39...LCDS37
P6REN.x
P6DIR.x
0
from SD24_B
1
P6OUT.x
0
from SD24_B
1
DVSS
0
DVCC
1
(MSP430F677xIPEU only)
P6.1/SD4DIO/S39
P6.2/SD5DIO/S38
P6.3/SD6DIO/S37
P6DS.x
P6SEL0.x
P6IN.x
EN
to SD24_B
D
Bus
Keeper
122
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 88. Port P6 (P6.1 Through P6.3) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P6.x)
x
FUNCTION
P6.1 (I/O)
P6.1/SD4DIO/S39
1
2
(1)
3
P6SEL0.x
LCD39..37
I:0; O:1
0
0
X
1
0
S39
X
X
1
I:0; O:1
0
0
Secondary digital function
X
1
0
S38
X
X
1
I:0; O:1
0
0
P6.3 (I/O)
P6.3/SD6DIO/S37
P6DIR.x
Secondary digital function
P6.2 (I/O)
P6.2/SD5DIO/S38
CONTROL BITS OR SIGNALS (1)
Secondary digital function
X
1
0
S37
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Port P6, P6.4 Through P6.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
S36...S0
LCDS36...LCDS0
P6REN.x
P6DIR.x
DVSS
0
DVCC
1
0
1
P6OUT.x
0
DVSS
1
(MSP430F677xIPEU only)
P6.4/S36
P6.5/S35
P6.6/S34
P6.7/S33
P6DS.x
P6SEL0.x
P6IN.x
EN
Not Used
D
Bus
Keeper
124
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 89. Port P6 (P6.4 Through P6.7) Pin Functions (MSP430F67xxIPEU Only)
PIN NAME (P6.x)
x
FUNCTION
P6.4 (I/O)
P6.4/S36
4
5
0
0
1
0
DVSS
1
1
0
S36
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
N/A
(1)
7
X
X
1
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S34
X
X
1
I:0; O:1
0
0
0
1
0
P6.7 (I/O)
P6.7/S33
LCD36..33
0
P6.6(I/O)
6
P6SEL0.x
I:0; O:1
S35
P6.6/S34
P6DIR.x
N/A
P6.5 (I/O)
P6.5/S35
CONTROL BITS OR SIGNALS (1)
N/A
DVSS
1
1
0
S33
X
X
1
X = don't care
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MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Port P6, P6.0 Through P6.7, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
S16...S9
LCDS16...LCDS9
P6REN.x
P6DIR.x
DVSS
0
DVCC
1
0
1
P6OUT.x
0
DVSS
1
(MSP430F677xIPZ only)
P6.0/S16
P6.1/S15
P6.2/S14
P6.3/S13
P6.4/S12
P6.5/S11
P6.6/S10
P6.7/S9
P6DS.x
P6SEL0.x
P6IN.x
EN
Not Used
D
Bus
Keeper
126
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 90. Port P6 (P6.0 Through P6.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P6.x)
x
FUNCTION
P6.0 (I/O)
P6.0/S16
0
1
0
0
1
0
DVSS
1
1
0
S16
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
N/A
3
4
5
6
(1)
0
1
0
1
I:0; O:1
0
0
0
1
0
N/A
DVSS
1
1
0
S13
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S12
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S11
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
P6.7 (I/O)
7
1
X
S10
P6.7/S9
0
0
1
P6.6 (I/O)
P6.6/S10
1
0
X
P6.5 (I/O)
P6.5/S11
X
S14
P6.4 (I/O)
P6.4/S12
X
I:0; O:1
DVSS
P6.3 (I/O)
P6.3/S13
LCD16..9
0
P6.2 (I/O)
2
P6SEL0.x
I:0; O:1
S15
P6.2/S14
P6DIR.x
N/A
P6.1 (I/O)
P6.1/S15
CONTROL BITS OR SIGNALS (1)
N/A
X
X
1
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S9
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Port P7, P7.0 Through P7.7, Input/Output With Schmitt Trigger (MSP430F67xxIPEU Only)
S32...S25
LCDS32...LCDS25
P7REN.x
P7DIR.x
DVSS
0
DVCC
1
0
1
P7OUT.x
0
DVSS
1
(MSP430F677xIPEU only)
P7.0/S32
P7.1/S31
P7.2/S30
P7.3/S29
P7.4/S28
P7.5/S27
P7.6/S26
P7.7/S25
P7DS.x
P7SEL0.x
P7IN.x
EN
Not Used
D
Bus
Keeper
128
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 91. Port P7 (P7.0 Through P7.7) Pin Functions (MSP430F67xxIPEU Only)
PIN NAME (P7.x)
x
FUNCTION
P7.0 (I/O)
P7.0/S32
0
1
0
0
1
0
DVSS
1
1
0
S32
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
N/A
3
4
5
6
(1)
0
1
0
1
I:0; O:1
0
0
0
1
0
N/A
DVSS
1
1
0
S29
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S28
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S27
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
P7.7 (I/O)
7
1
X
S26
P7.7/S25
0
0
1
P7.6 (I/O)
P7.6/S26
1
0
X
P7.5 (I/O)
P7.5/S27
X
S30
P7.4 (I/O)
P7.4/S28
X
I:0; O:1
DVSS
P7.3 (I/O)
P7.3/S29
LCD32..25
0
P7.2 (I/O)
2
P7SEL0.x
I:0; O:1
S31
P7.2/S30
P7DIR.x
N/A
P7.1 (I/O)
P7.1/S31
CONTROL BITS OR SIGNALS (1)
N/A
X
X
1
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S25
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Port P7, P7.0 Through P7.7, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
S8...S1
LCDS8...LCDS1
P7REN.x
P7DIR.x
DVSS
0
DVCC
1
0
1
P7OUT.x
0
DVSS
1
(MSP430F677xIPZ only)
P7.0/S8
P7.1/S7
P7.2/S6
P7.3/S5
P7.4/S4
P7.5/S3
P7.6/S2
P7.7/S1
P7DS.x
P7SEL0.x
P7IN.x
EN
Not Used
D
Bus
Keeper
130
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 92. Port P7 (P7.0 Through P7.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P7.x)
x
FUNCTION
P7.0 (I/O)
P7.0/S8
0
1
0
0
1
0
DVSS
1
1
0
S8
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
N/A
3
4
5
6
(1)
0
1
0
1
I:0; O:1
0
0
0
1
0
N/A
DVSS
1
1
0
S5
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S4
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S3
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
P7.7 (I/O)
7
1
X
S2
P7.7/S1
0
0
1
P7.6 (I/O)
P7.6/S2
1
0
X
P7.5 (I/O)
P7.5/S3
X
S6
P7.4 (I/O)
P7.4/S4
X
I:0; O:1
DVSS
P7.3 (I/O)
P7.3/S5
LCD8..1
0
P7.2 (I/O)
2
P7SEL0.x
I:0; O:1
S7
P7.2/S6
P7DIR.x
N/A
P7.1 (I/O)
P7.1/S7
CONTROL BITS OR SIGNALS (1)
N/A
X
X
1
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S1
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Port P8, P8.0 Through P8.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
S24...S17
LCDS24...LCDS17
P8REN.x
P8DIR.x
DVSS
0
DVCC
1
0
1
P8OUT.x
0
DVSS
1
(MSP430F677xIPEU only)
P8.0/S24
P8.1/S23
P8.2/S22
P8.3/S21
P8.4/S20
P8.5/S19
P8.6/S18
P8.7/S17
P8DS.x
P8SEL0.x
P8IN.x
EN
Not Used
D
Bus
Keeper
132
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 93. Port P8 (P8.0 Through P8.7) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P8.x)
x
FUNCTION
P8.0 (I/O)
P8.0/S24
0
1
0
0
1
0
DVSS
1
1
0
S24
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
N/A
3
4
5
6
(1)
0
1
0
1
I:0; O:1
0
0
0
1
0
N/A
DVSS
1
1
0
S21
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S20
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S19
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
P8.7 (I/O)
7
1
X
S18
P8.7/S17
0
0
1
P8.6 (I/O)
P8.6/S18
1
0
X
P8.5 (I/O)
P8.5/S19
X
S22
P8.4 (I/O)
P8.4/S20
X
I:0; O:1
DVSS
P8.3 (I/O)
P8.3/S21
LCD24..17
0
P8.2 (I/O)
2
P8SEL0.x
I:0; O:1
S23
P8.2/S22
P8DIR.x
N/A
P8.1 (I/O)
P8.1/S23
CONTROL BITS OR SIGNALS (1)
N/A
X
X
1
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S17
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Port P8, P8.0, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
S0
LCDS0
P8REN.x
P8DIR.x
DVSS
0
DVCC
1
0
1
P8OUT.x
0
DVSS
1
(MSP430F677xIPZ only)
P8.0/S0
P8DS.x
P8SEL0.x
P8IN.x
EN
Not Used
D
Bus
Keeper
Table 94. Port P8 (P8.0) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P8.x)
x
FUNCTION
P8.0 (I/O)
P8.0/S0
(1)
134
0
N/A
CONTROL BITS OR SIGNALS (1)
P8DIR.x
P8SEL0.x
LCD0
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S0
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P8, P8.1, Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
to Comparator_B
CBPD.z
P8REN.x
DVSS
0
DVCC
1
0
P8DIR.x
1
P8OUT.x
0
RTCCLK
1
(MSP430F677xIPZ only)
P8.1/TACLK/RTCCLK/CB3
P8DS.x
P8SEL0.x
P8IN.x
EN
to TACLK
D
Bus
Keeper
Table 95. Port P8 (P8.1) Pin Functions (MSP430F677xIPZ Only)
PIN NAME (P8.x)
x
FUNCTION
P8.1 (I/O)
P8.1/TACLK/RTCCLK/
CB3
(1)
1
TACLK
CONTROL BITS OR SIGNALS (1)
P8DIR.x
P8SEL0.x
CBPD.z
I:0; O:1
0
0
0
1
0
RTCCLK
1
1
0
CB3
X
X
1 (z = 3)
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Port P9, P9.0 Through P9.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
S16...S9
LCDS16...LCDS9
P9REN.x
P9DIR.x
DVSS
0
DVCC
1
0
1
P9OUT.x
0
DVSS
1
(MSP430F677xIPEU only)
P9.0/S16
P9.1/S15
P9.2/S14
P9.3/S13
P9.4/S12
P9.5/S11
P9.6/S10
P9.7/S9
P9DS.x
P9SEL0.x
P9IN.x
EN
Not Used
D
Bus
Keeper
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 96. Port P9 (P9.0 to P9.7) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P9.x)
x
FUNCTION
P9.0 (I/O)
P9.0/S16
0
1
0
0
1
0
DVSS
1
1
0
S16
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
N/A
3
4
5
6
(1)
0
1
0
1
I:0; O:1
0
0
0
1
0
N/A
DVSS
1
1
0
S13
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S12
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S11
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
P9.7 (I/O)
7
1
X
S10
P9.7/S9
0
0
1
P9.6 (I/O)
P9.6/S10
1
0
X
P9.5 (I/O)
P9.5/S11
X
S14
P9.4 (I/O)
P9.4/S12
X
I:0; O:1
DVSS
P9.3 (I/O)
P9.3/S13
LCD16..9
0
P9.2 (I/O)
2
P9SEL0.x
I:0; O:1
S15
P9.2/S14
P9DIR.x
N/A
P9.1 (I/O)
P9.1/S15
CONTROL BITS OR SIGNALS (1)
N/A
X
X
1
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S9
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
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Port P10, P10.0 Through P10.7, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
S8...S1
LCDS8...LCDS1
P10REN.x
P10DIR.x
DVSS
0
DVCC
1
0
1
P10OUT.x
0
DVSS
1
(MSP430F677xIPEU only)
P10.0/S8
P10.1/S7
P10.2/S6
P10.3/S5
P10.4/S4
P10.5/S3
P10.6/S2
P10.7/S1
P10DS.x
P10SEL0.x
P10IN.x
EN
Not Used
D
Bus
Keeper
138
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 97. Port P10 (P10.0 Through P10.7) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P10.x)
x
FUNCTION
P10.0 (I/O)
P10.0/S8
0
1
0
0
1
0
DVSS
1
1
0
S8
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
N/A
3
4
5
6
(1)
0
1
0
1
I:0; O:1
0
0
0
1
0
N/A
DVSS
1
1
0
S5
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S4
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
S3
X
X
1
I:0; O:1
0
0
N/A
0
1
0
DVSS
1
1
0
P10.7 (I/O)
7
1
X
S2
P10.7/S1
0
0
1
P10.6 (I/O)
P10.6/S2
1
0
X
P10.5 (I/O)
P10.5/S3
X
S6
P10.4 (I/O)
P10.4/S4
X
I:0; O:1
DVSS
P10.3 (I/O)
P10.3/S5
LCD8..1
0
P10.2 (I/O)
2
P10SEL0.x
I:0; O:1
S7
P10.2/S6
P10DIR.x
N/A
P10.1 (I/O)
P10.1/S7
CONTROL BITS OR SIGNALS (1)
N/A
X
X
1
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S1
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Port P11, P11.0, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
S0
LCDS0
P11REN.x
P11DIR.x
DVSS
0
DVCC
1
0
1
P11OUT.x
0
DVSS
1
(MSP430F677xIPEU only)
P11.0/S0
P11DS.x
P11SEL0.x
P11IN.x
EN
Not Used
D
Bus
Keeper
Table 98. Port P11 (P11.0) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P11.x)
x
FUNCTION
P11.0 (I/O)
P11.0/S0
(1)
140
0
N/A
CONTROL BITS OR SIGNALS (1)
P11DIR.x
P11SEL0.x
LCD0
I:0; O:1
0
0
0
1
0
DVSS
1
1
0
S0
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P11, P11.1, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
to Comparator_B
CBPD.z
P11REN.x
DVSS
0
DVCC
1
0
P11DIR.x
1
P11OUT.x
0
from Timer_A
1
(MSP430F677xIPEU only)
P11.1/TA3.1/CB3
P11DS.x
P11SEL0.x
P11IN.x
EN
to Timer_A
D
Bus
Keeper
Table 99. Port P11 (P11.1) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P11.x)
P11.1/TA3.1/CB3
(1)
x
1
FUNCTION
CONTROL BITS OR SIGNALS (1)
P11DIR.x
P11SEL0.x
CBPD.z
P11.1 (I/O)
I:0; O:1
0
0
TA3.CCI1A
0
1
0
TA3.1
1
1
0
CB3
X
X
1
X = don't care
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
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Port P11, P11.2 and P11.3, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
P11REN.x
DVSS
0
DVCC
1
0
P11DIR.x
1
0
P11OUT.x
1
from Timer_A
(MSP430F677xIPEU only)
P11.2/TA1.1
P11.3/TA2.1
P11DS.x
P11SEL0.x
P11IN.x
EN
to Timer_A
D
Bus
Keeper
Table 100. Port P11 (P11.2 and P11.3) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P11.x)
P11.2/TA1.1
x
2
FUNCTION
P11DIR.x
P11SEL0.x
P11.2 (I/O)
I:0; O:1
0
TA1.CCI1A
0
1
TA1.1
P11.3/TA2.1
142
3
CONTROL BITS OR SIGNALS
1
1
P11.3 (I/O)
I:0; O:1
0
TA2.CCI1A
0
1
TA2.1
1
1
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Port P11, P11.4 and P11.5, Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
P11REN.x
DVSS
0
DVCC
1
0
P11DIR.x
1
P11OUT.x
0
from Comparator_B
RTCCLK
1
(MSP430F677xIPEU only)
P11.4/CBOUT
P11.5/TACLK/RTCCLK
P11DS.x
P11SEL0.x
P11IN.x
EN
to TACLK
D
Bus
Keeper
Table 101. Port P11 (P11.4 and P11.5) Pin Functions (MSP430F677xIPEU Only)
PIN NAME (P11.x)
x
FUNCTION
P11.4 (I/O)
P11.4/CBOUT
4
N/A
CBOUT
5
P11DIR.x
P11SEL0.x
I:0; O:1
0
0
1
1
1
I:0; O:1
0
TACLK
0
1
RTCCLK
1
1
P11.5 (I/O)
P11.5/TACLK/RTCCLK
CONTROL BITS OR SIGNALS
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
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Port J, J.0, JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
0
DVCC
1
PJOUT.x
00
From JTAG
01
SMCLK
10
DVSS
0
DVCC
1
1
PJ.0/SMCLK/TDO
PJDS.0
0: Low drive
1: High drive
11
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
Port J, J.1 to J.3, JTAG Pins TMS, TCK, TDI/TCLK,
Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
DVSS
DVSS
0
DVCC
1
1
0
1
PJOUT.x
00
From JTAG
01
MCLK/ADC10CLK/ACLK
10
PJDS.x
0: Low drive
1: High drive
11
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
PJSEL.x
From JTAG
PJIN.x
EN
To JTAG
144
Bus
Holder
D
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 102. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (PJ.x)
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
x
0
1
FUNCTION
PJ.0 (I/O) (2)
PJ.3/ACLK/TCK
3
0
0
1
1
0
TDO (3)
x
x
1
I: 0; O: 1
0
0
1
1
0
x
x
1
PJ.1 (I/O)
(2)
PJ.2 (I/O)
(2)
(4)
I: 0; O: 1
0
0
ADC10CLK
1
1
0
TMS (3)
x
x
1
I: 0; O: 1
0
0
1
1
0
x
x
1
(4)
PJ.3 (I/O) (2)
ACLK
TCK (3)
(1)
(2)
(3)
(4)
JTAG
MODE
I: 0; O: 1
TDI/TCLK (3)
2
PJSEL.x
SMCLK
MCLK
PJ.2/ADC10CLK/TMS
PJDIR.x
(4)
X = don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
www.ti.com
Device Descriptors (TLV)
list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.
Table 103. F677x Device Descriptor Table
Info Block
Die Record
ADC10
Calibration
146
F6779IPEU
F6779IPZ
F6778IPEU
F6778IPZ
F6777IPEU
F6777IPZ
F6776IPEU
F6776IPZ
F6775IPEU
F6775IPZ
Value
Value
Value
Value
Value
06h
06h
06h
06h
06h
1
06h
06h
06h
06h
06h
1A02h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Device ID
1A04h
2
8196h
8195h
8194h
8193h
8192h
Hardware
Revision
1A06h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Firmware
Revision
1A07h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Die Record Tag
1A08h
1
08h
08h
08h
08h
08h
Die Record
Length
1A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
Lot ID
1A0Ah
4
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
X Position
1A0Eh
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Y Position
1A10h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Test Record
CP
1A12h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Test Record FT
1A13h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC
Calibration Tag
1A14h
1
13h
13h
13h
13h
13h
ADC
Calibration
Length
1A15h
1
10h
10h
10h
10h
10h
ADC Gain
Factor
1A16h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Description
Address
Size in bytes
Info Length
1A00h
1
CRC Length
1A01h
CRC Value
ADC Offset
1A18h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 15T30
1A1Ah
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 15T85
1A1Ch
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 20T30
1A1Eh
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 20T85
1A20h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 25T30
1A22h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 25T85
1A24h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Table 104. F676x Device Descriptor Table
Info Block
Die Record
ADC10
Calibration
F6769IPEU
F6769IPZ
F6768IPEU
F6768IPZ
F6767IPEU
F6767IPZ
F6766IPEU
F6766IPZ
F6765IPEU
F6765IPZ
Value
Value
Value
Value
Value
06h
06h
06h
06h
06h
1
06h
06h
06h
06h
06h
1A02h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Device ID
1A04h
2
8191h
8190h
818Fh
818Eh
818Dh
Hardware
Revision
1A06h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Firmware
Revision
1A07h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Die Record Tag
1A08h
1
08h
08h
08h
08h
08h
Die Record
Length
1A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
Lot ID
1A0Ah
4
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
X Position
1A0Eh
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Y Position
1A10h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Test Record
CP
1A12h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Test Record FT
1A13h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC
Calibration Tag
1A14h
1
13h
13h
13h
13h
13h
ADC
Calibration
Length
1A15h
1
10h
10h
10h
10h
10h
ADC Gain
Factor
1A16h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Description
Address
Size in bytes
Info Length
1A00h
1
CRC Length
1A01h
CRC Value
ADC Offset
1A18h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 15T30
1A1Ah
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 15T85
1A1Ch
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 20T30
1A1Eh
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 20T85
1A20h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 25T30
1A22h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 25T85
1A24h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Table 105. F674x Device Descriptor Table
Info Block
Die Record
F6749IPEU
F6749IPZ
F6748IPEU
F6748IPZ
F6747IPEU
F6747IPZ
F6746IPEU
F6746IPZ
F6745IPEU
F6745IPZ
Value
Value
Value
Value
Value
06h
06h
06h
06h
06h
1
06h
06h
06h
06h
06h
1A02h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Device ID
1A04h
2
818Ch
818Bh
818Ah
8189h
8188h
Hardware
Revision
1A06h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Firmware
Revision
1A07h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Die Record Tag
1A08h
1
08h
08h
08h
08h
08h
Die Record
Length
1A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
Description
Address
Size in bytes
Info Length
1A00h
1
CRC Length
1A01h
CRC Value
Lot ID
1A0Ah
4
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
X Position
1A0Eh
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Y Position
1A10h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Test Record
CP
1A12h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
Test Record FT
1A13h
1
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
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MSP430F677x
MSP430F676x
MSP430F674x
ECCN 5E002 TSPA - Technology / Software Publicly Available
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Table 105. F674x Device Descriptor Table (continued)
ADC10
Calibration
148
ADC
Calibration Tag
1A14h
1
13h
13h
13h
13h
13h
ADC
Calibration
Length
1A15h
1
10h
10h
10h
10h
10h
ADC Gain
Factor
1A16h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC Offset
1A18h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 15T30
1A1Ah
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 15T85
1A1Ch
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 20T30
1A1Eh
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 20T85
1A20h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 25T30
1A22h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
ADC 25T85
1A24h
2
Per Unit
Per Unit
Per Unit
Per Unit
Per Unit
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MSP430F677x
MSP430F676x
MSP430F674x
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
REVISION HISTORY
REVISION
DESCRIPTION
SLAS768
Product Preview release
SLAS768A
Production Data release
SLAS768B
Made editorial changes to Features.
Recommended Operating Conditions, Added TYP test conditions.
Active Mode Supply Current Into VCC Excluding External Current, Updated current values.
Auxiliary Supplies - AUX3 (Backup Subsystem) Currents, Changed IAUX3,RTCoff at 85°C.
DCO Frequency, Added note (1).
Flash Memory, Updated Flash program and erase currents.
SLAS768C
Table 6, Corrected pin number for P2.6/PM_UCB0SIMO/PM_UCB0SDA/R03.
10-Bit ADC External Reference, Note (1), changed "12-bit accuracy" to "10-bit accuracy".
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PACKAGE OPTION ADDENDUM
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3-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430F6745IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6745
MSP430F6745IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6745
MSP430F6745IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6745
MSP430F6745IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6745
MSP430F6746IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6746
MSP430F6746IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6746
MSP430F6746IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6746
MSP430F6746IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6746
MSP430F6747IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6747
MSP430F6747IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6747
MSP430F6747IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6747
MSP430F6747IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6747
MSP430F6748IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6748
MSP430F6748IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6748
MSP430F6748IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6748
MSP430F6749IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6749
MSP430F6749IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6749
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
3-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430F6765IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6765
MSP430F6765IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6765
MSP430F6765IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6765
MSP430F6765IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6765
MSP430F6766IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6766
MSP430F6766IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6766
MSP430F6766IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6766
MSP430F6766IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6766
MSP430F6767IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6767
MSP430F6767IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6767
MSP430F6767IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6767
MSP430F6767IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6767
MSP430F6768IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6768
MSP430F6768IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6768
MSP430F6768IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6768
MSP430F6768IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6768
MSP430F6769IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6769
MSP430F6769IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6769
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
3-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430F6769IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6769
MSP430F6769IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6769
MSP430F6775IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6775
MSP430F6775IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6775
MSP430F6775IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6775
MSP430F6775IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6775
MSP430F6776IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6776
MSP430F6776IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6776
MSP430F6776IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6776
MSP430F6776IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6776
MSP430F6777IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6777
MSP430F6777IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6777
MSP430F6777IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6777
MSP430F6777IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6777
MSP430F6778IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6778
MSP430F6778IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6778
MSP430F6778IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6778
MSP430F6778IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6778
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
3-Oct-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
MSP430F6779IPEU
ACTIVE
LQFP
PEU
128
72
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6779
MSP430F6779IPEUR
ACTIVE
LQFP
PEU
128
750
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6779
MSP430F6779IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6779
MSP430F6779IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
F6779
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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