TI1 CC3120RNMARGKT/R Simplelink wi-fi wireless network processor internet-of-things solution for mcu application Datasheet

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CC3120
SWAS034 – FEBRUARY 2017
CC3120 SimpleLink™ Wi-Fi® Wireless Network Processor,
Internet-of-Things Solution for MCU Applications
1 Device Overview
1.1
Features
1
• CC3120R SimpleLink™ Wi-Fi® Consists of a
Wireless Network Processor (NWP) and PowerManagement Subsystems
• Featuring Wi-Fi Internet-on-a chip™ Dedicated
ARM® Cortex®-M3 Microcontroller Unit (MCU)
Completely Offloads Wi-Fi and Internet Protocols
from the Application MCU
• Wi-Fi Modes:
– 802.11b/g/n Station
– 802.11b/g Access Point (AP) Supports up to
Four Stations
– Wi-Fi Direct® Client/Group Owner
• WPA2 Personal and Enterprise Security: WEP,
WPA/WPA2 PSK, WPA2 Enterprise (802.1x)
• IPv4 and IPv6 TCP/IP Stack
– Industry-Standard BSD Socket Application
Programming Interfaces (APIs)
– 16 Simultaneous TCP or UDP Sockets
– 6 Simultaneous TLS and SSL Sockets
• IP Addressing: Static IP, LLA, DHCPv4, and
DHCPv6 With Duplicate Address Detection (DAD)
• SimpleLink Connection Manager for Autonomous
and Fast Wi-Fi Connections
• Flexible Wi-Fi Provisioning With SmartConfig™
Technology, AP Mode, and WPS2 Options
• RESTful API Support Using Internal HTTP Server
• Wide Set of Security Features
– Hardware Features
– Separate Execution Environments
– Device Identity
– Networking security
– Personal and Enterprise Wi-Fi Security
– Secure Sockets (SSLv3, TLS1.0/1.1/TLS1.2)
– HTTPS Server
– Trusted Root-Certificate Catalog
– TI Root-of-Trust Public key
– Software IP protection
– Secure Key Storage
– File System Security
– Software Tamper Detection
– Cloning Protection
• Embedded Network Applications Running on the
Dedicated NWP
– HTTP/HTTPS Web Server With Dynamic User
Callbacks
– mDNS, DNS-SD, DHCP Server
– Ping
• Recovery Mechanism—Can Recover to Factory
Defaults or to a Complete Factory Image
• Wi-Fi TX Power
– 18.0 dBm @ 1 DSSS
– 14.5 dBm @ 54 OFDM
• Wi-Fi RX Sensitivity
– –96.0 dBm @ 1 DSSS
– –74.5 dBm @ 54 OFDM
• Application Throughput
– UDP: 16 Mbps
– TCP: 13 Mbps
• Power-Management Subsystem
– Integrated DC-DC Converters Support a Wide
Range of Supply Voltage:
– VBAT Wide-Voltage Mode: 2.1 V to 3.6 V
– VIO is Always Tied With VBAT
– Preregulated 1.85-V Mode
– Advanced Low-Power Modes
– Shutdown: 1 µA
– Hibernate: 4.5 µA
– Low-Power Deep Sleep (LPDS): 115 µA
– RX Traffic: 59 mA @ 54 OFDM
– TX Traffic: 229 mA @ 54 OFDM, Maximum
Power
– Idle Connected (MCU in LPDS): 690 µA @
DTIM = 1
• Clock Source
– 40.0-MHz Crystal With Internal Oscillator
– 32.768-kHz Crystal or External RTC
• RGK Package
– 64-Pin, 9-mm × 9-mm Very Thin Quad Flat
Nonleaded (VQFN) Package, 0.5-mm Pitch
• Operating Temperature
– Ambient Temperature Range: –40°C to +85°C
• Device Supports SimpleLink Developers
Ecosystem
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC3120
SWAS034 – FEBRUARY 2017
1.2
•
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Applications
For Internet-of-Things (IoT) applications, such as:
– Cloud Connectivity
– Internet Gateway
– Home and Building Automation
– Appliances
– Access Control
– Security Systems
– Smart Energy
1.3
–
–
–
–
–
–
Industrial Control
Smart Plug and Metering
Wireless Audio
IP Network Sensor Nodes
Asset Tracking
Medical Devices
Description
The CC3120R device is part of the SimpleLink™ microcontroller (MCU) platform which consists of Wi-Fi,
Bluetooth® low energy, Sub-1 GHz and host MCUs, which all share a common, easy-to-use development
environment with a single core software development kit (SDK) and rich tool set. A one-time integration of
the SimpleLink platform enables you to add any combination of the portfolio’s devices into your design,
allowing 100 percent code reuse when your design requirements change. For more information, visit
Overview for SimpleLink™ solutions.
Connect any microcontroller (MCU) to the Internet of Things (IoT) cloud with the CC3120R device from
Texas Instruments™. The Wi-Fi® Alliance CERTIFIED® CC3120R device is part of the second generation
of the SimpleLink™ Wi-Fi family that dramatically simplifies the implementation of low-power Internet
connectivity.
The CC3120R has all of the Wi-Fi and Internet protocols implemented in the ROM, which runs from the
dedicated on-chip ARM® network processor and significantly offloads the host MCU and simplifies the
system integration.
The CC3120R Wi-Fi Internet-on-a chip™ device contains a dedicated ARM MCU that offloads many of the
networking activities from the host MCU. This subsystem includes an 802.11b/g/n radio, baseband, and
MAC with a powerful crypto engine for fast, secure Internet connections with 256-bit encryption. The
CC3120R device supports station, AP, and Wi-Fi direct modes. The device also supports WPA2 personal
and enterprise security. The device includes embedded TCP/IP and TLS/SSL stacks, an HTTP server,
and multiple Internet protocols. The CC3120R device supports a variety of Wi-Fi provisioning methods,
including HTTP based on AP mode, SmartConfig™ technology, and WPS2.0.
As part of TI’s SimpleLink Wi-Fi family second generation, the CC3120R device introduces the new
features and enhanced capabilities, such as the following:
IPv6
Enhanced Wi-Fi provisioning
Enhanced power consumption
Wi-Fi AP connection with up to four stations
More concurrently opened BSD sockets; up to 16 BSD sockets, of which 6 are secure
HTTPS support
RESTful API support
Asymmetric keys crypto library
The CC3120R device is delivered with a slim and user-friendly host driver to simplify the integration and
development of networking applications. The host driver can easily be ported to most platforms and
operating systems (OS). The driver is written in strict ANSI-C (C89) and requires minimal platform
adaptation layer (porting layer). The driver has a small memory footprint and can run on 8-, 16-, or 32-bit
microcontrollers with any clock speed (no performance or real-time dependency).
2
Device Overview
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The CC3120R device comes in an easy-to-layout VQFN package and is delivered as a complete platform
solution, including various tools and software, sample applications, user and programming guides,
reference designs, and the TI E2E™ support community. The CC3120R device is part of the SimpleLink
MCU Ecosystem.
Device Information (1)
PART NUMBER
CC3120RNMARGKT/R
(1)
PACKAGE
BODY SIZE
VQFN (64)
9.00 mm × 9.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
Device Overview
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1.4
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Functional Block Diagrams
Figure 1-1 shows the CC3120R hardware overview.
Network
Processor
ROM
‡ :L-Fi Driver
‡ TCP/IP Stack
‡ TLS/SSL Stack
‡ Net Apps
RAM
Crypto Engine
ARM Cortex-M3
MAC Processor
UART
DC-DC
Oscillators
LNA
System
Synthesizer
PA
Host I/F
SPI
Baseband
Radio
Copyright © 2017, Texas Instruments Incorporated
Figure 1-1. CC3120R Hardware Overview
Figure 1-2 shows an overview of the CC3120R embedded software.
User Application
SimpleLink Driver
SPI or UART Driver
External Microcontroller
Internet Protocols
TLS/SSL
Embedded Internet
TCP/IP
Supplicant
Wi-Fi Driver
Wi-Fi MAC
Embedded Wi-Fi
Wi-Fi Baseband
Wi-Fi Radio
ARM Processor (Wi-Fi Network Processor)
Copyright © 2017, Texas Instruments Incorporated
Figure 1-2. CC3120R Software Overview
4
Device Overview
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SWAS034 – FEBRUARY 2017
Table of Contents
1
2
3
Device Overview ......................................... 1
4.13
Timing and Switching Characteristics ............... 18
1.1
Features .............................................. 1
4.14
External Interfaces
1.2
Applications ........................................... 2
4.15
Host UART .......................................... 28
1.3
Description ............................................ 2
1.4
Functional Block Diagrams ........................... 4
5.1
Overview
Revision History ......................................... 5
Terminal Configuration and Functions .............. 6
5.2
Functional Block Diagram ........................... 30
5.3
Device Features ..................................... 31
.......................................... 6
3.2
Pin Attributes ......................................... 7
3.3
Connections for Unused Pins ........................ 9
Specifications ........................................... 10
4.1
Absolute Maximum Ratings ......................... 10
4.2
ESD Ratings ........................................ 10
4.3
Power-On Hours .................................... 10
4.4
Recommended Operating Conditions ............... 10
4.5
Current Consumption Summary .................... 11
5.4
Power-Management Subsystem .................... 36
5.5
Low-Power Operating Modes ....................... 37
5.6
Memory .............................................. 38
5.7
Restoring Factory Default Configuration ............ 39
3.1
4
Pin Diagram
4.6
TX Power and IBAT versus TX Power Level
Settings .............................................. 12
4.7
.................
Electrical Characteristics (3.3 V, 25°C) .............
WLAN Receiver Characteristics ....................
WLAN Transmitter Characteristics ..................
WLAN Filter Requirements..........................
4.8
4.9
4.10
4.11
4.12
5
Brownout and Blackout Conditions
6
7
..................................
26
Detailed Description ................................... 30
............................................
30
Applications, Implementation, and Layout........ 40
6.1
Application Information .............................. 40
6.2
PCB Layout Guidelines
.............................
45
Device and Documentation Support ............... 48
.................................
7.1
Tools and Software
7.2
Device Nomenclature ............................... 49
48
7.3
Documentation Support ............................. 49
14
7.4
Community Resources .............................. 50
15
7.5
Trademarks.......................................... 51
16
7.6
Electrostatic Discharge Caution ..................... 51
16
7.7
Export Control Notice
17
7.8
Glossary ............................................. 51
Thermal Resistance Characteristics for RGK
Package ............................................. 17
8
...............................
51
Mechanical, Packaging, and Orderable
Information .............................................. 52
2 Revision History
DATE
REVISION
NOTES
February 2017
SWAS034*
Initial Release
Revision History
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3 Terminal Configuration and Functions
3.1
Pin Diagram
VDD_ANA1
VDD_ANA2
DCDC_ANA2_SW_N
DCDC_ANA2_SW_P
VIN_DCDC_DIG
DCDC_DIG_SW
DCDC_PA_OUT
DCDC_PA_SW_N
DCDC_PA_SW_P
VIN_DCDC_PA
DCDC_ANA_SW
VIN_DCDC_ANA
LDO_IN1
SOP0
SOP1
VDD_PA_IN
Figure 3-1 shows pin assignments for the 64-pin VQFN package.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
53
28
NC
VIN_IO2
54
27
NC
UART1_TX
55
26
NC
VDD_DIG2
56
25
LDO_IN2
UART1_RX
57
24
VDD_PLL
TEST_58
58
23
WLAN_XTAL_P
TEST_59
59
22
WLAN_XTAL_N
TEST_60
60
21
SOP2/TCXO_EN
UART1_nCTS
61
20
NC
TEST_62
62
19
RESERVED
NC
63
18
NC
NC
64
17
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
RESERVED
HOSTINTR
29
FLASH_SPI_CS
52
FLASH_SPI_MISO
RTC_XTAL_N
FLASH_SPI_MOSI
RESERVED
FLASH_SPI_CLK
30
VIN_IO1
51
VDD_DIG1
RTC_XTAL_P
HOST_SPI_nCS
RF_BG
HOST_SPI_MISO
31
HOST_SPI_MOSI
50
HOST_SPI_CLK
UART1_nRTS
NC
nRESET
RESERVED
32
nHIB
49
NC
VDD_RAM
Figure 3-1. VQFN 64-Pin Assignments
Top View
6
Terminal Configuration and Functions
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3.2
SWAS034 – FEBRUARY 2017
Pin Attributes
Table 3-1 describes the CC3120R pins.
NOTE
If an external device drives a positive voltage to signal pads when the CC3120R device is
not powered, DC current is drawn from the other device. If the drive strength of the external
device is adequate, an unintentional wakeup and boot of the CC3120R device can occur. To
prevent current draw, TI recommends one of the following:
• All devices interfaced to the CC3120R device must be powered from the same power rail
as the CC3120R device.
• Use level shifters between the CC3120R device and any external devices fed from other
independent rails.
• The nRESET pin of the CC3120R device must be held low until the VBAT supply to the
device is driven and stable.
Table 3-1. Pin Attributes
PIN
STATE AT RESET
AND HIBERNATE
I/O TYPE (1)
DESCRIPTION
nHIB
Hi-Z
I
Hibernate signal input to the NWP subsystem
(active low). This is connected to the MCU
GPIO. If the GPIO from the MCU can float
while the MCU enters low power, consider
adding a pullup resistor on the board to avoid
floating.
3
Reserved
Hi-Z
–
Reserved for future use
5
HOST_SPI_CLK
Hi-Z
I
Host interface SPI clock
6
HOST_SPI_MOSI
Hi-Z
I
Host interface SPI data input
7
HOST_SPI_MISO
Hi-Z
O
Host interface SPI data output
8
HOST_SPI_nCS
Hi-Z
I
Host interface SPI chip select (active low)
9
VDD_DIG1
Hi-Z
Power
Digital core supply (1.2 V)
10
VIN_IO1
Hi-Z
Power
I/O supply
11
FLASH_SPI_CLK
Hi-Z
O
Serial flash interface: SPI clock
12
FLASH_SPI_MOSI
Hi-Z
O
Serial flash interface: SPI data out
13
FLASH _SPI_MISO
Hi-Z
I
Serial flash interface: SPI data in (active high)
14
FLASH _SPI_CS
Hi-Z
O
Serial flash interface: SPI chip select
(active low)
15
HOST_INTR
Hi-Z
O
Interrupt output (active high)
19
Reserved
Hi-Z
–
Connect a 100-kΩ pulldown resistor to ground.
21
SOP2/TCXO_EN
Hi-Z
O
Controls restore to default mode. Enable signal
for external TCXO. Add a 10-kΩ pulldown
resistor to ground.
22
WLAN_XTAL_N
Hi-Z
Analog
Connect the WLAN 40-MHz XTAL here.
23
WLAN_XTAL_P
Hi-Z
Analog
Connect the WLAN 40-MHz XTAL here.
24
VDD_PLL
Hi-Z
Power
Internal PLL power supply (1.4 V nominal)
25
LDO_IN2
Hi-Z
Power
Input to internal LDO
Reserved
Hi-Z
O
Reserved for future use
31
RF_BG
Hi-Z
RF
2.4-GHz RF TX, RX
32
nRESET
Hi-Z
I
2
29
30
(1)
DEFAULT FUNCTION
RESET input for the device. Active low input.
Use RC circuit (100 k || 0.1 µF) for power on
reset (POR).
I = Input
O = Output RF = radio frequency
I/O = bidirectional
Terminal Configuration and Functions
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Table 3-1. Pin Attributes (continued)
8
PIN
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE (1)
33
VDD_PA_IN
Hi-Z
Power
Power supply for the RF power amplifier (PA)
34
SOP1
Hi-Z
–
Controls restore to default mode. Add 100-kΩ
pulldown to ground. Factory default function.
35
SOP0
Hi-Z
–
Controls restore to default mode. Add 100-kΩ
pulldown to ground. Factory default function.
36
LDO_IN1
Hi-Z
Power
Input to internal LDO
37
VIN_DCDC_ANA
Hi-Z
Power
Power supply for the DC-DC converter for
analog section
38
DCDC_ANA_SW
Hi-Z
Power
Analog DC-DC converter switch output
39
VIN_DCDC_PA
Hi-Z
Power
PA DC-DC converter input supply
40
DCDC_PA_SW_P
Hi-Z
Power
PA DC-DC converter switch output +ve
41
DCDC_PA_SW_N
Hi-Z
Power
PA DC-DC converter switch output –ve
42
DCDC_PA_OUT
Hi-Z
Power
PA DC-DC converter output. Connect the
output capacitor for DC-DC here.
43
DCDC_DIG_SW
Hi-Z
Power
Digital DC-DC converter switch output
44
VIN_DCDC_DIG
Hi-Z
Power
Power supply input for the digital DC-DC
converter
45
DCDC_ANA2_SW_P
Hi-Z
Power
Analog2 DC-DC converter switch output +ve
46
DCDC_ANA2_SW_N
Hi-Z
Power
Analog2 DC-DC converter switch output –ve
47
VDD_ANA2
Hi-Z
Power
Analog2 power supply input
48
VDD_ANA1
Hi-Z
Power
Analog1 power supply input
49
VDD_RAM
Hi-Z
Power
Power supply for the internal RAM
50
UART1_nRTS
Hi-Z
O
51
RTC_XTAL_P
Hi-Z
Analog
32.768-kHz XTAL_P or external CMOS level
clock input
52
RTC_XTAL_N
Hi-Z
Analog
32.768-kHz XTAL_N or 100-kΩ external pullup
for external clock
54
VIN_IO2
Hi-Z
Power
I/O power supply. Same as battery voltage.
55
UART1_TX
Hi-Z
O
56
VDD_DIG2
Hi-Z
Power
57
UART1_RX
Hi-Z
I
UART host interface; connect to test point on
prototype for flash programming.
58
TEST_58
–
Test signal; connect to an external test point.
59
TEST_59
–
Test signal; connect to an external test point.
DESCRIPTION
UART host interface (active low)
UART host interface. Connect to test point on
prototype for flash programming.
Digital power supply (1.2 V)
60
TEST_60
Hi-Z
O
Test signal; connect to an external test point.
61
UART1_nCTS
Hi-Z
I
UART host interface (active low)
62
TEST_62
Hi-Z
O
Test signal; connect to an external test point.
65
GND
Power
Terminal Configuration and Functions
Ground tab used as thermal and electrical
ground
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3.3
SWAS034 – FEBRUARY 2017
Connections for Unused Pins
All unused pins must be left as no connect (NC) pins. Table 3-2 provides a list of NC pins.
Table 3-2. Connections for Unused Pins
(1)
PIN
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE (1)
1
NC
WLAN analog
–
Unused; leave unconnected.
DESCRIPTION
4
NC
WLAN analog
–
Unused; leave unconnected.
16
NC
WLAN analog
–
Unused; leave unconnected.
17
NC
WLAN analog
–
Unused; leave unconnected.
18
NC
WLAN analog
–
Unused; leave unconnected.
20
NC
WLAN analog
–
Unused; leave unconnected.
26
NC
WLAN analog
–
Unused; leave unconnected.
27
NC
WLAN analog
–
Unused; leave unconnected.
28
NC
WLAN analog
–
Unused; leave unconnected.
26
NC
WLAN analog
–
Unused; leave unconnected.
27
NC
WLAN analog
–
Unused; leave unconnected.
28
NC
WLAN analog
–
Unused; leave unconnected.
53
NC
WLAN analog
–
Unused; leave unconnected.
63
NC
WLAN analog
–
Unused; leave unconnected.
64
NC
WLAN analog
–
Unused; leave unconnected.
I = Input
O = Output RF = radio frequency
I/O = bidirectional
Terminal Configuration and Functions
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4 Specifications
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over
process and voltage, unless otherwise indicated.
4.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
3.8
V
0.0
V
–0.5
VIO + 0.5
V
–0.5
2.1
V
–0.5
2.1
V
Operating temperature, TA
–40
85
°C
Storage temperature, Tstg
–55
125
°C
VBAT and VIO
Pins: 37, 39, 44
VIO – VBAT (differential)
Pins: 10, 54
Digital inputs
RF pins
Analog pins, XTAL
4.2
Pins: 22, 23, 51, 52
UNIT
ESD Ratings
VALUE
VESD
(1)
(2)
4.3
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Power-On Hours
NOTE
This information is provided solely for your convenience and does not extend or modify the
warranty provided under TI's standard terms and conditions for TI semiconductor products.
CONDITIONS
POH
TA up to 85°C (1)
(1)
4.4
87,600
The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device
can be in any other state.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
VBAT, VIO
(shorted to VBAT)
Pins: 10, 37, 39,
44, 54
Direct battery connection (3)
(3)
(4)
(5)
(6)
10
TYP
MAX
3.3
3.6
Preregulated 1.85 V (5) (6)
Ambient thermal slew
(1)
(2)
MIN
2.1 (4)
–20
20
UNIT
V
°C/minute
Operating temperature is limited by crystal frequency variation.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the transmission.
To ensure WLAN performance, ripple on the 2.1- to 3.3-V supply must be less than ±300 mV.
The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1
V, and care must be taken when operating at the minimum specified voltage.
To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV).
TI recommends keeping VBAT above 1.85 V. For lower voltages, use a boost converter.
Specifications
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4.5
SWAS034 – FEBRUARY 2017
Current Consumption Summary
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS (1)
PARAMETER
1 DSSS
TX
6 OFDM
54 OFDM
RX (3)
(2)
MIN
TYP
TX power level = 0
272
TX power level = 4
188
TX power level = 0
248
TX power level = 4
179
TX power level = 0
223
TX power level = 4
160
1 DSSS
53
54 OFDM
53
Idle connected (4)
690
LPDS
115
Hibernate
(5)
Peak calibration current (6) (3)
(1)
(2)
(3)
(4)
(5)
(6)
MAX
UNIT
mA
mA
µA
4
VBAT = 3.3 V
450
VBAT = 2.1 V
670
VBAT = 1.85 V
700
mA
TX power level = 0 implies maximum power (see Figure 4-1, Figure 4-2, and Figure 4-3). TX power level = 4 implies output power
backed off approximately 4 dB.
The CC3120R system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
The RX current is measured with a 1-Mbps throughput rate.
DTIM = 1
For the 1.85-V mode, the hibernate current is higher by 50 µA across all operating modes because of leakage into the PA and analog
power inputs.
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed
sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two
additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC3120,
CC3220 SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
Specifications
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TX Power and IBAT versus TX Power Level Settings
Figure 4-1, Figure 4-2, and Figure 4-3 show TX Power and IBAT versus TX power level settings for
modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively.
In Figure 4-1, the area enclosed in the circle represents a significant reduction in current during transition
from TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI
recommends using TX power level 4 to reduce the current.
1 DSSS
19.00
280.00
Color by
17.00
264.40
TX Power (dBm)
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
IBAT (VBAT @ 3.6 V)(mAmp)
TX Power (dBm)
15.00
15
Figure 4-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 4-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
12
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54 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 4-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
Specifications
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Brownout and Blackout Conditions
The device enters a brownout condition when the input voltage drops below Vbrownout (see Figure 4-4 and
Figure 4-5). This condition must be considered during design of the power supply routing, especially when
operating from a battery. High-current operations, such as a TX packet or any external activity (not
necessarily related directly to networking) can cause a drop in the supply voltage, potentially triggering a
brownout condition. The resistance includes the internal resistance of the battery, the contact resistance of
the battery holder (four contacts for 2× AA batteries), and the wiring and PCB routing resistance.
NOTE
When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect
during HIBERNATE state.
Figure 4-4. Brownout and Blackout Levels (1 of 2)
Figure 4-5. Brownout and Blackout Levels (2 of 2)
14
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In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the
Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The
blackout condition is equivalent to a hardware reset event in which all states within the device are lost.
Table 4-1 lists the brownout and blackout voltage levels.
Table 4-1. Brownout and Blackout Voltage Levels
VOLTAGE LEVEL
UNIT
Vbrownout
CONDITION
2.1
V
Vblackout
1.67
V
4.8
Electrical Characteristics (3.3 V, 25°C)
GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VIL
Low-level input voltage
–0.5
IIH
High-level input current
5
nA
IIL
Low-level input current
5
nA
VOH
VOL
IOH
IOL
VIL
(1)
4
UNIT
CIN
High-level output voltage
Low-level output voltage
High-level
source
current,
Low-level sink
current,
pF
VDD + 0.5 V
0.35 × VDD
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 8 mA; configured I/O drive
strength = 8 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 8 mA; configured I/O drive
strength = 8 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.35
2-mA drive
2
4-mA drive
4
6-mA drive
6
2-mA drive
2
4-mA drive
4
6-mA drive
6
nRESET (1)
0.6
V
V
V
V
mA
mA
V
The nRESET pin must be held below 0.6 V for the device to register a reset.
Specifications
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WLAN Receiver Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).
PARAMETER
Sensitivity
(8% PER for 11b rates, 10% PER for
11g/11n rates) (10% PER) (2)
Maximum input level
(10% PER)
(1)
(2)
(3)
TEST CONDITIONS (Mbps)
MIN
TYP (1)
1 DSSS
–96.0
2 DSSS
–94.0
11 CCK
–88.0
6 OFDM
–90.5
9 OFDM
–90.0
18 OFDM
–86.5
36 OFDM
–80.5
54 OFDM
–74.5
MCS7 (GF) (3)
–71.5
MCS7 (MM) (3)
–70.5
802.11b
–4.0
802.11g
–10.0
MAX
UNIT
dBm
dBm
In preregulated 1.85-V mode, RX sensitivity is 0.25- to 1-dB lower.
Sensitivity is 1-dB worse on channel 13 (2472 MHz).
Sensitivity for mixed mode is 1-dB worse.
4.10 WLAN Transmitter Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 7 (2442 MHz). (1)
PARAMETER
Maximum RMS output power measured at 1
dB from IEEE spectral mask or EVM
TEST CONDITIONS (2)
MIN
+18.0
2 DSSS
+18.0
11 CCK
+18.3
6 OFDM
+17.3
9 OFDM
+17.3
18 OFDM
+17.0
36 OFDM
+16.0
54 OFDM
+14.5
MCS7 (MM)
Transmit center frequency accuracy
(1)
(2)
16
TYP
1 DSSS
MAX
UNIT
dBm
+13.0
–25
25
ppm
Channel-to-channel variation is up to 2 dB. The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission
limits.
In preregulated 1.85-V mode, maximum TX power is 0.25- to 0.75-dB lower for modulations higher than 18 OFDM.
Specifications
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4.11 WLAN Filter Requirements
The device requires an external band-pass filter to meet the various emission standards, including FCC.
Table 4-2 presents the attenuation requirements for the band-pass filter. TI recommends using the same
filter used in the reference design to ease the process of certification.
Table 4-2. WLAN Filter Requirements
PARAMETER
FREQUENCY (MHz)
Return loss
2412 to 2484
Insertion loss (1)
2412 to 2484
Attenuation
Reference impendence
TYP
MAX
1
1.5
UNIT
10
dB
800 to 830
30
45
1600 to 1670
20
25
3200 to 3300
30
48
4000 to 4150
45
50
4800 to 5000
20
25
5600 to 5800
20
25
6400 to 6600
20
35
7200 to 7500
35
45
7500 to 10000
20
25
2412 to 2484
Filter type
(1)
MIN
dB
dB
50
Ω
Bandpass
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
4.12 Thermal Resistance Characteristics for RGK Package
AIR FLOW
PARAMETER
0 lfm (C/W)
150 lfm (C/W)
250 lfm (C/W)
500 lfm (C/W)
θja
23
14.6
12.4
10.8
Ψjt
0.2
0.2
0.3
0.1
Ψjb
2.3
2.3
2.2
2.4
θjc
6.3
θjb
2.4
Specifications
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4.13 Timing and Switching Characteristics
4.13.1 Power Supply Sequencing
For proper operation of the CC3120R device, perform the recommended power-up sequencing as follows:
1. Tie VBAT (pins 37, 39, 44) and VIO (pins 54 and 10) together on the board.
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit
(100 K ||, 1 µF, RC = 100 ms).
3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).
For timing diagrams, see Section 4.13.3.
4.13.2 Device Reset
When a device restart is required, the user may either issue a negative pulse on the nHIB pin (pin 2) or on
the nRESET pin (pin 32), keeping the other pulled high, depending on the configuration of the platform. In
case the nRESET pin is used, the user must follow one of the two alternatives to ensure the reset is
properly applied:
• A high-to-low reset pulse (on pin 32) of at least 200-mS duration
• If the above cannot be ensured, a pulldown resistor of 2M Ω should be connected to pin 32
(RTC_XTAL_N). If implemented, a shorter pulse of at least 100 uSec can be used.
To ensure a proper reset sequence, the user has to call the sl_stop function prior to toggling the reset.
4.13.3 Reset Timing
4.13.3.1 nRESET (32k XTAL)
Figure 4-6 shows the reset timing diagram for the 32k XTAL first-time power-up and reset removal.
T2
T1
T3
VBAT
VIO
nRESET
nHIB
STATE POWER RESET
OFF
HW INIT
Device Ready to
serve API calls
FW INIT
32-kHz
XTAL
Figure 4-6. First-Time Power-Up and Reset Removal Timing Diagram (32k XTAL)
Table 4-3 describes the timing requirements for the XTAL first-time power-up and reset removal.
Table 4-3. First-Time Power-Up and Reset Removal Timing Requirements (32k XTAL)
ITEM
NAME
T1
Supply settling time
T2
Hardware wake-up time
T3
Initialization time
18
DESCRIPTION
Depends on application board
power supply, decoupling
capacitor, and so on
32-kHz XTAL settling plus
firmware initialization time plus
radio calibration
Specifications
MIN
TYP
MAX
UNIT
3
ms
25
ms
1.35
s
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4.13.3.2 nRESET (External 32K)
Figure 4-7 shows the reset timing diagram for the external 32K first-time power-up and reset removal.
T1
T2
T3
RESET
HW INIT
FW INIT
VBAT
VIO
nRESET
nHIB
STATE
POWER
OFF
Device Ready to
serve API calls
32-kHz
RTC CLK
Figure 4-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32K)
describes the timing requirements for the external first-time power-up and reset removal.
Table 4-4. First-Time Power-Up and Reset Removal Timing Requirements (External 32K)
ITEM
NAME
T1
Supply settling time
T2
Hardware wake-up time
T3
Initialization time
DESCRIPTION
Depends on application board power
supply, decoupling capacitor, and so
on
Firmware initialization time plus
radio calibration
MIN
TYP
MAX
UNIT
3
ms
25
ms
250
ms
Specifications
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4.13.3.3 Wakeup From HIBERNATE Mode
Figure 4-8 shows the timing diagram for wakeup from HIBERNATE mode.
Thib_min
Twake_from_hib
HIBERNATE
HW WAKEUP+FW INIT
VBAT
VIO
nRESET
nHIB
ACTIVE
ACTIVE
HIBERNATE
32-kHz
XTAL/CXO
Figure 4-8. nHIB Timing Diagram
NOTE
The 32.768-kHz XTAL is kept enabled by default when the chip goes into HIBERNATE mode
in response to nHIB being pulled low.
Table 4-5 describes the timing requirements for nHIB.
Table 4-5. nHIB Timing Requirements
ITEM
NAME
DESCRIPTION
Thib_min
Minimum hibernate time
Minimum pulse width of nHIB being low (1)
Twake_from_hib
Hardware wakeup time plus
firmware initialization time
See (2)
(1)
(2)
MIN
TYP
10
MAX
UNIT
ms
50
ms
Ensure that the nHIB pulse width is kept above the minimum requirement under all conditions (such as power up, MCU reset, and so
on).
If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.
4.13.4 Clock Specifications
The CC3120R device requires two separate clocks for its operation:
• A slow clock running at 32.768 kHz is used for the RTC.
• A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN
subsystem.
The device features internal oscillators that enable the use of less-expensive crystals rather than
dedicated TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing
clock on the system and to reduce overall cost.
20
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4.13.4.1 Slow Clock Using Internal Oscillator
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow
clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between
RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm
requirement.
Figure 4-9 shows the crystal connections for the slow clock.
51
RTC_XTAL_P
10 pF
GND
32.768 kHz
52
RTC_XTAL_N
10 pF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 4-9. RTC Crystal Connections
Table 4-6 lists the RTC crystal requirements.
Table 4-6. RTC Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
MAX
UNIT
±150
ppm
32.768
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
32.768 kHz
kHz
70
kΩ
4.13.4.2 Slow Clock Using an External Clock
When an RTC oscillator is present in the system, the CC3120R device can accept this clock directly as an
input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock
must be a CMOS-level clock compatible with VIO fed to the device.
Figure 4-10 shows the external RTC input connection.
RTC_XTAL_P
32.768 kHz
VIO
Host system
100 KΩ
RTC_XTAL_N
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Figure 4-10. External RTC Input
Specifications
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Table 4-7 lists the external RTC digital clock requirements.
Table 4-7. External RTC Digital Clock Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
Frequency accuracy
(Initial plus temperature plus aging)
tr, tf
Vil
Square wave, DC coupled
ppm
50%
ns
80%
0.65 × VIO
VIO
0
0.35 × VIO
1
Input impedance
UNIT
±150
100
20%
Slow clock input voltage limits
MAX
Hz
Input transition time tr, tf (10% to
90%)
Frequency input duty cycle
Vih
TYP
32768
V
Vpeak
MΩ
5
pF
4.13.4.3 Fast Clock (Fref) Using an External Crystal
The CC3120R device also incorporates an internal crystal oscillator to support a crystal-based fast clock.
The XTAL is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable
loading capacitors.
Figure 4-11 shows the crystal connections for the fast clock.
23
WLAN_XTAL_P
6.2 pF
GND
40 MHz
WLAN_XTAL_N
22
6.2 pF
GND
SWAS031-030
NOTE: The XTAL capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency
Tuning for information on frequency tuning.
Figure 4-11. Fast Clock Crystal Connections
22
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Table 4-8 lists the WLAN fast-clock crystal requirements.
Table 4-8. WLAN Fast-Clock Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
Frequency
MAX
UNIT
40
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
40 MHz
MHz
±25
ppm
60
Ω
4.13.4.4 Fast Clock (Fref) Using an External Oscillator
The CC3120R device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation,
the clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The
external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power
consumption of the system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using
the LDO improves noise on the TCXO power supply.
Figure 4-12 shows the connection.
Vcc
XO (40 MHz)
C
CC3120R
EN
TCXO_EN
82 pF
WLAN_XTAL_P
OUT
WLAN_XTAL_N
Copyright © 2017, Texas Instruments Incorporated
Figure 4-12. External TCXO Input
Table 4-9 lists the external Fref clock requirements.
Table 4-9. External Fref Clock Requirements (–40°C to +85°C)
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
Frequency accuracy (Initial plus temperature plus
aging)
45%
Sine or clipped sine wave, AC
coupled
Clock voltage limits
0.7
@ 1 kHz
Phase noise @ 40 MHz
55%
1.2
–143
12
Capacitance
kΩ
7
Specifications
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Vpp
–138.5 dBc/Hz
@ 100 kHz
Input impedance
ppm
–125
@ 10 kHz
Resistance
50%
UNIT
MHz
±25
Frequency input duty cycle
Vpp
MAX
40.00
pF
23
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4.13.5 Interfaces
This section describes the interfaces that are supported by the CC3120R device:
• Host SPI
• Flash SPI
4.13.5.1 Host SPI Interface Timing
Figure 4-13 shows the Host SPI interface timing diagram.
I2
CLK
I6
I7
MISO
I9
I8
MOSI
SWAS032-017
Figure 4-13. Host SPI Interface Timing
Table 4-10 lists the Host SPI interface timing parameters.
Table 4-10. Host SPI Interface Timing Parameters
PARAMETER
NUMBER
(1)
(2)
24
MIN
MAX
Clock frequency @ VBAT = 3.3 V
20
Clock frequency @ VBAT ≤ 2.1 V
12
UNIT
I1
F (1)
I2
tclk (2) (1)
Clock period
I3
tLP (1)
Clock low period
I4
tHT
(1)
I5
D (1)
Duty cycle
I6
tIS (1)
RX data setup time
4
ns
I7
tIH (1)
RX data hold time
4
ns
(1)
I8
tOD
I9
tOH (1)
50
Clock high period
45%
MHz
ns
25
ns
25
ns
55%
TX data output delay
20
ns
TX data hold time
24
ns
The timing parameter has a maximum load of 20 pF at 3.3 V.
Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. nCS can be deasserted 10 ns after the clock edge.
Specifications
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4.13.5.2 Flash SPI Interface Timing
Figure 4-14 shows the Flash SPI interface timing diagram.
I2
CLK
I6
I7
MISO
I9
I8
MOSI
SWAS032-017
Figure 4-14. Flash SPI Interface Timing
Table 4-11 lists the Flash SPI interface timing parameters.
Table 4-11. Flash SPI Interface Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
20
MHz
I1
F
Clock frequency
I2
tclk
Clock period
I3
tLP
Clock low period
25
ns
I4
tHT
Clock high period
25
ns
I5
D
Duty cycle
I6
tIS
RX data setup time
1
I7
tIH
RX data hold time
2
I8
tOD
TX data output delay
I9
tOH
TX data hold time
50
45%
ns
55%
ns
ns
8.5
ns
8
ns
Specifications
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4.14 External Interfaces
4.14.1 SPI Flash Interface
The external serial flash stores the user profiles and firmware patch updates. The CC3120R device acts
as a master in this case; the SPI serial flash acts as the slave device. This interface can work up to a
speed of 20 MHz.
Figure 4-15 shows the SPI flash interface.
CC3120R (master)
Serial flash
FLASH_SPI_CLK
SPI_CLK
FLASH_SPI_CS
SPI_CS
FLASH_SPI_MISO
SPI_MISO
FLASH_SPI_MOSI
SPI_MOSI
Copyright © 2017, Texas Instruments Incorporated
Figure 4-15. SPI Flash Interface
Table 4-12 lists the SPI flash interface pins.
Table 4-12. SPI Flash Interface
PIN NAME
DESCRIPTION
FLASH_SPI_CLK
Clock (up to 20 MHz) CC3120R device to serial flash
FLASH_SPI_CS
CS signal from CC3120R device to serial flash
FLASH_SPI_MISO
Data from serial flash to CC3120R device
FLASH_SPI_MOSI
Data from CC3120R device to serial flash
26
Specifications
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4.14.2 SPI Host Interface
The device interfaces to an external host using the SPI interface. The CC3120R device can interrupt the
host using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can
work up to a speed of 20 MHz.
Figure 4-16 shows the SPI host interface.
MCU
CC3120R (slave)
HOST_SPI_CLK
SPI_CLK
HOST_SPI_nCS
SPI_nCS
HOST_SPI_MISO
SPI_MISO
HOST_SPI_MOSI
SPI_MOSI
HOST_INTR
INTR
nHIB
GPIO
Copyright © 2017, Texas Instruments Incorporated
Figure 4-16. SPI Host Interface
Table 4-13 lists the SPI host interface pins.
Table 4-13. SPI Host Interface
PIN NAME
DESCRIPTION
HOST_SPI_CLK
Clock (up to 20 MHz) from MCU host to CC3120R device
HOST_SPI_nCS
CS (active low) signal from MCU host to CC3120R device
HOST_SPI_MOSI
Data from MCU host to CC3120R device
HOST_INTR
Interrupt from CC3120R device to MCU host
HOST_SPI_MISO
Data from CC3120R device to MCU host
nHIB
Active-low signal that commands the CC3120R device to enter hibernate mode (lowest
power state)
Specifications
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4.15 Host UART
The SimpleLink device requires the UART configuration described in Table 4-14.
Table 4-14. SimpleLink UART Configuration
PROPERTY
SUPPORTED CC3120R CONFIGURATION
Baud rate
115200 bps, no auto-baud rate detection, can be changed by the host up to 3 Mbps using a special command
Data bits
8 bits
Flow control
CTS/RTS
Parity
None
Stop bits
1
Bit order
LSBit first
Host interrupt polarity
Active high
Host interrupt mode
Rising edge or level 1
Endianness
Little-endian only (1)
(1)
The SimpleLink device does not support automatic detection of the host length while using the UART interface.
4.15.1 5-Wire UART Topology
Figure 4-17 shows the typical 5-wire UART topology comprised of four standard UART lines plus one IRQ
line from the device to the host controller to allow efficient low-power mode.
HOST MCU
UART
nRTS
nRTS
nCTS
nCTS
TX
TX
RX
RX
HOST_INTR(IRQ)
CC3120R SL
UART
HOST_INTR(IRQ)
Copyright © 2017, Texas Instruments Incorporated
Figure 4-17. Typical 5-Wire UART Topology
This topology is recommended because the configuration offers the maximum communication reliability
and flexibility between the host and the SimpleLink device.
4.15.2 4-Wire UART Topology
The 4-wire UART topology eliminates the host IRQ line (see Figure 4-18). Using this topology requires
meeting one of the following conditions:
• The host is always awake or active.
• The host goes to sleep, but the UART module has receiver start-edge detection for auto wakeup and
does not lose data.
HOST MCU
UART
nRTS
nRTS
nCTS
nCTS
TX
TX
RX
RX
H_IRQ
X
CC3120R SL
UART
H_IRQ
Copyright © 2017, Texas Instruments Incorporated
Figure 4-18. 4-Wire UART Configuration
28
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4.15.3 3-Wire UART Topology
The 3-wire UART topology requires only the following lines (see Figure 4-19):
• RX
• TX
• CTS
nRTS
nRTS
X
nCTS
HOST MCU
UART
nCTS
TX
TX
RX
RX
H_IRQ
X
CC3120R SL
UART
H_IRQ
Copyright © 2017, Texas Instruments Incorporated
Figure 4-19. 3-Wire UART Topology
Using this topology requires meeting one of the following conditions:
• The host always stays awake or active.
• The host goes to sleep but the UART module has receiver start-edge detection for auto-wake-up and
does not lose data.
• The host can always receive any amount of data transmitted by the SimpleLink device because there
is no flow control in this direction.
Because there is no full flow control, the host cannot stop the SimpleLink device to send its data; thus, the
following parameters must be carefully considered:
• Maximum baud rate
• RX character interrupt latency and low-level driver jitter buffer
• Time consumed by the user's application
Specifications
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5 Detailed Description
5.1
Overview
The CC3120R Wi-Fi Internet-on-a-chip contains a dedicated ARM MCU that offloads many of the
networking activities from the host MCU. The device includes an 802.11b/g/n radio, baseband, and MAC
with a powerful crypto engine for a fast, secure WLAN and Internet connections with 256-bit encryption.
The CC3120R device supports station, AP, and Wi-Fi Direct modes. The device also supports WPA2
personal and enterprise security and WPS 2.0. The Wi-Fi network processor includes an embedded IPv6
and IPv4 TCP/IP stack.
5.2
Functional Block Diagram
Figure 5-1 shows the functional block diagram of the CC3120R SimpleLink Wi-Fi solution.
VCC
SPI
FLASH
32-kHz
XTAL
40-MHz
XTAL
32 kHz
MCU
MCU
nHIB
CC3120R
Network Processor
HOST_INTR
SPI/UART
Copyright © 2017, Texas Instruments Incorporated
Figure 5-1. Functional Block Diagram
30
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5.3
SWAS034 – FEBRUARY 2017
Device Features
5.3.1
WLAN
The WLAN features are as follows:
• 802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station,
AP, Wi-Fi Direct client and group owner with CCK and OFDM rates in the 2.4-GHz ISM band, channels
1 to 13.
NOTE
802.11n is supported only in Wi-Fi station, Wi-Fi direct, and P2P client mode
•
•
•
•
•
5.3.2
Autocalibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna
without requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in serial-flash allows
automatic fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x).
Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the
provisioning decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point using HTTPS
– SmartConfig Technology: a 1-step, 1-time process to connect a CC3120R-enabled device to the
home wireless network, removing dependency on the I/O capabilities of the host MCU; thus, it is
usable by deeply embedded applications
802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without
adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working
channel, rate, and transmitted power. The receiver mode works with the filtering options.
Network Stack
The Network Stack features are as follows:
• Integrated IPv4, IPv6 TCP/IP stack with BSD (BSD adjacent) socket APIs for simple Internet
connectivity with any MCU, microprocessor, or ASIC
NOTE
Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
•
•
•
Support of 16 simultaneous TCP, UDP, or RAW sockets
Support of 6 simultaneous SSL\TLS sockets
Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
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•
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Built-in network application and utilities:
– HTTP/HTTPS
• Web page content stored on serial flash
• RESTful APIs for setting and configuring application content
• Dynamic user callbacks
– Service discovery: Multicast DNS service discovery lets a client advertise its service without a
centralized server. After connecting to the access point, the CC3120R device provides critical
information, such as device name, IP, vendor, and port number.
– DHCP server
– Ping
Table 5-1 summarizes the NWP features.
Table 5-1. NWP Features
Feature
Description
802.11b/g/n station
Wi-Fi standards
802.11b/g AP supporting up to four stations
Wi-Fi Direct client and group owner
Wi-Fi
Channels 1 to 13
Wi-Fi security
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x)
Wi-Fi provisioning
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP/HTTPS web server
IP protocols
IPv4/IPv6
IP addressing
Static IP, LLA, DHCPv4, DHCPv6 (Stateful) with DAD and stateless auto configuration
Cross layer
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW IP
Ping
HTTP/HTTPS web server
Network applications and
utilities
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
Device identity
Security
Trusted root-certificate catalog
TI root-of-trust public key
Power management
Enhanced power policy management uses 802.11 power save and deep sleep power modes
RF Transceiver
Other
Programmable RX Filters with Events trigger mechanism including WoWLAN
Recovery mechanism – Restore to factory default
32
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5.3.3
SWAS034 – FEBRUARY 2017
Security
The SimpleLink Wi-Fi CC3120R Internet-on-a-chip device enhances the security capabilities available for
development of IoT devices, while completely offloading these activities from the MCU to the networking
subsystem. The security capabilities include the following key features:
Wi-Fi and Internet Security:
• Personal and enterprise Wi-Fi security
– Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK
• WEP
– Enterprise standards
• EAP Fast
• EAP PEAPv0 MSCHAPv2
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2
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•
•
•
•
•
www.ti.com
Secure sockets
– Protocol versions: SSL v3/TLS 1.0/TLS 1.1/TLS 1.2
– On-chip powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES
encryption for TLS and SSL connections
– Ciphers suites
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
– Server authentication
– Client authentication
– Domain name verification
– Socket upgrade to secure socket – STARTTLS
Secure HTTP server (HTTPS)
The Trusted root-certificate catalog verifies that the CA used by the application is trusted and known
secure content delivery
The TI root-of-trust public key is a hardware-based mechanism that allows authenticating TI as the
genuine origin of a given content using asymmetric keys
Secure content delivery allows file transfer to the system in a secure way on any unsecured tunnel
Code and Data Security:
• Secured network information: Network passwords and certificates are encrypted
• Secured and authenticated service pack: SP is signed based on TI certificate
34
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5.3.4
SWAS034 – FEBRUARY 2017
Host Interface and Driver
•
•
•
5.3.5
Interfaces over a 4-wire serial peripheral interface (SPI) with any MCU or a processor at a clock speed
of 20 MHz.
Interfaces over UART with any MCU with a baud rate up to 3 Mbps. A low footprint driver is provided
for TI MCUs and is easily ported to any processor or ASIC.
Simple APIs enable easy integration with any single-threaded or multithreaded application.
System
•
•
•
Works from a single preregulated power supply or connects directly to a battery
Ultra-low leakage when disabled (hibernate mode) with a current of less than 4 µA with the RTC
running
Integrated clock sources
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5.4
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Power-Management Subsystem
The CC3120R power-management subsystem contains DC-DC converters to accommodate the different
voltage or current requirements of the system.
• Digital DC-DC (Pin 44)
– Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
• ANA1 DC-DC (Pin 38)
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the ANA1 DC-DC converter is bypassed.
• PA DC-DC (Pin 39)
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the PA DC-DC converter is bypassed.
The CC3120R device is a single-chip WLAN radio solution used on an embedded system with a widevoltage supply range. The internal power management, including DC-DC converters and LDOs, generates
all of the voltages required for the device to operate from a wide variety of input sources. For maximum
flexibility, the device can operate in the modes described in Section 5.4.1 and Section 5.4.2.
5.4.1
VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the device is powered directly by the battery or preregulated 3.3-V
supply. All other voltages required to operate the device are generated internally by the DC-DC
converters. This scheme supports wide-voltage operation from 2.1 to 3.6 V and is thus the most common
mode for the device.
5.4.2
Preregulated 1.85V
The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at pins 10, 25,
33, 36, 37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V
supply. This mode provides the lowest BOM count version in which inductors used for PA DC-DC and
ANA1 DC-DC (2.2 and 1 µH) and a capacitor (22 µF) can be avoided.
In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following
characteristics:
• Load current capacity ≥900 mA
• Line and load regulation with <2% ripple with 500-mA step current and settling time of < 4 µs with the
load step
NOTE
The regulator must be placed as close as possible to the device so that the IR drop to the
device is very low.
36
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5.5
SWAS034 – FEBRUARY 2017
Low-Power Operating Modes
This section describes the low-power modes supported by the device to optimize battery life.
5.5.1
Low-Power Deep Sleep
The low-power deep-sleep (LPDS) mode is an energy-efficient and transparent sleep mode that is entered
automatically during periods of inactivity based on internal power optimization algorithms. The device can
wake up in less than 3 ms from the internal timer or from any incoming host command. Typical battery
drain in this mode is 115 µA. During LPDS mode, the device retains the software state and certain
configuration information. The operation is transparent to the external host; thus, no additional handshake
is required to enter or exit LPDS mode.
5.5.2
Hibernate
The hibernate mode is the lowest power mode in which all of the digital logic is power-gated. Only a small
section of the logic powered directly by the main input supply is retained. The RTC is kept running and the
device wakes up once the nHIB line is asserted by the host driver. The wake-up time is longer than LPDS
mode at approximately 50 ms.
NOTE
Wake-up time can be extended depending on the service-pack size.
5.5.3
Shutdown
The shutdown mode is the lowest power-mode system-wise. All device logics are off, including the realtime clock (RTC). The wake-up time in this mode is longer than hibernate at approximately 1.1 s.
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5.6
5.6.1
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Memory
External Memory Requirements
The CC3120R device maintains a proprietary file system on the sFLASH. The CC3120R file system stores
the service pack file, system files, configuration files, certificate files, web page files, and user files. By
using a format command through the API, users can provide the total size allocated for the file system.
The starting address of the file system cannot be set and is always at the beginning of the sFLASH. The
applications microcontroller must access the sFLASH memory area allocated to the file system directly
through the CC3120R file system. The applications microcontroller must not access the sFLASH memory
area directly.
The file system manages the allocation of sFLASH blocks for stored files according to download order,
which means that the location of a specific file is not fixed in all systems. Files are stored on sFLASH
using human-readable filenames rather than file IDs. The file system API works using plain text, and file
encryption and decryption is invisible to the user. Encrypted files can be accessed only through the file
system.
All file types can have a maximum of 100 supported files in the file system. All files are stored in 4-KB
blocks and thus use a minimum of 4KB of flash space. Fail-safe files require twice the original size and
use a minimum of 8KB. Encrypted files are counted as fail-safe in terms of space. The maximum file size
is 1MB.
Table 5-2 lists the minimum required memory consumption under the following assumptions:
• System files in use consume 64 blocks (256KB).
• Vendor files are not taken into account.
• Gang image:
– Storage for the gang image is rounded up to 32 blocks (meaning 128-KB resolution).
– Gang image size depends on the actual content size of all components. Additionally, the image
should be 128-KB aligned so unaligned memory is considered lost. Service pack, system files, and
the 128-KB aligned memory are assumed to occupy 256KB.
• All calculations consider that the restore-to-default is enabled.
Table 5-2. Title
ITEM
CC3120 [KB]
File system allocation table
20
System and configuration files
256
Service Pack
264
Gang image size
256
Total
796
Minimal flash size
8MBit
Recommended flash size
16MBit
space
NOTE
The maximum supported sFLASH size is 32MB (256Mb). Please refer to Using Serial Flash
on CC3120/CC3220 SimpleLink™ Wi-Fi® and Internet-of-Things Devices.
38
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5.7
SWAS034 – FEBRUARY 2017
Restoring Factory Default Configuration
The device has an internal recovery mechanism that allows rolling back the file system to its predefined
factory image or restoring the factory default parameters of the device. The factory image is kept in a
separate sector on the sFLASH in a secure manner and cannot be accessed from the host processor. The
following restore modes are supported:
• None—no factory restore settings
• Enable restore of factory default parameters
• Enable restore of factory image and factory default parameters
The restore process is performed by pulling or forcing SOP[2:0] = 110 pins and toggling the nRESET pin
from low to high.
The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The
restore process typically takes about 8 seconds, depending on the attributes of the serial flash vendor.
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6 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
6.1
6.1.1
40
Application Information
Typical Application—CC3120R Wide-Voltage Mode
Applications, Implementation, and Layout
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Figure 6-1 shows the typical application schematic using the CC3120R device in the wide-voltage mode of operation. For a full operation reference
design, refer to the BoosterPack that uses the CC3120R device (see CC3120 SimpleLink™ and Internet of Things Hardware Design Files).
Antenna match. Pi
network might be
required depending on
type of antenna.
1
IN
OUT
3
50 Ohm
VBAT_CC
GND
GND
2
L1
FL1
VBAT_CC
E1
1
Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak currents.
3.3nH
2
4
C1
0.5pF GNDGND
VBAT_CC
#37
#39
#44
#54
#10
GND
GND
U1
VBAT_CC
C3
100µF
GND
C4
4.7µF
GND
C5
4.7µF
GND
C6
4.7µF
GND
GND
GND
8
C8
0.1µF
C7
0.1µF
R1
10k
1
6
5
2
3
7
C9
0.1µF
GND
R2
100k
GND
VDD_ANA
C12
1µF
VBAT_CC
GND
C13
C14
GND
GND
VDD_ANA1
VDD_ANA2
VDD_PA_IN
VDD_DIG1
VDD_DIG2
VDD_PLL
VDD_RAM
RF_BG
FLASH_SPI_CLK
FLASH _SPI_CS
FLASH _SPI_MISO
FLASH_SPI_MOSI
C16
0.1µF
0.1µF
0.1µF
GND
C15
0.1µF
37
39
44
10
54
GND
UART1_CTS
UART1_RTS
UART1_TX
UART1_RX
VIN_DCDC_ANA
VIN_DCDC_PA
VIN_DCDC_DIG
VIN_IO1
VIN_IO2
L2
38
2.2uH
36
25
C17
10µF
L3
C19
0.1µF
C18
0.1µF
PA_SWP
PA_SWN
VDD_PA
40
41
42
TEST_58
TEST_59
TEST_60
TEST_62
DCDC_ANA_SW
GND
GND
C20
22µF
GND
C23
43
C21
22µF
GND
C22
10µF
2.2uH
11
14
13
12
RTC_XTAL_P
TP1
TP2
TP3
TP4
NC
DCDC_DIG_SW
HOST_SPI_CLK
HOST_SPI_CS
HOST_SPI_MISO
HOST_SPI_MOSI
HOST_INTR
HIB
R62 is needed only if
UART is used as host
interface.
R5
100k
4
CC_SPI_CLK
CC_SPI_CS
CC_SPI_DOUT
CC_SPI_DIN
CC_IRQ
CC_nHIB
5
8
7
6
15
2
52
RTC_XTAL_N
WLAN_XTAL_P
23
RTC_XTAL_P
WLAN_XTAL_N
22
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
16
17
18
20
26
27
28
53
63
64
1
10pF
SOP0
SOP1
SOP2/TCXO_EN
J1
1
3
5
32
3
19
29
30
VBAT_CC
R9
100k
Flash Programming / Host
Control
GND
DCDC_PA_SW_P
DCDC_PA_SW_N
DCDC_PA_OUT
DCDC_ANA2_SW_P
DCDC_ANA2_SW_N
51
VBAT_CC
R12
100k
CC_UART1_CTS
CC_UART1_RTS
CC_UART1_TX
CC_UART1_RX
CC_WLRS232_TX
CC_WLRS232_RX
CC_WL_UART_TX
CC_NWP_UART_TX
58
59
60
62
45
46
35
34
21
2
4
6
R4
100k
CC_SPI_CLK
CC_SPI_CS
CC_SPI_DOUT
CC_SPI_DIN
CC_IRQ
CC_nHIB
HOST INTERFACE
(Ensure the nHIB line does
not float at any time.)
R6
Y1
32.768kHz
C24
R3
100k
GND
CC_UART1_CTS
CC_UART1_RTS
CC_UART1_TX
CC_UART1_RX
61
50
55
57
R10
100k
RESET
RESERVED
RESERVED
RESERVED
RESERVED
PAD
100k
WLAN_XTAL_N
GND
GND
C25
6.2pF
Y2
40 MHz
C26
6.2pF
65
GND
CC3120RNMARGKR
R11
2.7K
R7
100k
WLAN_XTAL_P
2
GND
SFL_CLK
SFL_CS
SFL_MISO
SFL_MOSI
GND
RTC_XTAL_N
10pF
VBAT_CC
31
LDO_IN1
LDO_IN2
L4
GND
4
1
3
GND
GND
2
4
GND
48
47
33
9
56
24
VDD_PLL
VDD_RAM 49
VDD_PA
VDD_DIG_CC
C11
0.1µF
CS
SCLK
SI/SIO0
SO/SIO1
WP/SIO2
RESET/SIO3
U2
VDD_FL
C10
10µF
VCC
G
G
C2
100µF
GND
GND
GND
GND
R13
100k
C27
0.1µF
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 6-1. CC3120R Wide-Voltage Mode Application
Applications, Implementation, and Layout
Copyright © 2017, Texas Instruments Incorporated
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SWAS034 – FEBRUARY 2017
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Table 6-1 lists the bill of materials for an application using the CC3120R device in wide-voltage mode.
Table 6-1. Bill of Materials for CC3120R in Wide-Voltage Mode
QUANTITY
PART REFERENCE
VALUE
MANUFACTURER
PART NUMBER
DESCRIPTION
1
C1
0.5 pF
Murata
GRM1555C1HR50BA01D
CAP, CERM, 0.5 pF, 50 V, ±20%, C0G/NP0, 0402
2
C2, C3
100 µF
Taiyo Yuden
LMK325ABJ107MMHT
CAP, CERM, 100 µF, 10 V, ±20%, X5R, AEC-Q200 Grade 3,
1210
3
C4, C5, C6
4.7 µF
TDK
C1005X5R0J475M050BC
CAP, CERM, 4.7 µF, 6.3 V, ±20%, X5R, 0402
11
C7, C8, C9, C11, C13,
C14, C15, C16, C18, C19, 0.1 µF
C27
TDK
C1005X5R1A104K050BA
CAP, CERM, 0.1 µF, 10 V, ±10%, X5R, 0402
3
C10, C17, C22
10 µF
Murata
GRM188R60J106ME47D
CAP, CERM, 10 µF, 6.3 V, ±20%, X5R, 0603
1
C12
1 µF
TDK
C1005X5R1A105K050BB
CAP, CERM, 1 µF, 10 V, ±10%, X5R, 0402
2
C20, C21
22 µF
TDK
C1608X5R0G226M080AA
CAP, CERM, 22 µF, 4 V, ±20%, X5R, 0603
2
C23, C24
10 pF
Johanson Technology
500R07S100JV4T
CAP, CERM, 10 pF, 50 V, ±5%, C0G/NP0, 0402
2
C25, C26
6.2 pF
Murata
GRM1555C1H6R2CA01D
CAP, CERM, 6.2 pF, 50 V, ±5%, C0G/NP0, 0402
1
E1
2.45-GHz Ant
Taiyo Yuden
AH316M245001-T
ANT Bluetooth W-LAN ZIGBEE WIMAX, SMD
1
FL1
1.02 dB
TDK
DEA202450BT-1294C1-H
Multilayer Chip Band Pass Filter For 2.4GHz WLAN/Bluetooth, SMD
1
L1
3.3 nH
Murata
LQG15HS3N3S02D
Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A, 0.17 ohm, SMD
2
L2, L4
2.2 uH
Murata
LQM2HPN2R2MG0L
Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08 ohm, SMD
1
L3
1 uH
Murata
LQM2HPN1R0MG0L
Inductor, Multilayer, Ferrite, 1 µH, 1.6 A, 0.055 ohm, SMD
1
R1
10 k
Vishay-Dale
CRCW040210K0JNED
RES, 10 k, 5%, 0.063 W, 0402
1
R11
2.7 k
Vishay-Dale
CRCW04022K70JNED
RES, 2.7 k, 5%, 0.063 W, 0402
10
R2, R3, R4, R5, R6, R7,
R9, R10, R12, R13
100 k
Vishay-Dale
CRCW0402100KJNED
RES, 100 k, 5%, 0.063 W, 0402
1
U1
MX25R
Macronix International
MX25R1635FM1IL0
ULTRA LOW POWER, 16M-BIT [x 1/x 2/x 4] CMOS
MXSMIO(SERIAL MULTI I/O) FLASH MEMORY, SOP-8
1
U2
CC3120
Texas Instruments
CC3120RNMRGK
SimpleLink Wi-Fi Network Processor, Internet-of-Things
Solution for MCU Applications, RGK0064B
1
Y1
Crystal
Abracon Corporation
ABS07-32.768KHZ-9-T
CRYSTAL, 32.768KHZ, 9PF, SMD
1
Y2
Crystal
Epson
Q24FA20H0039600
Crystal, 40MHz, 8pF, SMD
42
Applications, Implementation, and Layout
Copyright © 2017, Texas Instruments Incorporated
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6.1.2
SWAS034 – FEBRUARY 2017
Typical Application Schematic—CC3120R Preregulated, 1.85-V Mode
Figure 6-2 shows the typical application schematic using the CC3120R in preregulated, 1.85-V mode of operation. For addition information on this
mode of operation please contact your TI representative.
Antenna match. Pi
network might be
required depending on
type of antenna.
1.85V
1
IN
OUT
3
GND
GND
2
4
50 Ohm
1.85V
2
E1
L1
FL1
1
Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak currents.
3.3nH
C1
0.5pF
GNDGND
1.85V
1.85V
#37
#39
#44
#54
#10
GND
GND
U1
C2
100µF
C10
10µF
C3
100µF
GND
C4
4.7µF
GND
C5
4.7µF
GND
C6
4.7µF
GND
C8
0.1µF
C7
0.1µF
GND
GND
R1
10k
C9
0.1µF
GND
R2
100k
8
VCC
1
6
5
2
3
7
CS
SCLK
SI/SIO0
SO/SIO1
WP/SIO2
RESET/SIO3
GND
GND
GND
4
U2
1.85V
C11
0.1µF
GND
C13
C12
C14
C15
22µF
1µF
0.1µF
0.1µF
GND
GND
C16
0.1µF
GND
48
47
33
9
56
24
49
VDD_ANA1
VDD_ANA2
VDD_PA_IN
VDD_DIG1
VDD_DIG2
VDD_PLL
VDD_RAM
37
39
44
10
54
VIN_DCDC_ANA
VIN_DCDC_PA
VIN_DCDC_DIG
VIN_IO1
VIN_IO2
38
DCDC_ANA_SW
36
25
LDO_IN1
LDO_IN2
40
41
42
DCDC_PA_SW_P
DCDC_PA_SW_N
DCDC_PA_OUT
43
DCDC_DIG_ SW
45
46
DCDC_ANA2_SW_P
DCDC_ANA2_SW_N
VBA T_CC
GND
C17
0.1µF
L2
GND
GND
C18
0.1µF
C21
C19
C20
10µF
0.1µF
2.2uH
RF_BG
31
FLASH_SPI_CLK
FLASH _SPI_CS
FLASH _SPI_MISO
FLASH_SPI_MOSI
11
14
13
12
UART1_CTS
UART1_RTS
UART1_TX
UART1_RX
61
50
55
57
TEST_58
TEST_59
TEST_60
TEST_62
58
59
60
62
1.85V
SFL_CLK
SFL_CS
SFL_MISO
SFL_MOSI
GND
R3
100k
R4
100k
CC_UART1_CTS
CC_UART1_RTS
CC_UART1_TX
CC_UART1_RX
CC_UART1_CTS
CC_UART1_RTS
CC_UART1_TX
CC_UART1_RX
CC_WLRS232_TX
CC_WLRS232_RX
CC_WL_UART_TX
CC_NWP_UART_TX
TP1
TP2
TP3
TP4
R62 is needed only if
UART is used as host
interface.
R5
100k
GND
NC
HOST_SPI_CLK
HOST_SPI_CS
HOST_SPI_MISO
HOST_SPI_MOSI
HOST_INTR
HIB
4
5
8
7
6
15
2
CC_SPI_CLK
CC_SPI_CS
CC_SPI_DOUT
CC_SPI_DIN
CC_IRQ
CC_nHIB
CC_SPI_CLK
CC_SPI_CS
CC_SPI_DOUT
CC_SPI_DIN
CC_IRQ
CC_nHIB
(Ensure the nHIB line does
not float at any time.)
GND
52
WLAN_XTAL_P
RTC_XTAL_P
WLAN_XTAL_N
22
35
34
21
SOP0
SOP1
SOP2/TCXO_EN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
16
17
18
20
26
27
28
53
63
64
PAD
65
10pF
VBAT_CC
J1
2
4
6
32
1
3
5
1.85V
R8
100k
R9
100k
3
19
29
30
R10
2.7K
RESET
RESERVED
RESERVED
RESERVED
RESERVED
R7
100k
23
RTC_XTAL_N
51
100k
GND
GND
1
3
GND
C23
6.2pF
Y2
40 MHz
G
G
GND
C24
6.2pF
2
4
Y1
32.768kHz
1
C22
HOST INTERFACE
R6
2
10pF
GND
Flash Programming / Host
Control
GND
CC3120RNMARGKR
GND
GND
R11
100k
GND
R12
100k
GND
C25
0.1µF
GND
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 6-2. CC3120R Preregulated 1.85-V Mode Application Circuit
Applications, Implementation, and Layout
Copyright © 2017, Texas Instruments Incorporated
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SWAS034 – FEBRUARY 2017
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Table 6-2 lists the bill of materials for an application using the CC3120R device in preregulated 1.85-V mode.
Table 6-2. Bill of Materials for CC3120R in Preregulated, 1.85-V Mode
QUANTITY
DESIGNATOR
VALUE
MANUFACTURER
PART NUMBER
DESCRIPTION
1
U1
MX25R
Macronix International Co., LTD
MX25R1635FM1IL0
ULTRA LOW POWER, 16M-BIT [x 1/x 2/x 4]
CMOS MXSMIO(SERIAL MULTI I/O) FLASH
MEMORY, SOP-8
1
U2
CC3120
Texas Instruments
CC3120RNMRGK
SimpleLink Wi-Fi Network Processor, Internetof-Things Solution for MCU Applications,
RGK0064B
1
R10
2.7 k
Vishay-Dale
CRCW04022K70JNED
RES, 2.7 k, 5%, 0.063 W, 0402
10
R2, R3, R4, R5, R6, R7, R8,
R9, R11, R12
100 k
Vishay-Dale
CRCW0402100KJNED
1
R1
10 k
Vishay-Dale
CRCW040210K0JNED
RES, 10 k, 5%, 0.063 W, 0402
1
FL1
1.02 dB
TDK
DEA202450BT-1294C1-H
Multilayer Chip Band Pass Filter For 2.4-GHz
W-LAN/Bluetooth, SMD
1
L2
2.2 µH
MuRata
LQM2HPN2R2MG0L
Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08
ohm, SMD
1
L1
3.3 nH
MuRata
LQG15HS3N3S02D
Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A,
0.17 Ω, SMD
1
Y1
Crystal
Abracon Corportation
ABS07-32.768KHZ-9-T
CRYSTAL, 32.768 kHz, 9 pF, SMD
1
Y2
Crystal
Epson
Q24FA20H0039600
Crystal, 40 MHz, 8 pF, SMD
2
C2, C3
100 µF
Taiyo Yuden
LMK325ABJ107MMHT
CAP, CERM, 100 µF, 10 V, ±20%, X5R, AECQ200 Grade 3, 1210
1
C13
22 µF
TDK
C1608X5R0G226M080AA
CAP, CERM, 22 µF, 4 V, ±20%, X5R, 0603
2
C10, C20
10 µF
MuRata
GRM188R60J106ME47D
CAP, CERM, 10 µF, 6.3 V, ±20%, X5R, 0603
2
C21, C22
10 pF
Johanson Technology
500R07S100JV4T
CAP, CERM, 10 pF, 50 V, ±5%, C0G/NP0,
0402
2
C23, C24
6.2 pF
MuRata
GRM1555C1H6R2CA01D
CAP, CERM, 6.2 pF, 50 V, ±5%, C0G/NP0,
0402
3
C4, C5, C6
4.7 µF
TDK
C1005X5R0J475M050BC
CAP, CERM, 4.7 µF, 6.3 V, ±20%, X5R, 0402
1
C12
1 µF
TDK
C1005X5R1A105K050BB
CAP, CERM, 1 µF, 10 V, ±10%, X5R, 0402
1
C1
0.5 pF
MuRata
GRM1555C1HR50BA01D
CAP, CERM, 0.5 pF, 50 V, ±20%, C0G/NP0,
0402
11
C7, C8, C9, C11, C14, C15,
C16, C17, C18, C19, C25
0.1 µF
TDK
C1005X5R1A104K050BA
1
E1
2.45-Ghz Ant
Taiyo Yuden
AH316M245001-T
44
Applications, Implementation, and Layout
RES, 100 k, 5%, 0.063 W, 0402
CAP, CERM, 0.1 µF, 10 V, ±10%, X5R, 0402
ANT BLUETOOTH W-LAN ZIGBEE WIMAX,
SMD
Copyright © 2017, Texas Instruments Incorporated
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6.2
SWAS034 – FEBRUARY 2017
PCB Layout Guidelines
This section details the PCB guidelines to speed up the PCB design using the CC3120R VQFN device.
Follow these guidelines ensures that the design will minimize the risk with regulatory certifications
including FCC, ETSI, and CE. For more information, see CC3120 and CC3220 SimpleLink™ Wi-Fi® and
IoT Solution Layout Guidelines.
6.2.1
General PCB Guidelines
Use the following PCB guidelines:
• Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended
layers for signals and ground.
• Ensure that the QFN PCB footprint follows the information in Section 8.
• Ensure that the QFN PCB GND and solder paste follow the recommendations provided in CC3120 and
CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.
• Decoupling capacitors must be as close as possible to the QFN device.
6.2.2
Power Layout and Routing
Three critical DC-DC converters must be considered for the CC3120R device.
• Analog DC-DC converter
• PA DC-DC converter
• Digital DC-DC converter
Each converter requires an external inductor and capacitor that must be laid out with care. DC current
loops are formed when laying out the power components.
6.2.2.1
Design Considerations
The following design guidelines must be followed when laying out the CC3120R device:
• Route all of the input decoupling capacitors (C11, C13, and C18) on L2 using thick traces, to isolate
the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask
specifications.
• Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power
amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).
• Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
• Place all decoupling capacitors as close to the respective pins as possible.
• Power budget: The CC3120R device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, and 700
mA for 1.85 V, for 24 ms during the calibration cycle.
• Ensure the power supply is designed to source this current without any issues. The complete
calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
• The CC3120R device contains many high-current input pins. Ensure the trace feeding these pins is
capable of handling the following currents:
– PA DCDC input (pin 39) maximum 1 A
– ANA DCDC input (pin 37) maximum 600 mA
– DIG DCDC input (pin 44) maximum 500 mA
– PA DCDC switching nodes (pin 40 and pin 41) maximum 1 A
– PA DCDC output node (pin 42) maximum 1 A
– ANA DCDC switching node (pin 38) maximum 600 mA
– DIG DCDC switching node (pin 43) maximum 500 mA
– PA supply (pin 33) maximum 500 mA
Applications, Implementation, and Layout
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Figure 6-3 shows the ground routing for the input decoupling capacitors.
Figure 6-3. Ground Routing for the Input Decoupling Capacitors
The ground return for the input capacitors are routed on L2 to reduce the EMI and improve the spectral
mask. This routing must be strictly followed because it is critical for the overall performance of the device.
6.2.3
Clock Interfaces
The following guidelines are for the slow clock.
• The 32.768-kHz crystal must be placed close to the QFN package.
• Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance
is within ±150 ppm.
• The ground plane on layer two is solid below the trace lanes and there is ground around these traces
on the top layer.
The following guidelines are for the fast clock.
• The 40-MHz crystal must be placed close to the QFN package.
• Ensure that he load capacitance is tuned according to the board parasitics to the frequency tolerance
is within ±100 ppm at room temperature. The total frequency across parts, temperature, and with
aging, must be ±25 ppm to meet the WLAN specification.
• Ensure that no high-frequency lines are routed close to the XTAL routing to avoid noise degradation.
• Ensure that crystal tuning capacitors are close to the crystal pads.
• Make both traces (XTALM and XTALP) as close to parallel as possible and approximately the same
length.
• The ground plane on layer two is solid below the trace lines and that there is ground around these
traces on the top layer.
• See CC31xx & CC32xx Frequency Tuning for frequency tuning.
46
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6.2.4
SWAS034 – FEBRUARY 2017
Digital Input and Output
The following guidelines are for the digital I/O.
• Route SPI and UART lines away from any RF traces.
• Keep the length of the high-speed lines as short as possible to avoid transmission line effects.
• Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects. This is
required if the traces cannot be kept short. Place the resistor at the source end, closer to the device
that is driving the signal.
• Add series-terminating resistor for each high-speed line (such as SPI_CLK or SPI_DATA) to match the
driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line
impedance.
• Route high-speed lines with a ground reference plane continuously below it to offer good impedance
throughout. This routing also helps shield the trace against EMI.
• Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple
locations, use a separate line driver for each line.
• If the lines are longer compared to the rise time, add series-terminating resistors near the driver for
each high-speed line to match the driver impedance to the line. Typical terminating-resistor values
range from 27 to 36 Ω for a 50-Ω line impedance.
6.2.5
RF Interface
The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific
antenna design guides (including placement of the antenna). Also see CC3120 and CC3220 SimpleLink™
Wi-Fi® and IoT Solution Layout Guidelines for general antenna guidelines.
• Ensure that the antenna is matched for 50-Ω. A Pi-matching network is recommended.
• Ensure that the area underneath the BPF pads are grounded on layer one and layer two, and that the
minimum fulter requirements are met.
• Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.
• The RF trace bends must be made with gradual curves, and 90-degree bends must be avoided.
• The RF traces must not have sharp corners.
• There must be no traces or ground under the antenna section.
• The RF traces must have via stitching on the ground plane beside the RF trace on both sides.
Applications, Implementation, and Layout
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7 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions are listed in this section.
7.1
Tools and Software
Development Tools
SimpleLink Studio for CC3120R The CC3120R device is supported.
SimpleLink Studio for CC3120R is a Windows®-based software tool used to aid in the
development of embedded networking applications and software for microcontrollers. Using
SimpleLink Studio for CC3120R, embedded software developers can develop and test
applications using any desktop IDE, such as Visual Studio or Eclipse, and connect their
applications to the cloud using the CC3120R BoosterPack™ Plug-in Module. The application
can then be easily ported to any microcontroller. With the SimpleLink Wi-Fi CC3120R
solution, customers now have the flexibility to add Wi-Fi to any microcontroller (MCU). This
Internet-on-a-chip solution contains all you need to easily create IoT solutions: security, quick
connection, cloud support, and more. For more information on CC3120R, visit SimpleLink
Wi-Fi Solutions.
CC3120R Software Development Kit (SDK) The CC3120R device is supported.
The SimpleLink Wi-Fi CC3220 SDK contains drivers for the CC3220 programmable MCU,
30+ sample applications, and documentation needed to use the solution. The SDK also
contains the flash programmer, a command line tool for flashing software, configuring
network and software parameters (SSID, access point channel, network profile, and so on),
system files, and user files (certificates, web pages, and so on). This SDK can be used with
TI’s SimpleLInk Wi-Fi CC3220 LaunchPad™ development kit.
The SDK has a variety of support offerings. All sample applications in the SDK are
supported on the integrated Cortex-M4 processor with CCS IDE and no RTOS. In addition, a
few of the applications support IAR, Free RTOS, and TI-RTOS.
TI Designs and Reference Designs
The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jumpstart your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
48
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7.2
SWAS034 – FEBRUARY 2017
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the
CC3120R device and support tools (see Figure 7-1).
X CC
3 1 20 R
N M
x
RGK
R/T
PACKAGING
R = tape/reel
T = small reel
PREFIX
X = perproduction device
no prefix = production device
PACKAGE
RGK = 9-mm x 9-mm VQFN
DEVICE FAMILY
CC = wireless connectivity
REVISION
A = Revision A
SERIES NUMBER
3 = Wi-Fi Centric
No Memory
Figure 7-1. CC3120R Device Nomenclature
7.3
Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (CC3120). In the upper right corner, click the "Alert me" button. This registers you to
receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document. The current documentation that describes the processor, related
peripherals, and other technical collateral follows.
The following documents provide support for the CC3120 device.
Application Reports
SimpleLink™ CC3120, CC3220 Wi-Fi® Internet-on-a chip™ Networking Sub-System Power
Management
This application report describes the best practices for power management and extended
battery life for embedded low-power Wi-Fi devices such as the SimpleLink Wi-Fi Internet-ona chip™ solution from Texas Instruments™.
SimpleLink™ CC3120, CC3220 Wi-Fi® Internet-on-a chip™ Solution Built-In Security Features The
SimpleLink Wi-Fi CC3120 and CC3220 Internet-on-a chip™ family of devices from Texas
Instruments™ offer a wide range of built-in security features to help developers address a
variety of security needs, which is achieved without any processing burden on the main
microcontroller (MCU). This document describes these security-related features and provides
recommendations for leveraging each in the context of practical system implementation.
SimpleLink™ CC3120, CC3220 Wi-Fi® and Internet of Things Over-the-Air Update This document
describes the OTA library for the SimpleLink™ Wi-Fi® CC3x20 family of devices from Texas
Instruments™ and explains how to prepare a new cloud-ready update to be downloaded by
the OTA library.
SimpleLink™ CC3120, CC3220 Wi-Fi® Internet-on-a chip™ Solution Device Provisioning This guide
describes the provisioning process, which provides the SimpleLink Wi-Fi device with the
information (network name, password, and so forth) needed to connect to a wireless
network.
Using Serial Flash on SimpleLink™ CC3120 and CC3220 Wi-Fi® and Internet-of-Things Devices
This application note is divided into two parts. The first part provides important guidelines
and best- practice design techniques to consider when choosing and embedding a serial
flash paired with the CC3120 and CC3220 (CC3x20) devices. The second part describes the
file system, along with guidelines and considerations for system designers working with the
CC3x20 devices.
Device and Documentation Support
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User's Guides
SimpleLink™ Wi-Fi® and Internet of Things CC3120 and CC3220 Network Processor This document
provides software (SW) programmers with all of the required knowledge for working with the
networking subsystem of the SimpleLink Wi-Fi devices. This guide provides basic guidelines
for writing robust, optimized networking host applications, and describes the capabilities of
the networking subsystem. The guide contains some example code snapshots, to give users
an idea of how to work with the host driver. More comprehensive code examples can be
found in the formal software development kit (SDK). This guide does not provide a detailed
description of the host driver APIs.
SimpleLink™ Wi-Fi® CC3120 BoosterPack™ Plug-In Module and IoT Solution The SimpleLink Wi-Fi
CC3120 wireless network processor from Texas Instruments™ provides users the flexibility
to add Wi-Fi to any MCU. This user's guide explains the various configurations of the
CC3120 BoosterPack™ Plug-In Module.
SimpleLink™ Wi-Fi® CC3120 and CC3220 and IoT Solution Layout Guidelines This
document
provides the design guidelines of the 4-layer PCB used for the CC3120 and CC3220
SimpleLink Wi-Fi family of devices from Texas Instruments™. The CC3120 and CC3220
devices are easy to lay out and are available in quad flat no-leads (QFNS) packages. When
designing the board, follow the suggestions in this document to optimize performance of the
board.
SimpleLink™ Wi-Fi® CC3120 Internet-on-a-chip™ Solution SDK This guide is intended to help users in
the initial setup and demonstration of the different demos in the CC3120 SDK. The guide
lists the software and hardware components required to get started, and explains how to
install the supported integrated development environment (IDE), SimpleLink CC3120 SDK,
and the various other tools required.
SimpleLink™ Wi-Fi® and Internet-on-a-chip™ CC3120 and CC3220 Solution Radio Tool The Radio
Tool serves as a control panel for direct access to the radio, and can be used for both the
radio frequency (RF) evaluation and for certification purposes. This guide describes how to
have the tool work seamlessly on Texas Instruments ™ evaluation platforms such as the
BoosterPack™ plus FTDI emulation board for CC3120 devices, and the LaunchPad™ for
CC3220 devices.
SimpleLink™ Wi-Fi® CC3120 and CC3220 Provisioning for Mobile Applications This guide describes
TI’s SimpleLink™ Wi-Fi® provisioning solution for mobile applications, specifically on the
usage of the Android™ and iOS® building blocks for UI requirements, networking, and
provisioning APIs required for building the mobile application.
More Literature
RemoTI Manifest
CC3120 SimpleLink™ WI-Fi® and Internet of Things CC3120 hardware design files.
7.4
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
50
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7.5
SWAS034 – FEBRUARY 2017
Trademarks
SimpleLink, Internet-on-a chip, SmartConfig, Texas Instruments, E2E, BoosterPack, LaunchPad are
trademarks of Texas Instruments.
Cortex is a registered trademark of ARM Limited.
ARM is a registered trademark of ARM Physical IP, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Windows is a registered trademark of Microsoft Inc.
Wi-Fi, Wi-Fi Direct are registered trademarks of Wi-Fi Alliance.
All other trademarks are the property of their respective owners.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
52
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC3120RNMARGKR
ACTIVE
VQFN
RGK
64
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC3120R
NMA
CC3120RNMARGKT
ACTIVE
VQFN
RGK
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC3120R
NMA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CC3120RNMARGKR
VQFN
RGK
64
2500
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
CC3120RNMARGKT
VQFN
RGK
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC3120RNMARGKR
VQFN
RGK
64
2500
367.0
367.0
38.0
CC3120RNMARGKT
VQFN
RGK
64
250
210.0
185.0
35.0
Pack Materials-Page 2
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reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
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(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
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TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
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represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
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