LD39150xx Ultra low drop BiCMOS voltage regulator Features ■ 1.5 A guaranteed output current ■ Ultra low dropout voltage (200 mV typ. @ 1.5 A load, 40 mV typ. @ 300 mA load) ■ Very low quiescent current (1 mA typ. @ 1.5 A load, 1 µA max @ 25 °C in off mode) DPAK PPAK ■ Logic-controlled electronic shutdown ■ Current and thermal internal limit ■ ± 1.5 % output voltage tolerance @ 25 °C ■ Fixed and ADJ output voltages: 1.22 V, 1.8 V, 2.5 V, 3.3 V, ADJ. (see Table 1) ■ Temperature range: -40 to 125 °C ■ Fast dynamic response to line and load changes Description ■ Stable with ceramic capacitor (see Section 7.1, Section 7.2 and Section 7.3) ■ Available in PPAK, DPAK and DFN6 (3x3 mm) The LD39150xx is a fast ultra low drop linear regulator which operates from 2.5 V to 6 V input supply. Typical application ■ Microprocessor power supply ■ DSPs power supply ■ Post regulators for switching suppliers ■ High efficiency linear regulator Table 1. DFN6 (3x3 mm) A wide range of output options are available. The low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessor and memory applications. The device is developed on a BiCMOS process which allows low quiescent current operation independently of output load current. Device summary Order codes Part numbers DPAK (T&R) LD39150XX12 LD39150DT12-R LD39150XX18 LD39150DT18-R LD39150XX25 LD39150XX33 LD39150XX PPAK (T&R) DFN (1) Output voltages LD39150PU12R 1.22 V LD39150PT18-R LD39150PU18R 1.8 V LD39150DT25-R LD39150PT25-R LD39150PU25R 2.5 V LD39150DT33-R LD39150PT33-R LD39150PU33R 3.3 V LD39150PT-R LD39150PU-R ADJ from 1.22 to 5.0 V 1. Available on request. January 2009 Rev 2 1/19 www.st.com 19 Contents LD39150xx Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 LD39150xx Diagram 1 Diagram Figure 1. Block diagram (*) Not present on ADJ versions. 3/19 Pin configuration LD39150xx 2 Pin configuration Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN) Table 2. DPAK PPAK DFN6 (3x3 mm) Pin description Pin n° SYMBOL DFN 5 NOTE PPAK DPAK 5 VSENSE/N.C. For fixed versions: to be connected with LDO output voltage pins for DFN package and not connected on PPAK ADJ For adjustable version: Error amplifier input pin for VO from 1.22 to 5.0 V 3 2 1 VI LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a distance of not more than 0.5’’ from input pin. 4 4 3 VO LDO output voltage pins, with minimum CO = 2.2 µF needed for stability (also refer to CO vs ESR stability chart) 2 1 1 3 6 4/19 2 VINH Inhibit input voltage: ON MODE when VINH ≥ 2 V, OFF MODE when VINH ≤ 0.3 V (Do not leave floating, not internally pulled down/up) GND Common ground N.C. Not connected LD39150xx 3 Typical application circuits Typical application circuits (CI and CO capacitors must be placed as close as possible to the IC pins) Figure 3. LD39150xx fixed version with inhibit Note: Inhibit pin is not internally pulled down/up then it must not be left floating. Disable the device when connected to GND or to a positive voltage less than 0.3 V. Figure 4. LD39150xx adjustable version VO = VREF (1 + R1/R2) Note: Set R2 as close as possible to 4.7 kΩ 5/19 Typical application circuits Figure 5. LD39150xx DPAK Figure 6. Timing diagram 6/19 LD39150xx LD39150xx Maximum ratings 4 Maximum ratings Table 3. Absolute maximum ratings Symbol Value Unit -0.3 to 6.5 V INHIBIT input voltage -0.3 to VI +0.3 (6.5 V max) V DC output voltage -0.3 to VI +0.3 (6.5 V max) V VADJ ADJ pin voltage -0.3 to VI +0.3 (6.5 V max) V IO Output current Internally limited mA PD Power dissipation Internally limited mW VI VINH VO Parameter DC input voltage TSTG Storage temperature range -50 to 150 °C TOP Operating junction temperature range -40 to 125 °C Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 4. Thermal data Symbol Parameter RthJA Thermal resistance junction-ambient RthJC Thermal resistance junction-case PPAK DPAK DFN (1) Unit 100 100 40 °C/W 8 8 10 °C/W 1. With PCB ground plane heatsink. 7/19 Electrical characteristics LD39150xx 5 Electrical characteristics Table 5. Electrical characteristics (TJ = 25 °C, VI = VO+1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = 2 V, unless otherwise specified) Symbol VI Parameter Parameter Operating input voltage VI = VO+1V, ILOAD = 10mA to 1.5A VO Output voltage tolerance VREF Reference voltage ΔVO Output voltage LINE regulation ΔVO/ΔILOAD Output voltage LOAD regulation VDROP IQ Dropout voltage (VI - VO) VI = VO+1V to 6V, ILOAD = 10mA to 1.5A TJ = -40 to 125°C Min. Typ. Max. Unit 2.5 6 V -1.5 1.5 -3 3 % of VO(NOM) 1.22 V VI = VO+1V to 6V 0.04 % VI = VO+1V to 6V, TJ = -40 to 125°C 0.1 ILOAD = 10mA to 1.5A 0.06 ILOAD = 10mA to 1.5A, TJ = -40 to 125°C 0.2 0.4 ILOAD = 300mA, TJ=-40 to 125°C 40 80 ILOAD = 1.5A, TJ = -40 to 125°C 200 400 1 2.5 0.2 % %/A mV Quiescent current: ON MODE ILOAD = 10mA to 1.5A, VINH = 2V TJ = -40 to 125°C Quiescent current: OFF MODE VINH = 0.3V 1 VINH = 0.3V, TJ = -40 to 125°C 5 mA µA Short circuit protection ISC Short circuit protection RL = 0 3 Inhibit threshold LOW Inhibit threshold HIGH VI = 2.5 to 6V OFF TJ = -40 to 125°C TD-OFF Current limit ILOAD = 1.5A, VO = 3.3V 15 TD-ON Current limit ILOAD = 1.5A, VO = 3.3V 15 Inhibit input current (1) VI = 6V, VINH = 0 to 6V ±0.1 A Inhibit input VINH IINH 0.3 V 2 µs ±1 µA AC parameters SVR eN TSHDN Supply voltage rejection Output noise voltage f = 120Hz 65 f = 1kHz 55 dB BW = 10Hz to 100kHz, CO = 2.2µF, VO = 2.5V 100 Thermal shutdown OFF 170 Hysteresis 10 µVRMS °C 1. Guaranteed by design 8/19 VI = 4.5 ± 1V, VO = 3.3V, ILOAD = 10mA, LD39150xx Typical performance characteristics 6 Typical performance characteristics Figure 7. (TJ = 25 °C, VI = VO + 1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = VI, unless otherwise specified) Output voltage vs temperature Figure 8. Dropout voltage vs temperature Figure 9. Dropout voltage vs output current Figure 11. Quiescent current vs temperature Figure 10. Quiescent current vs supply voltage Figure 12. Quiescent current vs temperature 9/19 Typical performance characteristics LD39150xx Figure 13. Short circuit current vs temperature Figure 14. Output voltage vs input voltage Figure 15. Stability region vs CO & ESR (at 100 Figure 16. Stability region vs CO & low ESR (at kHz) 100 kHz) Figure 17. Load transient Figure 18. Line transient VI = 3.5V, IO = 10mA to 1.5A, CI = 1µF, CO = 2.2µF VI = 3.5V to 5.5V, ILOAD = 10mA, CO = 2.2µF 10/19 LD39150xx Application notes 7 Application notes 7.1 External capacitors The LD39150xx requires external capacitors for regulator stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance (see Figure 15 and Figure 16). The input/output capacitors must be located less than 1cm from the relative pins and connected directly to the input/output ground pins using traces which have no other currents flowing through them. Any good quality of Ceramic or Electrolytic capacitors can be used. 7.2 Input capacitor An input capacitor whose minimum value is 1 µF is required with the LD39150xx (amount of capacitance can be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin of the device and returned to a clean analog ground. Any good quality ceramic, tantalum or film capacitors can be used for this capacitor. 7.3 Output capacitor It is possible to use ceramic or tantalum capacitors but the output capacitor must meet the requirement for minimum amount of capacitance and ESR (equivalent series resistance) value. A minimum capacitance of 2.2 µF is a good choice to guarantee the stability of the regulator. Anyway, other CO values can be used according to the (Figure 15 and Figure 16) showing the allowable ESR range as a function of the output capacitance. This curve represents the stability region over the full temperature and IO range. 7.4 Thermal note The output capacitor must maintain its ESR in the stable region over the full operating temperature range to assure stability. Also, capacitors tolerance and variation with temperature must be kept in consideration in order to assure the minimum amount of capacitance at all times. 7.5 Inhibit input operation The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically reducing the current consumption down to less than 1 µA. When the inhibit feature is not used, this pin must be tied to VI to keep the regulator output ON at all times. To assure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section (VIH VIL). The inhibit pin must not be left floating because it is not internally pulled down/up. 11/19 Package mechanical data 8 LD39150xx Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 12/19 LD39150xx Package mechanical data PPAK mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.4 0.6 0.015 0.023 B2 5.2 5.4 0.204 0.212 0.023 C 0.45 0.6 0.017 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 6.6 0.252 D1 E 5.1 6.4 E1 4.7 e G 0.201 1.27 4.9 0.260 0.185 0.050 5.25 0.193 0.206 G1 2.38 2.7 0.093 0.106 H 9.35 10.1 0.368 0.397 0.039 L2 0.8 L4 0.6 L5 1 L6 1 1 2.8 0.031 0.023 0.039 0.039 0.110 0078180-E 13/19 Package mechanical data LD39150xx DPAK mechanical data mm. inch. Dim. Min. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 Typ. 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 Max. Min. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 6.6 0.252 5.1 6.4 0.260 0.173 0.368 0.039 2.8 0.8 0.181 0.397 0.110 0.031 1 0.023 0.2 0° 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.185 0.090 4.6 10.1 0.6 Max. 0.200 4.7 2.28 4.4 9.35 1 Typ. 0.039 0.008 8° 0° 8° 0068772-F 14/19 LD39150xx Package mechanical data DFN6 (3x3 mm) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0 0.02 0.05 0 0.001 0.002 A3 0.20 0.008 b 0.23 0.30 0.38 0.009 0.012 0.015 D 2.90 3.00 3.10 0.114 0.118 0.122 D2 2.23 2.38 2.48 0.088 0.094 0.098 E 2.90 3.00 3.10 0.114 0.118 0.122 E2 1.50 1.65 1.75 0.059 0.065 0.069 e L 0.95 0.30 0.40 0.037 0.50 0.012 0.016 0.020 7946637A 15/19 Package mechanical data LD39150xx Tape & reel DPAK-PPAK mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 330 13.0 13.2 Max. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 16/19 Max. 0.504 0.512 22.4 0.519 0.882 Ao 6.80 6.90 7.00 0.268 0.272 0.2.76 Bo 10.40 10.50 10.60 0.409 0.413 0.417 Ko 2.55 2.65 2.75 0.100 0.104 0.105 Po 3.9 4.0 4.1 0.153 0.157 0.161 P 7.9 8.0 8.1 0.311 0.315 0.319 LD39150xx Package mechanical data Tape & reel QFNxx/DFNxx (3x3) mechanical data mm. inch. Dim. Min. Typ. A Max. Min. Typ. 180 13.2 7.087 C 12.8 D 20.2 0.795 N 60 2.362 T Max. 0.504 0.519 14.4 0.567 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 17/19 Revision history LD39150xx 9 Revision history Table 6. Document revision history Date Revision 26-Jan-2007 1 Initial release. 12-Jan-2009 2 Removed: package DFN8 (4x4 mm) and added package DFN6 (3x3 mm). 18/19 Changes LD39150xx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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