CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY Power PSoC™ Devices 1.0 Features 1.1 • Configurable Analog Mux, 10:1 or 5:2 Differential • Configurable Digital Blocks — 8- to 16-Bit Timers, Counters, and PWMs — Connectable to All GPIO Pins — Connectable to All High Voltage Output Pins — Single Block Deadband PWM with Kill — Digital Blocks can Drive Outputs to 36V — Complex Peripherals by Combining Blocks Key Features • Extended Operating Voltage of 2.5V to 36V • 2 HV Linear Opamp Control Loops for Driving Power PFETs • 2 HV Switching Control Loops for Driving External PFETs • • • • 2 High Voltage CMOS or Open Drain Outputs 2 High Voltage Analog Sense Inputs 4KB of Flash 256 Bytes of SRAM 1.2 • • • • • 1.3 • • • • • • • Improved Features Very Low Current Mode for 100 nA Sleep (Deep Sleep) Analog Absolute Accuracy (0.75%) Additional Flexibility for Sleep Modes 2 Comparators with DAC References 6- to 12-Bit ADC (20 Ksps at 8 Bits) Applications Battery Chargers (Linear, Switched, or Fly Back) DC-DC Buck and Boost Converters Fan Controllers (Tachometer, Temp. Sense, Current Limit) Motor Drivers (H-Bridge, Hall-Effect Sensors) White LED Drivers Temperature Sensor (Thermistor, Thermocouple) General-Purpose High Voltage Microcontroller 2.0 Block Diagram HVdd LowDrop-Out Regulator ANALOG and HIGH VOLTAGE SECTIONS InternalVdd ODAC0 VDAC0 ODAC1 VBG VDAC1 VDAC1 IBIAS DBC01 GDO1 VDAC0 DBC00 GDO0 VS1 HVO[1] VS0 Analog to Digital Convertor HVDriver P0[7] HVDriver HVO[0] P0[6] P0[3] P0[2] P0[1] Atten1 Vss Vref Vbg P0[4] Temp P0[5] P0[0] Atten0 P1[0] P1[1] IDAC1 AMuxBus3 AMuxBus2 AMuxBus1 AMuxBus0 IDAC0 SYSTEM RESOURCES PSoC CORE SleepandWatchdog COMP0 ODAC1 ACLK ACLK POR andLVD COMP1 ODAC0 LowSpeed Oscillator Internal Voltage Reference M8C CPU PSoC CORE Internal Main Oscillator 4KBFlash Global Digital InterconnectBus System Bus 256BSRAM I2C DBC00 DBC01 DBD02 DBD03 SystemResets DigitalPSoC BlockArray InterruptController 1 DigitalRow Digital Clocks DIGITAL SYSTEM Figure 2-1. Block Diagram Cypress Semiconductor Corporation Document 38-12034 Rev. *C • 198 Champion Court • San Jose, CA 95134 • 408.943.2600 Revised November 17, 2005 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 3.0 Complete Feature List • Extended Operating Voltage of 2.5V to 36V • Powerful Harvard Architecture Processor — M8C Processor Speeds to 24 MHz — Low Power at High Speed — Industrial Temperature Range: -40°C to +85°C • Additional Flexibility for Sleep Modes — Select when System Resources are Shut Down — Very Low Current Mode for 100 nA Sleep (Deep Sleep) • 2 Advanced Power PSoC Blocks — 2 High Voltage Analog Sense Inputs — 2 High Voltage Linear Opamp Control Loops for Driving Power PFETs — 2 High Voltage Switching Control Loops for Driving External PFETs — 2 High Voltage CMOS or Open Drain Outputs • Advanced Analog Blocks — Analog Absolute Accuracy (0.75%) — 2 Comparators with DAC References — 6- to 12-Bit ADC (20 Ksps at 8 Bits) — Configurable Analog Mux, 10:1 or 5:2 Differential • 4 Advanced Digital Blocks (2 with Integrated Deadband) — 8- to 16-Bit Timers, Counters, and PWMs — Connectable to All GPIO Pins — Connectable to All High Voltage Output (HVO) Pins — Single Block Deadband PWM with Kill — Digital Blocks can Drive Outputs to 36V — Complex Peripherals by Combining Blocks • Flexible On-Chip Memory — 4KB Flash Program Storage 50,000 Erase/Write Cycles — 256 Bytes SRAM — In-System Serial Programming (ISSP™) — Partial Flash Updates (64-Byte Blocks) — Flexible Protection Modes — EEPROM Emulation in Flash • Precision, Programmable Clocking • Development Tools — Free Development Software (PSoC™ Designer) — Full-Featured, In-Circuit Emulator and Programmer — Full Speed Emulation — Complex Breakpoint Structure — 128KB Trace Memory — Free Application Generation Software (PSoC Express™) • Additional System Resources — I2C™ Master, Slave, and Multi-Master to 400 kHz — Watchdog and Sleep Timers — User-Configurable Low Voltage Detection — Integrated Supervisory Circuit — On-Chip Precision Voltage Reference — 4-Bit Current References Document 38-12034 Rev. *C 4.0 PSoC Functional Overview The key feature set of the Power PSoC family is the ability to be powered from and connect to voltages above the standard 5V logic voltage used by most microcontrollers. The Power PSoC's HVdd pin can connect to a supply voltage of up to 36V. Internally, an LDO regulator converts the supply voltage to 5V for powering the analog system, digital system, the core, and the GPIO. High voltage signals can be connected to the analog circuitry through one of two selectable attenuators, each having three ranges. These precision dividers reduce the external analog voltage by a factor of 4, 8, or 16. This allows single-ended or differential signals with up to 36V common mode to be measured with the ADC. The GPIO pins are not high-voltage tolerant. Signals with voltages exceeding VGPIO (as shown in the Absolute Maximum Ratings table, Table 8.2) cannot be connected to the GPIO pins (P0 [7:0] and P1 [1:0]). Doing so will damage the device. The Power PSoC family consists of several Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low-cost single-chip programmable component. A Power PSoC device includes configurable analog, digital, and power blocks, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture, as illustrated in Figure 2-1, is comprised of five main areas: the Core, the System Resources, the Digital System, the Analog System, and the Power Control System. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each PSoC device includes 4 digital blocks, up to 2 digital high voltage outputs, and up to 10 general purpose IO (GPIO). The GPIO provide access to the global digital and analog interconnects. 4.1 Power PSoC Core The Power PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low-speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such as digital clocks for increased flexibility of the PSoC mixed-signal arrays; I2C functionality for implementing master, slave, and multi-master; an internal voltage reference of 1.3V for a number of analog PSoC subsystems; and various system resets supported by the M8C. Page 2 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY Digital System The digital blocks can be connected to any GPIO (or digital high voltage output) through a set of global buses that can route any signal to any pin. The buses also allow signal multiplexing and the combining of signals through logic operations. This configurability frees designs from the constraints of a fixed peripheral controller. 4.3 • Analog-to-digital converters (up to 12-bit resolution with single-ended or differential inputs). • Adjustable input gain of 1/4, 1, 4, or 16 for the ADC. • Pin-to-pin comparator with low power mode for operation during sleep. • Single-ended or differential comparators (up to 2) with absolute (1.3V) reference or internal DAC reference. • 1.3V reference (as a System Resource). ANALOG and HIGH VOLTAGE SECTIONS DBC01 GDO1 ODAC1 VDAC1 VBG IBIAS VDAC1 ODAC0 VDAC0 VDAC0 GDO0 HVO[1] VS0 Analog to Digital Convertor HV Driver P0[7] HV Driver HVO[0] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] Atten1 P1[1] AMuxBus3 AMuxBus1 IDAC1 P0[0] Atten0 P1[0] AMuxBus2 AMuxBus0 IDAC0 Multiple Sleep Modes COMP1 The CY8C42x23 devices have solid analog performance, low (100 µV) offsets, reduced temperature sensitivity, and are capable of measuring 0.75% absolute voltage accuracy. The Analog System is composed of configurable blocks to allow creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Following are some of the more common PSoC analog functions (most available as user modules). Document 38-12034 Rev. *C COMP0 ODAC1 ACLK Analog System ACLK The CY8C42x23 devices can have some of the system resources (the SleepTimer/Watchdog Timer, the Voltage Regulator or the Power Supply Supervisor) powered down in order to achieve the desired level of sleep current. Sleep modes with current levels from 750 µA in idle to 0.1 µA in deep sleep, and wakeup times from instantaneous to 400 µsec are available. Deeper sleep modes have longer wakeup times and sleep modes with more resource power typically have shorter wakeup times. 4.4 DBC00 VS1 Vss Vref Vbg The Digital System is composed of 4 digital PSoC blocks, 2 Enhanced Basic (Type D) and 2 Basic (Type C) to provide unique power control pulse width modulator (PWM) features. The power control features include integrated deadband, latched kill, and synchronous or asynchronous kill. The kill feature can be combined with a comparator to implement a fast over-current protection circuit. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user module references. A sampling of digital block configurations is listed below. • PWMs (8 to 32 bit) • PWMs with Deadband (8 to 16 bit) • Counters (8 to 32 bit) • Timers (8 to 32 bit) Temp 4.2 ODAC0 Figure 4-1. Analog Block Diagram 4.5 High Voltage Interface Two types of high voltage outputs are available. HVO[0] and HVO[1] are digital outputs that can each be configured as a CMOS output connected between HVdd and Vss, or configured as an open-drain drive that can be externally pulled up to HVdd or down to Vss. The second type, Gate Drive Outputs (GDO0 and GDO1), can each be used to drive the gate of a high-side PFET in a linear or switched regulator. The GDO0 and GDO1 outputs will drive between HVdd-5V and HVdd, the signal level required for a "logic level" PFET. The Gate Drive Outputs can be driven by an amplifier and used to control a PFET in a linear mode. A sense voltage can be fed back to the amplifier through an HV attenuator to implement a constant voltage or constant current driver. The output of the VDAC can be used to set the target voltage of the regulator. Alternately, the Gate Drive Outputs can be connected to the output gated PWM and used to drive a PFET as a high-side switch in a boost or buck convertor. Page 3 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 4.6 Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin in ports P0 and P1. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. This bus is split into four sections, AMux Bus 0 and AMux Bus 2, which connect to the even port pins and AMux Bus 1 and AMux Bus 3, which connect to the odd port pins. The four sections can be combined to support dual-channel single-end processing, single-channel differential processing, or dual-channel differential processing. They can also be connected as one bus that can route to all GPIO pins. Other multiplexer applications include: • Chip-wide mux that allows analog input from up to 10 GPIO pins. • Crosspoint connection between any GPIO pin combinations. 4.7 4.8 Development Tools • Standard Cypress PSoC IDE tools are available for debugging the CY8C42x23 family of parts. However, the additional trace length and a minimal ground plane in the Flex-Pod can create noise problems that make it difficult to debug a Power PSoC design. A custom bonded On-Chip Debug (OCD) device is available in an 32-pin QFN package. The OCD device is recommended for debugging designs that have high current and/or high analog accuracy requirements. The QFN package is compact and can be connected to the ICE through a high density connector. • In-System Serial Programming (ISSP) is available. However, ISSP for Power PSoC differs from ISSP for standard PSoC devices. With Power PSoC devices, the power pin (HVdd) should not be connected directly to the Vdd pin of the ISSP connector. Doing so can damage the programming device. Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems implemented in a single power block. Additional resources include an I2C master and slave, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. • Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. • The I2C module provides 50-, 100-, and 400-kHz communication over two wires. Slave, master, and multi-master modes are all supported. • Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. • An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. Document 38-12034 Rev. *C Page 4 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 5.0 Typical Power PSoC Applications 5.1 Boost Converter White LED Driver A white LED driver is a constant current power supply. By driving the same current through a set of LEDs in series, the intensity of the LEDs can be closely matched. The CY8C42x23 Power PSoC can be configured as a constant voltage or constant current boost supply. In this configuration, the HVdd voltage is lower than required to drive the LEDs in series and a higher voltage must be generated. White LEDs typically have a forward voltage of around 4V, so in the five LED configuration shown in Figure 5-1 the LED drive voltage would have to be around 20V (plus allowance for the voltage losses in the FET and the current sense resistor, RISENSE). Figure 5-1 shows an inductor, an NFET, a diode, and a capacitor configured as a boost converter with the CY8C42x23 as the controller. The voltage on the capacitor is fed back through a voltage sense pin, VS0, and an attenuator, Atten0, to the comparator, COMP0. The VS0 pin can be connected directly to a voltage higher than HVdd, so no external signal level conversion is needed. The output of the comparator controls a single PSoC digital block configured as a PWM. The reference for the comparator is the output of VDAC0. When the attenuator output exceeds the reference, the comparator will stop the PWM using the "Kill" input. This creates a feedback loop that maintains the VS0 node at a voltage proportional to the VDAC0 setting. The Atten0 output is also connected to the ADC so the control software can monitor the output voltage. To maintain constant current, the voltage across the RISENSE resistor is routed through pin P0[4] and AMuxBus0 to the ADC where it is monitored. The control software adjusts the VDAC0 setting, based on current sense measurements, to achieve the desired current through the load. 5.1.1 Resources This application could connect the RISENSE resistor to any of the GPIO pins (P0[7:0] and P1[1:0]). The Power PSoC still has three digital blocks, half of the high voltage resources, one VDAC, two IDACs, seven of the analog multiplexer channels to the ADC, and over 90% of the CPU available for other tasks. HVdd HVdd HVdd Low Drop-Out Reg ulator DBC01 ANALOG and HIGH V OLTAGE SECTIONS Internal Vdd ODAC1 VDAC1 GDO1 ODAC0 VDAC0 VDAC0 VBG VDAC1 IBIAS Q1 DBC00 GDO0 VS0 VS1 HVO[1] Analog to Dig ital Convertor HV Driver P0[7] HV Driver HVO[0] P0[6] Vbg Atten1 Vss P0[2] P0[1] Vref P0[4] P0[3] Temp P0[5] P0[0] Atten0 P1[1] R ISEN SE P1[0] IDAC1 AM uxBus3 AMuxBus2 AM uxBus1 AMuxBus0 COMP 1 COMP 0 ODAC1 ODAC0 ACLK ACLK Kill IDAC0 PWM primary PWM DB DCB00 DCB01 DBD02 DCD03 DIGITAL SECTION Figure 5-1. Boost Converter White LED Driver Document 38-12034 Rev. *C Page 5 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 5.2 Buck Converter Battery Charger with Current Limit A battery charger is constant current and constant voltage power supply. At different points in a charging cycle a Lithium Ion battery requires a constant current or a constant voltage to be applied. The CY8C42x23 Power PSoC can be configured as a constant voltage or constant current linear supply. In this configuration, the HVdd voltage is high enough to drive one or more battery in series and a lower voltage must be generated efficiently. Lithium Ion batteries have a fully charged voltage of 4.2V. With the two-cell configuration in Figure 5-2, HVdd would have to be at least 8.4V (plus allowance for voltage losses in the FET and the current sense resistor, RISENSE). The HVdd voltage is converted to 5V by the internal Low Drop-Out Regulator for use by the Power PSoC Core. Figure 5-2 shows an inductor, two FETs, and a capacitor configured as a buck converter with the CY8C42x23 as the controller. The voltage on the capacitor is fed back through a voltage sense pin, VS1, and an attenuator, Atten1, to the comparator, COMP1. The output of the comparator controls a single PSoC digital block configured as a pulse width modulator (PWM). The reference for the comparator is the output of VDAC1. When the attenuator output exceeds the reference, the comparator will stop the PWM using the "Kill" input. This creates a feedback loop that maintains the VS1 node at a voltage proportional to the VDAC1 setting. The Atten1 output is also connected to the ADC so the control software can monitor the output voltage. The accuracy of the ADC and the control loop are better than 0.75%. Meeting high accuracy is critical to Lithium Ion batteries. To maintain constant current, the voltage across the RISENSE resistor is routed through pin P1[0] and AMuxBus0 to the ADC where it is monitored. The control software adjusts the VDAC1 setting, based on current sense measurements, to achieve the desired current through the load. The current sense voltage is also connected to the positive input of COMP0. The negative input of COMP0 is controlled by the output of ODAC0. If the current sense voltage exceeds the ODAC0 setting, the output of the comparator will be latched high. This acts as an over-current detection circuit that can be cleared by the control software. The output of the comparator, COMP0, can be combined with the output of COMP1 and connected to the Kill input of the PWM. This configures the Power PSoC so that an over-current condition will shut off the External PFET. For a lower cost, but lower efficiency, converter, Q2 can be replaced with a diode. 5.2.1 Resources This application could connect the RISENSE resistor to any of the GPIO pins (P0[7:0] and P1[1:0]). The Power PSoC still has three digital blocks, half of the high voltage resources, one VDAC, two IDACs, seven of the analog multiplexer channels to the ADC, and over 90% of the CPU available to implement the battery charging algorithm and other tasks. HVdd HVdd Q1 HVdd LowDrop-Out Regulator DBC01 GDO1 ANALOG and HIGH VOLTAGE SECTIONS InternalVdd ODAC1 VDAC1 VDAC1 VBG IBIAS ODAC0 VDAC0 VDAC0 DBC00 GDO0 VS1 VS0 HVO[1] Analog to Digital Convertor HVDriver P0[7] HVDriver HVO[0] P0[6] P0[5] Q2 P0[4] P0[3] Atten1 Vss Vref Vbg Temp P0[2] P0[1] P0[0] Atten0 P1[1] RISENSE P1[0] IDAC1 AMuxBus3 AMuxBus2 AMuxBus1 AMuxBus0 COMP1 COMP0 ODAC1 ODAC0 ACLK ACLK Kill IDAC0 PWM PWM primary secondary PWM DB DCB00 DCB01 DBD02 DCD03 DIGITAL SECTION Figure 5-2. Buck Converter Battery Charger with Current Limit Document 38-12034 Rev. *C Page 6 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 5.3 Brushless DC Fan Motor The CY8C42x23 PSoC can be configured as a one- or two-phase brushless DC motor controller suitable for use in small brushless fans. In this configuration, the HVdd voltage is high enough to drive a one- or two-phase brushless motor coil, typically 12V. The HVdd voltage is converted to 5V by the internal Low Drop-Out Regulator for use by the Power PSoC Core. Additionally, several milliamperes of 5V from the internal regulator is made available to bias a hall sensor and thermistor. The high side PFETs of the H-bridge are driven by the GDO0 and GDO1 pins controlled by the processor. The low side NFETs of the H-bridge are driven by the HVO[0] and HVO[1] pins controlled by a combination of the processor and the pulse width modulator (PWM) for speed control. A differential comparator is used to determine rotor position from either an analog or digital hall sensor to facilitate rotor commutation. A second comparator and 8-bit DAC, VDAC0, are available to provide an optional hardware current limit. The 10-bit ADC is available to measure optional parameters such as ambient temperature or motor coil current. The M8C processor handles coil commutation, user customizable speed, and control algorithms as well as an optional communications interface. The PSoC digital resources provide an 8-bit PWM output to drive the motor coil as well as two timer configurations. Using dynamic reconfiguration, two digital blocks are used to create a 16-bit timer to measure the tachometer period while the same two blocks are also used to create two 8-bit timers to measure the input PWM duty cycle. 5.3.1 Resources This application leaves 3 GPIO pins, 1 digital block, I2C and ample memory unused for further application customization. HVdd 1 or 2 Phase Brushless Motor (1 Phase Depicted) RISENSE HVdd Optional HVdd LowDrop-Out Regulator InternalVdd ODAC1 VDAC1 VDAC1 DBC01 GDO1 ANALOG and HIGH VOLTAGE SECTIONS VBG IBIAS VDAC0 ODAC0 VDAC0 DBC00 GDO0 VS1,HVO[1] VS0, HVO[0] P0[7] HVDriver AVdd Analog to Digital Convertor HVDriver P0[6] P0[4] P0[5] P0[2] P0[1] ` ATTEN1 P1[1] Tach Out IDAC1 TEMP Vss Vref Vbg P0[3] ATTEN0 AMuxBus3 AMuxBus2 AMuxBus1 AMuxBus0 P0[0] 5V Out P1[0] InputPWM IDAC0 5V COMP1 5V COMP0 ODAC0 ACLK ACLK Analog Hall Sensor ODAC1 T DIGITAL SECTION Kill PWM Out PWM DB Capture Optional 16-bit Timer (Tachometer) 2x8-bit Timer (Input PWM) Figure 5-3. Brushless DC Fan Motor Document 38-12034 Rev. *C Page 7 of 42 PRELIMINARY 6.0 CY8C42123/CY8C42223 CY8C42323/CY8C42423 Pin Assignment This section lists, describes, and illustrates all Power PSoC device pins and pinout configurations. For up-to-date ordering, pinout, and packaging information, refer to the individual PSoC device’s data sheet or go to http://www.cypress.com/psoc. 6.1 Pinouts The PSoC devices are available in a variety of packages. Refer to the following information for details on individual devices. Every port pin (labeled with a “P”) in the following tables and illustrations is capable of digital IO. 6.1.1 8-Pin SOIC Part Pinouts The 8-pin SOIC part is for the CY8C42123 PSoC device. Pin No. Digital Analog 8-Pin Part Pinout (SOIC) Name 1 HVO HVO GD1 2 IO I P0[1] 3 IO I P1[1] I P1[0] 4 5 Power IO CY8C42123 PSoC Device Vss Description High Side Gate Driver 1 I2C Clock* Ground Connection IO I P0[0] 7 HVO HVI VS0 High Voltage Sense 0, High Voltage Output 0 HVdd Supply Voltage Power 1 8 2 SOIC 7 3 6 4 5 HV dd HVO[0],VS0 P0[0] P1[0] I2C* I2C Data* 6 8 GD1 P0[1] I2C* P1[1] Vss LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details. Document 38-12034 Rev. *C Page 8 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 6.1.2 16-Pin SOIC Part Pinouts The 16-pin SOIC part is for the CY8C42223 PSoC device. 1 HVO 2 Analog Pin No. Digital 16-Pin Part Pinout (SOIC) Name HVO GD1 High Side Gate Driver 1 VS1 High Voltage Sense 1 HVI CY8C42223 PSoC Device Description 3 HVO 4 IO I P0[7] I2C Clock 5 IO I P0[5] I2C Data 6 IO I P0[3] 7 IO I P1[1] 8 HVO[1] High Voltage Output 1 Power Vss I P1[0] I2C Data* 10 IO I P0[2] Optional External CLK Input (EXTCLK) IO I P0[4] IO I P0[6] 13 HVO 14 15 16 HVO SOIC 16 15 14 13 12 11 10 9 HVdd GD0 VS0 HVO[0] P0[6], EXTREF P0[4] P0[2], EXTCLK P1[0] I2C* Ground Connection IO 11 1 2 3 4 5 6 7 8 I2C Clock* 9 12 GD1 VS1 HVO[1] SCL, P0[7] SDA, P0[5] P0[3] I2C* P1[1] Vss Optional External Voltage Reference (EXTREF) HVO[0] High Voltage Output 0 HVI VS0 HVO GD0 High Side Gate Driver 0 HVdd Supply Voltage Power High Voltage Sense 0 LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details. Document 38-12034 Rev. *C Page 9 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 6.1.3 16-Pin TSSOP Part Pinouts The 16-pin TSSOP part is for the CY8C42323 PSoC device. Pin No. Digital Analog 16-Pin Part Pinout (TSSOP) Name 1 HVO HVO GD1 High Side Gate Driver 1 2 HVO HVI VS1 High Voltage Sense 1, High Voltage Output 1 3 IO I P0[7] I2C Clock 4 IO I P0[5] I2C Data 5 IO I P0[3] 6 IO I P0[1] 7 IO I P1[1] 8 Power CY8C42323 PSoC Device Vss 9 IO I P1[0] 10 IO I P0[0] Description 16 15 14 TSSOP 13 12 11 10 9 HVdd GD0 VS0, HVO[0] P0[6], EXTREF P0[4] P0[2], EXTCLK P0[0] P1[0] I2C* I2C Clock* I2C Data* 11 IO I P0[2] IO I P0[4] 13 IO I P0[6] Optional External Voltage Reference (EXTREF) 14 HVO HVI VS0 High Voltage Sense 0, High Voltage Output 0 15 HVO HVO Power 1 2 3 4 5 6 7 8 Ground Connection 12 16 GD1 HVO[1], VS1 SCL, P0[7] SDA, P0[5] P0[3] P0[1] I2C* P1[1] Vss Optional External CLK Input (EXTCLK) GD0 High Side Gate Driver 0 HVdd Supply Voltage LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details. Document 38-12034 Rev. *C Page 10 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 6.1.4 32-Pin QFN Part Pinouts The 32-pin QFN part is for the CY8C42423 PSoC device. NC No Connection 4 NC No Connection 5 IO I P0[7] I2C Clock 6 IO I P0[5] I2C Data 7 IO I P0[3] 8 IO I P0[1] 9 NC No Connection 10 NC No Connection IO 12 13 I Power IO P1[1] I2C Clock* Vss I P1[0] I2C Data* 14 NC No Connection 15 NC No Connection 16 NC No Connection 17 IO I P0[0] 18 IO I P0[2] 19 IO I P0[4] 20 IO I P0[6] 21 I No Connection NC No Connection HVO DNU 26 30 Do Not Use HVI VS0 High Voltage Sense 0 HVO GD0 High Side Gate Driver 0 Power HVdd Supply Voltage Power HVO HVO HVdd Supply Voltage HVO GD1 High Side Gate Driver 1 HVI VS1 High Voltage Sense 1 NC No Connection Vss Center Pad Must be Connected to Ground 31 32 CP HV O[0] NC NC XRES P0[6] P0[4] P0[2] P0[0] HVO[0] High Voltage Output 0 25 29 QFN (Top View ) (CP) 24 23 22 21 20 19 18 17 XRES External Reset NC 28 1 2 3 4 5 6 7 8 Optional External Voltage Reference (EXTREF) 23 27 NC HV O[1] NC NC P0[7] P0[5] P0[3] P0[1] Optional External CLK Input (EXTCLK) 22 24 VS0 DNU HVO[1] High Voltage Output 1 3 11 26 25 No Connection 9 10 11 12 13 14 15 16 HVO Description GD1 HVdd HVdd GD0 NC NC NC I2C*, P1[1] Vss I2C*, P1[0] NC NC NC 2 Name NC VS1 1 CY8C42423 PSoC Device 32 31 30 29 28 27 Digital Pin No. Analog 32-Pin Part Pinout (QFN**) Power LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage, NC = No Connection. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details. **The QFN package has a center pad (CP) that must be connected to ground (Vss). Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Document 38-12034 Rev. *C Page 11 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The 32-pin QFN part is for the CY8C42000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. HVO[1] High Voltage Output 1 OCD HCLK On-Chip Debug Clock 4 OCD CCLK On-Chip Debug Clock 5 IO I P0[7] I2C Clock 6 IO I P0[5] I2C Data 7 IO I P0[3] 8 IO I P0[1] 9 NC No Connection 10 NC No Connection 11 IO 12 13 I Power IO P1[1] I2C Clock* Vss I P1[0] I2C Data* 14 NC No Connection 15 NC No Connection 16 NC No Connection 17 IO I P0[0] 18 IO I P0[2] 19 IO I P0[4] 20 IO I P0[6] 21 I No Connection NC No Connection HVO HV O[0] OCDE OCDO XRES P0[6] P0[4] P0[2] P0[0] Not for Production HVO[0] High Voltage Output 0 25 DNU 26 HVO Do Not Use HVI VS0 High Voltage Sense 0 HVO GD0 High Side Gate Driver 0 28 Power HVdd Supply Voltage 29 Power HVdd Supply Voltage HVO GD1 High Side Gate Driver 1 HVI VS1 High Voltage Sense 1 NC No Connection Vss Center Pad Must be Connected to Ground HVO 31 32 CP QFN (Top View ) (CP) 24 23 22 21 20 19 18 17 XRES External Reset NC 30 1 2 3 4 5 6 7 8 Optional External Voltage Reference (EXTREF) 23 27 NC HV O[1] HCLK CCLK P0[7] P0[5] P0[3] P0[1] Optional External CLK Input (EXTCLK) 22 24 VS0 DNU HVO 3 26 25 No Connection 2 GD1 HVdd HVdd GD0 Description NC VS1 NC 32 31 30 29 28 27 Name 9 10 11 12 13 14 15 16 1 CY8C42000 OCD PSoC Device NC NC I2C*, P1[1] Vss I2C*, P1[0] NC NC NC Digital Pin No. Analog 32-Pin OCD Part Pinout (QFN**) Power LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage, NC = No Connection, OCD = On-Chip Debug. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details. **The QFN package has a center pad (CP) that must be connected to ground (Vss). Document 38-12034 Rev. *C Page 12 of 42 PRELIMINARY 7.0 CY8C42123/CY8C42223 CY8C42323/CY8C42423 Registers This section discusses the registers of the Power PSoC device. It lists all the registers in mapping tables, in address order. 7.1 Register Conventions The register conventions specific to this section are listed in the following table. Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document 38-12034 Rev. *C Page 13 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 7.2 Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Addr (0,Hex) Name Access Addr (0,Hex) Name Access Addr (0,Hex) Name Access PRT0DR 00 RW 40 80 C0 PRT0IE 01 RW 41 81 C1 PRT0GS 02 RW 42 82 C2 PRT0DM2 03 RW 43 83 PRT1DR 04 RW 44 ASC00CR0 84 RW C4 PRT1IE 05 RW 45 ASC00CR1 85 RW C5 PRT1GS 06 RW 46 ASC00CR2 86 RW PRT1DM2 07 RW 47 ASC00CR3 87 RW IDAC_D C7 RW HVP2_DR 08 RW 48 ASC01CR0 88 RW P0_MUX C8 RW 09 49 ASC01CR1 89 RW P1_MUX C9 RW 0A 4A ASC01CR2 8A RW CA 0B 4B ASC01CR3 8B RW CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 90 D0 11 51 91 D1 12 52 92 D2 13 53 93 D3 14 54 94 D4 15 55 95 16 56 96 I2C_CFG D6 RW 17 57 97 I2C_SCR D7 # 18 58 98 I2C_DR D8 RW 19 59 99 I2C_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C INT_CLR2 DC RW 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F INT_MSK2 DF RW C3 C6 D5 DBC00DR0 20 R AC0_MUX 60 RW PWR0_CR A0 RW INT_MSK0 E0 RW DBC00DR1 21 W AC0_CR0 61 RW PWR1_CR A1 RW INT_MSK1 E1 RW DBC00DR2 22 RW AC0_CR1 62 RW A2 INT_VC E2 RC DBC00CR0 23 RW AC0_CR2 63 RW A3 RES_WDT E3 W DBC01DR0 24 R AC0_MSP 64 RW DBC01DR1 25 W AC0_LSP 65 RW A5 DBC01DR2 26 RW AC0_MSR 66 RW A6 DBC01CR0 27 RW AC0_LSR 67 RW VDAC_CR A7 RW E7 DBD02DR0 28 R AC0_CC 68 # VDAC_DR0 A8 RW E8 DBD02DR1 29 W 69 VDAC_DR1 A9 RW E9 DBD02DR2 2A RW 6A AA EA DBD02CR0 2B RW 6B AB EB DBD03DR0 2C R TMP_DR0 6C RW AC EC DBD03DR1 2D W TMP_DR1 6D RW AD ED DBD03DR2 2E RW TMP_DR2 6E RW AE EE DBD03CR0 2F RW TMP_DR3 6F RW AF 30 CMP_SYN 70 RW RDI0RI B0 31 CMP_LFN0 71 RW RDI0SYN B1 RW F1 RDI0IS B2 RW F2 32 72 AA_REF A4 RW E4 E5 E6 EF RW F0 33 CMP_LMD 73 RW RDI0LT0 B3 RW F3 34 CMP_CDS 74 RW RDI0LT1 B4 RW F4 35 CMP_CIS 75 RW RDI0RO0 B5 RW F5 36 CMP_RDC 76 RW RDI0RO1 B6 RW F6 37 CMP_GOEN0 77 RW RDI0GF B7 RW 38 78 CPU_F F7 B8 F8 39 CMP_CLK 79 RW B9 F9 3A CMP_CR 7A RW BA FA 3B CMP_SRC 7B RW BB FB 3C CMP_MUX0 7C RW BC 3D CMP_MUX1 7D RW BD CPU_SCR2 RL FC FD RSW 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # Blank fields are Reserved and should not be accessed. Document 38-12034 Rev. *C Page 14 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 7.3 Register Map Bank 1 Table: Configuration Space Name Addr (1,Hex) Access Name Addr (1,Hex) Access Addr (1,Hex) Name Access Name Addr (1,Hex) Access PRT0DM0 00 RW 40 80 C0 PRT0DM1 01 RW 41 81 C1 PRT0IC0 02 RW 42 82 C2 PRT0IC1 03 RW 43 83 C3 PRT1DM0 04 RW 44 84 C4 PRT1DM1 05 RW 45 85 C5 PRT1IC0 06 RW 46 86 PRT1IC1 07 RW 47 87 HVP2_DM0 08 RW 48 88 HVP2_DM1 09 RW 49 89 C9 HVP2_DS0 0A RW 4A 8A CA 0B 4B 8B CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F 10 50 90 GDI_O_IN D0 11 51 91 GDI_E_IN D1 RW 12 52 92 GDI_O_OU D2 RW 13 53 93 GDI_E_OU D3 RW 14 54 94 AC0_GOEN D4 RW 15 55 95 D5 16 56 96 D6 17 57 97 18 58 98 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F C6 IDAC_CR C7 RW C8 CF RW D7 AC0_CLK RW OSC_CR3 DF RW DBC00FN 20 RW 60 SLP_CR0 A0 RW OSC_CR0 E0 RW DBC00IN 21 RW 61 SLP_CR1 A1 RW OSC_CR1 E1 RW DBC00OU 22 RW 62 SLP_CR2 A2 RW OSC_CR2 E2 RW VLT_CR E3 RW VLT_CMP E4 R 23 9F D8 63 A3 DBC01FN 24 RW 64 DBC01IN 25 RW 65 A5 E5 DBC01OU 26 RW 66 A6 E6 67 A7 27 BUS_TOP A4 RW E7 DBD02FN 28 RW 68 VDAC_TR A8 RW IMO_TR E8 DBD02IN 29 RW 69 VDAC_ITRIP0 A9 RW LSO_TR E9 RW DBD02OU 2A RW 6A BDG_TR EA RW 2B AA 6B AB DBD03FN 2C RW TMP_DR0 6C RW DBD03IN 2D RW TMP_DR1 6D RW AD DBD03OU 2E RW TMP_DR2 6E RW AE TMP_DR3 6F RW 2F RDIV0 AC W EB RW EC AA_TR ED RW EE AF EF 30 70 RDI0RI B0 RW F0 31 71 RDI0SYN B1 RW F1 32 72 RDI0IS B2 RW F2 33 73 RDI0LT0 B3 RW F3 34 74 RDI0LT1 B4 RW F4 35 75 RDI0RO0 B5 RW F5 36 76 RDI0RO1 B6 RW F6 37 77 RDI0GF B7 RW 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC 3D 7D BD CPU_SCR2 FD RSW 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF # CPU_F F7 RL FC Blank fields are Reserved and should not be accessed. Document 38-12034 Rev. *C Page 15 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 8.0 Electrical Specifications Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. 8.1 Frequencies 36 SLIMO Mode = 0 Refer to Table 8.4 for the electrical specifications on the internal main oscillator (IMO) using slow IMO (SLIMO) mode, which can be set using the CPU_SCR1 register. 36 ~ ~ ~ ~ HVdd Voltage HVdd Voltage l i d ng Va a t i n r pe io O Re g 4.75 ~ ~ 3.00 3.00 2.40 2.40 3 MHz 12 MHz 24 MHz SLIMO ~ Mode=0~ SLIMO Mode=1 SLIMO Mode=1 SLIMO Mode=0 4.75 3.60 93 kHz SLIMO Mode=1 93 kHz 12 MHz 6 MHz 24 MHz CPU Fre que ncy IM O Fre que ncy Figure 8-1a. Supply Voltage versus CPU Frequency Figure 8-1b. IMO Frequency Trim Options 8.2 Absolute Maximum Ratingsa Parameter Description TSTG Storage Temperature TA HVdd VGPIO VGPIO36 VGD VVS VHVO IMIO IMIOHV Conditions Higher storage temperatures will reduce data retention time. Ambient Temperature with Power Applied Supply Voltage on HVdd Relative to Vss DC Input to any Low Voltage HVdd ≤ 5.0V. Input Pin DC Input to any Low Voltage HVdd > 5.0V. Input Pin DC Input to any Gate Drive Pin DC Input to High Voltage Sense Pin DC Applied to High Voltage Outputs in High-Z State Maximum Current into any Low Voltage Port Pin Maximum Current into any High Voltage Port Pin Document 38-12034 Rev. *C Min. -50 Typ. – Max. +100 Units oC -40 – +85 oC -0.5 – +40 V -0.5 – V -0.5 – HVdd + 0.5 5.5 HVdd 5.5 -0.5 – V -0.5 – -25 – HVdd + 0.5 HVdd + 0.5 HVdd + 0.5 +50 mA -50 – +50 mA – V Page 16 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY Absolute Maximum Ratingsa (continued) 8.2 IMIOGDb ESD ESDHV LU Maximum Current into any Gate Drive Pin Electro Static Discharge Voltage Human Body Model ESD. Electro Static Discharge to High Human Body Model ESD. Voltage Port Pin Latch-up Current -10 – 10 mA 2000 2000 – – – – V V – – 200 mA Max. +85 +100 Units oC oC a. Operation at these conditions degrades reliability. b. Cannot result in pin voltage exceeding VGD limits or thermal specifications being exceeded. 8.3 Operating Temperature Parameter Description TA Ambient Temperature TJ Junction Temperature Conditions The temperature rise from ambient to junction is package specific. See Table 9.1, “Thermal Impedances per Package,” on page 38. The system designer must limit the power consumption to comply with this requirement. Min. -40 -40 Typ. – – The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.4 DC Chip-Level Specifications Parameter Description HVdd Supply Voltage IDD Supply Current, IMO = 24 MHz IDD36 Supply Current, IMO = 24 MHz IDD3 Supply Current, IMO = 6 MHz Document 38-12034 Rev. *C Conditions See Table 8.18, “DC POR and LVD Specifications,” on page 25. Conditions are HVdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. Conditions are HVdd = 36V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. Conditions are HVdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. Min. 2.5 Typ. – Max. 36 Units V – 3 4 mA – 3 4 mA – 1.2 2 mA Page 17 of 42 PRELIMINARY 8.4 CY8C42123/CY8C42223 CY8C42323/CY8C42423 DC Chip-Level Specifications (continued) IDD27 Supply Current, IMO = 6 MHz IRESET Supply Current in Reset ISBI Supply Current in Idle Mode ISB Supervised Sleep Current (POR, LVD, SleepTimer, WDT, and Voltage Regulation) Regulated Sleep Current (No POR, No LVD, but with SleepTimer, WDT, and Voltage Regulation) Watchdog Sleep Current (No POR, No LVD, No SleepTimer, No Voltage Regulation but with WDT) Deep Sleep Current (No POR, No LVD, No SleepTimer, No Voltage Regulation and No WDT Deep Sleep Current at HV (No POR, No LVD, No SleepTimer, No Voltage Regulation and No WDT Reference Voltage (Bandgap) Reference Voltage (Bandgap) ISBR ISBW ISBD ISBDHV VREF VREF27 Document 38-12034 Rev. *C Conditions are HVdd = 2.7V, TA = 25 oC, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz, analog power = off. SLIMO mode = 1. IMO = 6 MHz. Conditions are HVdd = 5.0V, -40 oC ≤ TA ≤ 85 oC. Conditions are with internal slow speed oscillator, HVdd = 3.3V, -40 oC ≤ TA ≤ 85 oC, analog power = off. Conditions are with internal slow speed oscillator, HVdd = 3.3V, -40 oC ≤ TA ≤ 85 oC, analog power = off. Conditions are with internal slow speed oscillator, HVdd = 3.3V, -40 oC ≤ TA ≤ 85 oC, analog power = off. – 1.1 1.5 mA – – 250 µA – – 750 µA – 2.8 3 µA – – 1 µA Conditions are with internal slow speed oscillator, HVdd = 3.3V, TA = 25 oC, analog power = off. – 0.5 – µA Conditions are bypass mode on, deep sleep enabled, HVdd = 3.3V, TA = 25 oC, analog power = off. – 0.1 – µA Conditions are analog power off, deep sleep enabled, HVdd = 6V, TA = 25 oC. – ((HVdd - 6) / 2) + 0.1 – µA 1.291 1.16 1.30 1.30 1.309 1.33 V V Trimmed for HVdd > 3.0V. Trimmed for HVdd = 2.5V to 3.0V. Page 18 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.5 4.75V to 36V DC GPIO Specifications Parameter Description RPU Pull-up Resistor RPD Pull-down Resistor VOHa High Output Level Conditions IOH = 10 mA, HVdd = 4.75V to 36V maximum 40 mA on even port pins (for example, P0[2], P1[0]), maximum 40 mA on odd port pins (for example, P0[3], P1[1]). IOL = 25 mA, HVdd = 4.75V to 36V maximum 90 mA on even port pins (for example, P0[2], P1[0]), maximum 90 mA on odd port pins (for example, P0[3], P1[1]). 4.5V ≤ VOH ≤ 5.5V, HVdd = 4.75V to 36V. HVdd = 4.75V to 36V. HVdd = 4.75V to 36V. VOLa Low Output Level IOHb Current Supplied while Maintaining 10% Regulation Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Gross tested to 1 µA. Capacitive Load on Pins as Input Package and pin dependent. Temp = 25oC. Capacitive Load on Pins as Package and pin dependent. Temp = Output 25oC. VIL VIH VH IIL CIN COUT Min. 4 4 3.6 Typ. 5.6 5.6 – Max. 8 8 5.4 Units kΩ kΩ V – – 0.75 V 5.5 – – mA – 2.1 – – – – – 60 1 3.5 0.8 – – – 10 V V mV nA pF – 3.5 10 pF a. IOH and IOL are also limited by the die temperature. See “Thermal Considerations” on page 37. b. Odd and even port pins are regulated separately, therefore the current limit total applies separately to all odd port pins and to all even port pins. 8.6 3.0V to 5.0V DC GPIO Specifications Parameter Description RPU Pull-up Resistor RPD Pull-down Resistor VOHa High Output Level VOLa Low Output Level VIL VIH Input Low Level Input High Level Document 38-12034 Rev. *C Conditions IOH = 8 mA, HVdd = 3.0V to 3.6V maximum 30 mA on even port pins (for example, P0[2], P1[0]), maximum 30 mA on odd port pins (for example, P0[3], P1[1]). IOL = 16 mA, HVdd = 3.0V to 3.6V maximum 60 mA on even port pins (for example, P0[2], P1[0]), maximum 60 mA on odd port pins (for example, P0[3], P1[1]). HVdd = 3.0V to 3.6V. HVdd = 3.0V to 3.6V. Min. 4 4 HVdd 1.0 Typ. 5.6 5.6 – Max. 8 8 HVdd Units kΩ kΩ V – – 0.75 V – 2.1 – – 0.8 – V V Page 19 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 8.6 3.0V to 5.0V DC GPIO Specifications (continued) VH IIL CIN COUT Input Hysteresis Input Leakage (Absolute Value) Gross tested to 1 µA. Capacitive Load on Pins as Input Package and pin dependent. Temp = 25oC. Capacitive Load on Pins as Package and pin dependent. Temp = Output 25oC. – – – 60 1 3.5 – – 10 mV nA pF – 3.5 10 pF a. IOH and IOL are also limited by the die temperature. See “Thermal Considerations” on page 37. 8.7 2.5V to 3.0V DC GPIO Specifications Parameter Description RPU Pull-up Resistor RPD Pull-down Resistor a VOH High Output Level Conditions IOH = 2 mA, HVdd = 2.5V to 3.0V maximum 16 mA on even port pins (for example, P0[2], P1[0]), maximum 16 mA on odd port pins (for example, P0[3], P1[1]). IOL = 8 mA, HVdd = 2.5V to 3.0V maximum 40 mA on even port pins (for example, P0[2], P1[0]), maximum 40 mA on odd port pins (for example, P0[3], P1[1]). HVdd = 2.5V to 3.0V. HVdd = 2.5V to 3.0V. VOLa Low Output Level VIL VIH VH IIL CIN Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Gross tested to 1 µA. Capacitive Load on Pins as Input Package and pin dependent. Temp = 25oC. Capacitive Load on Pins as Package and pin dependent. Temp = Output 25oC. COUT Min. 4 4 HVdd 1.0 Typ. 5.6 5.6 – Max. 8 8 HVdd Units kΩ kΩ V – – 0.75 V – 2.0 – – – – – 60 1 3.5 0.8 – – – 10 V V mV nA pF – 3.5 10 pF a. IOH and IOL are also limited by the die temperature. See “Thermal Considerations” on page 37. Document 38-12034 Rev. *C Page 20 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.8 4.75V to 36V DC High Voltage Output Specifications Parameter Description High Output Level VOHHVa Conditions IOH = 50 mA, HVdd = 4.75V to 36V. VOLHVa IIL COUT IOL = 50 mA, HVdd = 4.75V to 36V. Gross tested to 1 µA. Package and pin dependent. Temp = 25oC. Low Output Level Input Leakage (Absolute Value) Capacitive Load on Pins as Output Min. HVdd 2.0 – – – Typ. – Max. – Units V – 1 – 2.0 – 100 V nA pF Typ. – Max. – Units V – 1 – 0.75 – 100 V nA pF a. IOH and IOL are also limited by the die temperature. See “Thermal Considerations” on page 37. 8.9 2.5V to 5V DC High Voltage Output Specifications Parameter Description VOHHVa High Output Level Conditions IOH = 10 mA, HVdd = 2.5V to 5V. VOLHVa IIL COUT IOL = 10 mA, HVdd = 2.5V to 5V. Gross tested to 1 µA. Package and pin dependent. Temp = 25oC. Low Output Level Input Leakage (Absolute Value) Capacitive Load on Pins as Output Min. HVdd 0.7 – – – a. IOH and IOL are also limited by the die temperature. See “Thermal Considerations” on page 37. Document 38-12034 Rev. *C Page 21 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.10 DC Comparator Specifications Parameter Description VOSSYN Input Offset Voltage in Synchronous Mode (Absolute Value) VOS Input Offset Voltage in NonSynchronous Mode (Absolute Value) ICOMPSYN Current Consumption in Synchronous Mode Current Consumption of ICOMP Comparator ICOMPLP Current Consumption in Low Power Mode VIN27 Input Voltage Range VIN36 Input Voltage Range VINLP27 Input Voltage Range in Low Power Mode VINLP36 Input Voltage Range in Low Power Mode Conditions Min. – Typ. – Max. 100 Units µV – 2.5 15 mV – 100 200 µA HVdd = 2.5V to 36V. – 10 30 µA HVdd = 2.5V to 36V. – 3 10 µA HVdd = 2.5V to 5V. HVdd = 5V to 36V. HVdd = 2.5V to 5V. 0 0 0 – – – HVdd 5.0 HVdd -1.1 V V V HVdd = 5V to 36V. 0 – 3.9 V The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.11 DC Analog-to-Digital Converter Specifications Parameter VOS VIN HVIN RIN INL DNL Description Conditions Input Offset Voltage Input Voltage Range Voltage on Analog Mux Bus. High Voltage Sense Input Range Voltage on Analog Mux Bus. Input Impedance Resolution INL Error DNL Error Absolute System Errora Factory trimmed at ADC gains of 1/4, 1, 4, 16. Min. – 0 0 – 6 – – – Typ. – – – 100K – – – – Max. 100 3 HVdd – 12 1 1/2 0.75% Units µV V V Ω bits LSb LSb a. Maximum error is 11% for HVdd = 2.5V to 3.0V; consistent with VREF27 specifications. Document 38-12034 Rev. *C Page 22 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.12 DC Linear Control Specifications Parameter VOS RATIO1 RATIO2 RATIO3 RATTEN VDAC VOC1 VOC2 VOC3 VOC4 Description Conditions Comparator Input Offset Voltage Attenuation Resistor Ratioa Attenuation Resistor Ratioa Attenuation Resistor Ratioa Attenuator Resistance Control Loop Reference Full range is 0V to VREF. Resolution Loop Control Reference Settinga Pre-Programmed Over-Current Set Point Pre-Programmed Over-Current Set Point Pre-Programmed Over-Current With VDAC_CR Mode = 1. Set Point Pre-Programmed Over-Current With VDAC_CR Mode = 1. Set Point Min. – – – – – – Typ. – 4 8 16 400K 8 Max. 100 – – – – – Units µV 0 120 – 150 VREF 180 V mV 240 300 360 mV 360 450 540 mV 720 900 1080 mV Ω bits a. Error in this parameter is included in the Absolute System Error. The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.13 4.75V to 36V DC Gate Drive, Linear Output Specificationsa Parameter Description VOHGD High Output Voltage Conditions HVdd = 5V to 36V. VOLGD HVdd = 5V to 36V. Low Output Voltage Min. HVdd 0.1 – Typ. – Max. – Units V HVdd - 5 – V a. To maintain the Absolute System Error per table DC Analog-to-Digital Converter Specifications, the current into or out of the Gate Drive Output must be less than 100 nA. 8.14 2.5V to 5V DC Gate Drive, Linear Output Specifications Parameter Description VOHGD High Output Voltage Conditions IOH = 100 nA, HVdd = 2.5V to 5V. VOLGD IOL = 100 nA, HVdd = 2.5V to 5V. Low Output Voltage Document 38-12034 Rev. *C Min. HVdd 0.1 – Typ. – Max. – Units V – 1.0 V Page 23 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.15 4.75V to 36V DC Gate Drive, PWM Output Specifications Parameter Description VOHGD High Output Voltage Conditions IOH = 1 µA, HVdd = 4.75V to 36V. VOLGD IOL = 1 µA, HVdd = 4.75V to 36V. Low Output Voltage Min. HVdd 0.1 – Typ. – Max. – Units V HVdd - 5 – V Typ. – Max. – Units V – 1.0 V 8.16 2.5V to 5 V DC Gate Drive, PWM Output Specifications Parameter Description VOHGD High Output Voltage Conditions IOH = 1 µA, HVdd = 2.5V to 5V. VOLGD IOL = 1 µA, HVdd = 2.5V to 5V. Low Output Voltage Min. HVdd 0.1 – The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.17 DC Analog Mux Bus Specifications Parameter Description RSW Switch Resistance to Common Analog Bus Document 38-12034 Rev. *C Conditions HVdd ≥ 5V. HVdd = 3.3V. HVdd = 2.7V. Min. – – – Typ. 1000 1500 2000 Max. – – – Units Ω Ω Ω Page 24 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 The following table lists guaranteed maximum and minimum specifications for the temperature range: -40°C ≤ TA ≤ 85°C. Typical parameters apply at 25°C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the Power PSoC Mixed-Signal Array Technical Reference Manual for more information on the VLT_CR register. 8.18 DC POR and LVD Specifications Parameter VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Conditions Vdd must be greater than or equal to 2.6V during startup, reset from the XRES pin, or reset from Watchdog. Min. Typ. Max. Units – – – 2.46 2.82 4.55 2.50 2.95 4.70 V V V 2.50 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.550 2.920 3.02 3.13 4.48 4.64 4.73 4.81 2.61a 2.99b 3.09 3.20 4.55 4.75 4.83 4.95 V V V V V V V V a. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply. b. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply. Document 38-12034 Rev. *C Page 25 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.19 DC Programming Specifications Parameter Description VddIWRITE Supply Voltage for Flash Write Operations IDDP Supply Current During Programming or Verify VILP Input Low Level During Programming or Verify VIHP Input High Level During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Level During Programming or Verify VOHV Output High Level During Programming or Verify VOHV36 Output High Level During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)a FlashDR Flash Data Retention Conditions Min. 2.80 Typ. – Max. – Units V – 5 25 mA – – 0.8 V 2.1 – – V Driving internal pull-down resistor. – – 0.2 mA Driving internal pull-down resistor. – – 1.5 mA – – 0.75 V HVdd 1.0 3.6 – HVdd V 5.0 – V 50 1,800 10 – – – – – – KCycles KCycles Years HVdd = 2.5V to 5V. HVdd = 5V to 36V. Erase/write cycles per block. Erase/write cycles. a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document 38-12034 Rev. *C Page 26 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.20 3.0V to 36V AC Chip-Level Specifications Parameter Description FIMO24 Internal Main Oscillator Frequency for 24 MHz Conditions Trimmed for 5V or 3.3V operation using factory trim values. See Figure 8-1b on page 16. SLIMO mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See Figure 8-1b on page 16. SLIMO mode = 1. Min. 23.4 Typ. 24 Max. 24.6a,b,c Units MHz 5.85 6 6.15a,b,c MHz CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Refer to the AC Digital Block Specifications. F24M Digital PSoC Block Frequency F1K Internal Low Speed Oscillator Frequency DC24M 24 MHz Duty Cycle Step24M 24 MHz Trim Step Size Fout48M 48 MHz Output Frequency Trimmed. Utilizing factory trim values. Jitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean Squared FMAX Maximum Frequency of Signal on Row Input or Row Output TRAMP Supply Ramp Time TSBI Wakeup Time from Idle Mode TSB Wakeup Time from Supervised Sleep TSBR Wakeup Time from Regulated Sleep TSBW Wakeup Time from Watchdog Sleep TSBD Wakeup Time from Deep Sleep 0.91 0.91 0 24 12 48 24.6a,b 12.3b,c 49.2a,b,d MHz MHz MHz 0 0.6 24 1 24.6b,d 1.5 MHz kHz 40 – 46.8 50 50 48.0 60 – 49.2a,c % kHz MHz – 300 – ps – – 600 ps – – 12.3 MHz 0 – – – – – – 0 30 µs µs µs – – 30 µs – – 400 µs – – 3 ms FIMO6 Internal Main Oscillator Frequency for 6 MHz FCPU1 FCPU2 F48M a. b. c. d. 4.75V < HVdd < 36V, -40°C ≤ TA ≤ 70°C. Accuracy derived from Internal Main Oscillator with appropriate trim for HVdd range. 3.0V < HVdd < 3.6V, -40°C ≤ TA ≤ 70°C. See the individual user module data sheets for information on maximum frequencies for user modules. Document 38-12034 Rev. *C Page 27 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 8.21 2.5V to 3.0V AC Chip-Level Specifications Parameter Description FIMO12 Internal Main Oscillator Frequency for 12 MHz Conditions Trimmed for 2.7V operation using factory trim values. See Figure 8-1b on page 16. SLIMO mode = 0. Trimmed for 2.7V operation using factory trim values. See Figure 8-1b on page 16. SLIMO mode = 1. Min. 11.5 Typ. 12 Max. 12.5a,b Units MHz 5.76 6 6.24a,b MHz CPU Frequency (2.7V Nominal) Digital PSoC Block Frequency Refer to the AC Digital Block Speci(2.7V Nominal) fications. F1K Internal Low Speed Oscillator Frequency DC12M 12 MHz Duty Cycle Jitter12M1P 12 MHz Period Jitter (IMO) Peak-to-Peak Jitter12M1R 12 MHz Period Jitter (IMO) Root Mean Squared FMAX Maximum Frequency of Signal on Row Input or Row Output TRAMP Supply Ramp Time 0.90 0 3 12 3.12a 12.5a,b MHz MHz 0.6 1 1.5 kHz 40 – 50 340 60 – % ps – – 600 ps – – 12.5 MHz 0 – – µs FIMO6 Internal Main Oscillator Frequency for 6 MHz FCPU1 FBLK27 a. Accuracy derived from Internal Main Oscillator with appropriate trim for HVdd range. b. See the individual user module data sheets for information on maximum frequencies for user modules. The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.22 3.0V and 36V AC GPIO Specifications Parameter Description FGPIO GPIO Operating Frequency TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF TFallF Fall Time, Normal Strong Mode, Cload = 50 pF TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF TFallS Fall Time, Slow Strong Mode, Cload = 50 pF Document 38-12034 Rev. *C Conditions Normal Strong Mode. HVdd = 4.5 to 5.25V, 10% - 90%. Min. 0 3 Typ. – – Max. 12.5 18 Units MHz ns HVdd = 4.5 to 5.25V, 10% - 90%. 2 – 18 ns HVdd = 3 to 5.25V, 10% - 90%. 10 27 – ns HVdd = 3 to 5.25V, 10% - 90%. 10 22 – ns Page 28 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 8.23 2.5V to 3.0V AC GPIO Specifications Parameter Description FGPIO GPIO Operating Frequency TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF TFallF Fall Time, Normal Strong Mode, Cload = 50 pF TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF TFallS Fall Time, Slow Strong Mode, Cload = 50 pF Conditions Normal Strong Mode. HVdd = 2.5 to 3.0V, 10% - 90%. Min. 0 6 Typ. – – Max. 3.12 50 Units MHz ns HVdd = 2.5 to 3.0V, 10% - 90%. 6 – 50 ns HVdd = 2.5 to 3.0V, 10% - 90%. 18 40 120 ns HVdd = 2.5 to 3.0V, 10% - 90%. 18 40 120 ns 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Figure 8-2. GPIO Timing Diagram The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.24 AC High Voltage Output Specifications Parameter Description FHVO High Voltage Output Operating Frequency TRISE TFALL Document 38-12034 Rev. *C Conditions Min. – Typ. – Max. 1.04 Units MHz – – – – 200 200 ns ns Page 29 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.25 AC Comparator Specifications Parameter Description TRSYNC27 Response Time in Synchronous Mode (50 mV Overdrive) TRSYNC36 Response Time in Synchronous Mode (50 mV Overdrive) TR27 Response Time (50 mV Overdrive) TR36 Response Time (50 mV Overdrive) Response Time in Low Power TRLP27 TRLP36 Response Time in Low Power Conditions HVdd = 2.5V to 3.0V. Output clocked at 12 MHz. HVdd = 3.0V to 36V. Output clocked at 24 MHz. HVdd = 2.5V to 3.0V. Min. – Typ. 84 Max. – Units ns – 42 – ns – – 200 ns HVdd = 3.0V to 36V. – – 100 ns HVdd = 2.5V to 3.0V HVdd = 3.0V to 36V – – – – 400 200 ns ns The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.26 AC Analog-to-Digital Converter Specifications Parameter Description Sample Ratea, b 8-Bit Sample Rateb Conditions 12 bits to 6 bits at 6 MHz. Min. 1.46 – Typ. – 23.4 Max. 93.75 – Units Ksps Ksps a. Dependent on clock frequency and bit resolution. See individual user module data sheets. b. For HVdd = 2.5V to 3.0V, sample rates are halved. Bit BPEN in the AC0_CLK register must be set to 1. Document 38-12034 Rev. *C Page 30 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.27 3.0V to 36V AC Digital Block Specifications Parameter Description Timer Capture Pulse Width Maximum Frequency (Capture Not Used) Maximum Frequency (With or Without Capture) Counter Enable Pulse Width Maximum Frequency (Enable Not Used) Maximum Frequency (With or Without Enable Input) PWM Maximum Frequency (Enable Not Used) Maximum Frequency (With or Without Enable Input) Deadband Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency Conditions 4.75V < HVdd < 36V. Min. 50a – Typ. – – Max. – 49.9 Units ns MHz 3.0V < HVdd < 36V. – – 25.0 MHz 4.75V < HVdd < 36V. 50a – – – – 49.9 ns MHz 3.0V < HVdd < 36V. – – 25.0 MHz 4.75V < HVdd < 36V. – – 49.9 MHz 3.0V < HVdd < 36V. – – 25.0 MHz 4.75V < HVdd < 36V. 3.0V < HVdd < 36V. 20 50a 50a – – – – – – – – – – 49.9 25.0 ns ns ns MHz MHz a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). 8.28 2.5V to 3.0V AC Digital Block Specifications Parameter Description Timer Capture Pulse Width Maximum Frequency Counter Enable Pulse Width Maximum Frequency PWM Maximum Frequency Deadband Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency Conditions Min. 100a – 100a – – Typ. – – – – – Max. – 12.5 – 12.5 12.5 Units ns MHz ns MHz MHz 20 100a 100a – – – – – – – – 12.5 ns ns ns MHz a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document 38-12034 Rev. *C Page 31 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.29 4.75V to 36V AC Gate Drive, Linear Output Specifications Parameter Description BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Conditions Min. 0.8 Typ. – Max. – Units MHz Min. 0.7 Typ. – Max. – Units MHz 200 – – kHz Min. 0.6 Typ. – Max. – Units MHz 180 – – kHz 8.30 3.0V to 5.0V AC Gate Drive, Linear Output Specifications Parameter Description BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Conditions 8.31 2.5V to 3.0V AC Gate Drive, Linear Output Specifications Parameter Description BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Conditions The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.32 4.75V to 36V AC Gate Drive, PWM Output Specifications Parameter Description FMAX TROB Rise Time 10% to 90%, 5V Step, 100pF Load TFOB Fall Time 10% to 90%, 5V Step, 100pF Load Document 38-12034 Rev. *C Conditions Min. – – Typ. – – Max. 2 50 Units MHz ns – – 50 ns Page 32 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 8.33 3.0V to 5.0V AC Gate Drive, PWM Output Specifications Parameter Description FMAX TROB Rise Time 10% to 90%, 5V Step, 100pF Load TFOB Fall Time 10% to 90%, 5V Step, 100pF Load Conditions Min. – – Typ. – – Max. 1 130 Units MHz ns – – 60 ns Min. – – Typ. – – Max. 0.5 360 Units MHz ns – – 60 ns 8.34 2.5V to 3.0V AC Gate Drive, PWM Output Specifications Parameter Description FMAX TROB Rise Time 10% to 90%, 5V Step, 100pF Load TFOB Fall Time 10% to 90%, 5V Step, 100pF Load Conditions The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.35 4.75V to 36V AC External Clock Specifications Parameter FOSCEXT – – – Description Frequency High Period Low Period Power Up IMO to Switch Conditions Min. 0.090 20.6 20.6 150 Typ. – – – – Max. 25.0 5300 – – Units MHz ns ns µs Min. 0.090 Typ. – Max. 12.5 Units MHz 0.180 – 25.0 MHz 41.7 – 5300 ns 41.7 – – ns 150 – – µs 8.36 3.0V to 5.0V AC External Clock Specifications Parameter Description FOSCEXT Frequency with CPU Clock divide by 1a Frequency with CPU Clock FOSCEXT divide by 2 or greaterb – High Period with CPU Clock divide by 1 – Low Period with CPU Clock divide by 1 – Power Up IMO to Switch Conditions a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. Document 38-12034 Rev. *C Page 33 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 8.37 2.5V to 3.0V AC External Clock Specifications Parameter Description FOSCEXT Frequency with CPU Clock divide by 1a Frequency with CPU Clock FOSCEXT divide by 4 or greaterb – High Period with CPU Clock divide by 1 – Low Period with CPU Clock divide by 1 – Power Up IMO to Switch Conditions Min. 0.090 Typ. – Max. 3.12 Units MHz 0.180 – 12.5 MHz 41.7 – 5300 ns 41.7 – – ns 150 – – µs a. Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 4 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.38 AC Programming Specifications Parameter Description Conditions TRSCLK Rise Time of SCLK TFSCLK Fall Time of SCLK TSSCLK Data Set up Time to Falling Edge of SCLK THSCLK Data Hold Time from Falling Edge of SCLK FSCLK Frequency of SCLK TERASEB Flash Erase Time (Block) TWRITE Flash Block Write Time TDSCLK Data Out Delay from Falling HVdd > 3.6. Edge of SCLK TDSCLK3 Data Out Delay from Falling 3.0 ≤ HVdd ≤ 3.6. Edge of SCLK TDSCLK2 Data Out Delay from Falling 2.5 ≤ HVdd ≤ 3.0. Edge of SCLK Document 38-12034 Rev. *C Min. 1 1 40 Typ. – – – Max. 20 20 – Units ns ns ns 40 – – ns 0 – – – – 20 20 – 8 – – 45 MHz ms ms ns – – 50 ns – – 70 ns Page 34 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.39 3.0V to 36V AC Characteristics of I2C SDA and SCL Pins Parameter Description FSCLI2C SCL Clock Frequency Hold Time (repeated) START THDSTAI2C Condition. After this period, the first clock pulse is generated. TLOWI2C LOW Period of the SCL Clock THIGHI2C HIGH Period of the SCL Clock Set-up Time for a Repeated TSUSTAI2C START Condition THDDATI2C Data Hold Time Data Set-up Time TSUDATI2C Set-up Time for STOP Condition TSUSTOI2C TBUFI2C Bus Free Time Between a STOP and START Condition Pulse Width of spikes are TSPI2C suppressed by the input filter. Conditions Standard Mode Min. Max. 0 100 4.0 – Fast Mode Min. Max. 0 400 0.6 – Units kHz µs 4.7 4.0 4.7 – – – 1.3 0.6 0.6 – – – µs µs µs 0 250 4.0 4.7 – – – – 0 100a 0.6 1.3 – – – – µs ns µs µs – – 0 50 ns a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document 38-12034 Rev. *C Page 35 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40°C ≤ TA ≤ 85°C (referred to as 5V operation), 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C (referred to as 3.3V operation), or 2.5V to 3.0V and -40°C ≤ TA ≤ 85°C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 8.40 2.5V to 3.0V AC Characteristics of I2C SDA and SCL Pins (Fast Mode not Supported) Parameter Description FSCLI2C SCL Clock Frequency Hold Time (repeated) START THDSTAI2C Condition. After this period, the first clock pulse is generated. TLOWI2C LOW Period of the SCL Clock THIGHI2C HIGH Period of the SCL Clock Set-up Time for a Repeated TSUSTAI2C START Condition THDDATI2C Data Hold Time Data Set-up Time TSUDATI2C Set-up Time for STOP Condition TSUSTOI2C TBUFI2C Bus Free Time Between a STOP and START Condition Standard Mode Min. Max. 0 100 4.0 – Conditions SDA TLOWI2C TSUDATI2C THDSTAI2C Units kHz µs 4.7 4.0 4.7 – – – µs µs µs 0 250 4.0 4.7 – – – – µs ns µs µs TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Figure 8-3. Definition for Timing for Fast/Standard Mode on the I2C Bus Document 38-12034 Rev. *C Page 36 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 9.0 Thermal Considerations The Power PSoC device can support a supply voltage up to 36V. An internal linear regulator provides the nominal 5 volts used to power the M8C processor and other internal resources. Because regulating to a lower voltage generates excess heat, care must be taken to not exceed the maximum junction temperature of the PSoC device when using higher supply voltages. The junction temperature depends on the ambient temperature, the amount of power being dissipated in the device and the thermal resistance (θJA) of the package. In Linear Power PSoC devices, dissipated power can be broken into four sources: the PSoC core (CPU, PSoC blocks and system resources), the General Purpose Inputs/Outputs (GPIO), and the Gate Drive outputs (GD). The equation for junction temperature is shown in Equation 1, where θJA is the thermal resistance of the device package. TJ = TA + θJA * (PCore + PGPIO + PGD) However, HVdd - VOH can be quite large and current sourced by GPIO must be looked at carefully when using HVdd voltages greater than 5V. The equation for GPIO power dissipation is shown in Equation 3, where ISink is the total current being sunk by GPIO pins, and ISource is the total current being sourced by GPIO pins. PGPIO = VOL * ISink + (HVdd - VOH) * ISource Equation 3 The power dissipated by the high voltage Gate Drives (GD0 and GD1) is divided into a current sink and current source element. With the GD pins, the (HVdd - VOHGD) component is relatively small and the VOLGD component can be large (approximately HVdd - 5V). Therefore, with the GD pins, care must be taken to consider the effects of sinking currents. The equation for GD power dissipation is shown in Equation 4, where ISinkGD is the total current sunk by the GD pins, and ISourceGD is the total current sourced by the GD pins. Equation 1 PGD = VOLGD * ISinkGD + (HVdd - VOHGD) * ISourceGD The core power dissipated in the PSoC is the supply voltage (HVdd) times the combined current of: the CPU, digital blocks, analog blocks and system resources (Idd). The equation for the PSoC core power dissipation is: PCore = HVdd * Idd Equation 2 The power dissipated in the PSoC due to the GPIO can be divided into two elements: current being sourced and current being sunk. Because VOL is a relatively small value (less than 1V), the sinking current will not be a major contributor to heat in the Power PSoC. Equation 4 The following figures show the effects of supply voltage and current on the temperature of the PSoC. Figure 9-1a shows the maximum current with a varied supply voltage at an ambient temperature of 70°C and Figure 9-1b shows the maximum current with a varied supply voltage at an ambient temperature of 85°C. The PSoC model used assumes Idd = 5mA and all other current is sourced by GPIO. Each curve in the figures shows the maximum ISource that can be tolerated (TJ remains below the maximum limit) at various supply voltages between 2.5V and 36V, for a specific package. The maximum current is clipped at 85 mA due to drive limitations on the GPIO pins. The four package types available with Linear Power PSoC devices are shown. Thermal resistance (θJA) for the packages can be found in Section 9.1 on page 38. 90 90 80 80 32-pin MLF 70 Idd + IGPIO Idd + IGPIO 70 60 50 16-pin SOIC 40 32-pin MLF 60 50 40 16-pin SOIC 16-pin TSSOP 30 30 20 20 16-pin TSSOP 8-pin SOIC 8-pin SOIC 10 10 0 0 0 10 20 HVdd 30 Figure 9-1a. Maximum Current vs. Supply Voltage by Package (70o Ambient) Document 38-12034 Rev. *C 0 10 20 HVdd 30 Figure 9-1b. Maximum Current vs. Supply Voltage by Package (85o Ambient) Page 37 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 9.1 Thermal Impedances per Package Typical θJA * 186 oC/W 124 oC/W 122 oC/W 22 oC/W Package 8 SOIC 16 SOIC 16 TSSOP 32 QFN * Thermal resistance from silicon junction to ambient (TJ = TA + POWER x θJA). 9.2 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Package Minimum Peak Temperature* Maximum Peak Temperature 8 SOIC 240oC 260oC 16 SOIC 240oC 260oC 16 TSSOP 240oC 260oC 32 QFN 240oC 260oC * Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. 10.0 CY8C42x23 PSoC Device Key Features and Ordering Information SRAM (Bytes) Temperature Range Power Blocks Digital Blocks Analog Channel Digital IO Pins HV GPO XRES Pin CY8C42123-24SXI 4K 256 -40°C to +85°C 2 4 2 4 0 No 8-Pin SOIC Tape and Reel CY8C42123-24SXIT 4K 256 -40°C to +85°C 2 4 2 4 0 No 16-Pin SOIC CY8C42223-24SXI 4K 256 -40°C to +85°C 2 4 2 8 2 No 16-Pin SOIC Tape and Reel CY8C42223-24SXIT 4K 256 -40°C to +85°C 2 4 2 8 2 No No Ordering Code 8-Pin SOIC Package Flash (Bytes) The following table lists the CY8C42x23 Power PSoC device’s key package features and ordering codes . 16-Pin TSSOP CY8C42323-24ZXI 4K 256 -40°C to +85°C 2 4 2 10 2 16-Pin TSSOP Tape and Reel CY8C42323-24ZXIT 4K 256 -40°C to +85°C 2 4 2 10 2 No 32-Pin QFN CY8C42423-24LFXI 4K 256 -40°C to +85°C 2 4 2 10 2 Yes 32-Pin QFN Tape and Reel CY8C42423-24LFXIT 4K 256 -40°C to +85°C 2 4 2 10 2 Yes 32-Pin OCD QFN* CY8C42000-24LFXI* 4K 256 -40°C to +85°C 2 4 2 10 2 Yes * This part may be used for in-circuit debugging. It is NOT available for production. Document 38-12034 Rev. *C Page 38 of 42 CY8C42123/CY8C42223 CY8C42323/CY8C42423 PRELIMINARY 11.0 Package Diagrams 51-85066-*C Figure 11-1. 8-Lead (150) SOIC PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0°~8° 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068-*B Figure 11-2. 16-Lead (150) SOIC Document 38-12034 Rev. *C Page 39 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 51-85091-*A Figure 11-3. 16-Lead (4x4 mm) TSSOP E-PAD X, Y for this product is 3.71 mm, 3.71 mm (+/-0.08 mm) 51-85188 *A Figure 11-4. 32-Lead (5x5 mm) QFN Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Document 38-12034 Rev. *C Page 40 of 42 PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134 Phone: 408.943.2600 Web Sites: Company Information – http://www.cypress.com Sales – http://www.cypress.com/aboutus/sales_locations.cfm Technical Support – http://www.cypress.com/support/login.cfm Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation and “Programmable Systemon-Chip,” PSoC, PSoC Designer, and PSoC Express are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its PSoC family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products. Document 38-12034 Rev. *C Page 41 of 42 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY8C42123/CY8C42223 CY8C42323/CY8C42423 Document History Page Description Title: CY8C42123, CY8C42223, CY8C42323, and CY8C42423 Power PSoC™ Devices Document Number: 38-12034 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 339515 See ECN ARI New data sheet. *A 391130 See ECN HMT Update for PR3 Cypress “Preliminary” requirements. (Parts, pinouts, diagrams, specs., etc.) *B 394530 See ECN HMT Change pin 13 to P1[0]I2C*. Change pin 14 to NC. Change pin 25 to DNU. *C 406740 See ECN HMT Update White LED application diagram. Add RATTEN to the DC Linear Control Specifications table. Add CY corporate address on Information page. Implement CY standard QFN package terminology. Document 38-12034 Rev. *C Page 42 of 42