ACE ACE24LC02BN+ Two-wire serial eeprom Datasheet

ACE24LC02BN+
Technology
Two-wire Serial EEPROM
Description
The ACE24LC02BN+ provides low operation voltage of 2048 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is optimized for
use in many industrial and commercial applications where low-power and low-voltage operations are
essential.
Features
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Low Operation Voltage: Vcc=1.7V to 3.6V
Internally Organized: 256x/(2K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1MHz (3.6V,2.7V,2.5V) and 400 kHz (1.7V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page(02)
Partial Page Writes are Allowed
Self-timed Write Cycle (5 ms max)
High-reliability - Endurance: 1,000,000 Write Cycles
- Data Retention: 100 Years
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SOT-23-5 RoHS compliant Packages
z Wafer Sales: available in inked wafer Form
Absolute Maximum Ratings
Operating Temperature
-55℃ to +125℃
Storage Temperature
-65℃ to +150℃
Voltage on Any Pin with Respect to Ground -1.0V to +7.0V
Maximum Operating Voltage ACE24C02
6.25V
DC Output Current
5.0 mA
*Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
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ACE24LC02BN+
Technology
Two-wire Serial EEPROM
Packaging Type
SOT-23-5
WP
SCL
Vcc
GND
SDA
Pin Configurations
Pin Name
Function
A0~A2
Device Address Inputs
SDA
Serial Data Input / Output
SCL
Serial Clock Input
WP
Write Protect
VCC
Power Supply
GND
Ground
Block Diagram
Figure 1
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Two-wire Serial EEPROM
Ordering information
Selection Guide
ACE24LC02 XX
+
X
H
Halogen-free
U : Tube
T : Tape and Reel
Pb - free
BN : SOT-23-5
Serial Clock (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock
data out of each device.
Serial Data (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device/Page Addresses (A2, A1, A0):
The A2, A1 and A0 pins are device address inputs that are hard wired for the ACE24LC02, As many as
eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail
under the Device Addressing section).
Write Protect (WP):
The ACE24LC02 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows
normal read/write operations when connected to ground (GND). When the Write Protect pin is conceded to Vcc
the write protection feature is enabled.
Write Protect Description
WP Pin Status
Part of the Array Protected
ACE24LC02
WP=VCC
Full (2K) Array
WP=GND
Normal Read / Write Operations
Memory Organization
ACE24LC02, 2K SERIAL EEPROM:
Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for
random word addressing.
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Two-wire Serial EEPROM
Technology
Pin Capacitance
Applicable over recommended operating range from: TA = 25℃, f = 1.0 MHz, VCC = +1.7V.
Symbol
Test Condition
Max
Units
Conditions
CI/O 1
Input / Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
CIN
1
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +3.6V, (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Units
3.6
V
VCC
Supply Voltage
ICC1
Supply Current
VCC = 3.6V, Read at 400K
0.4
1.0
mA
ICC2
Supply Current
VCC = 3.6V, Write at 400K
2.0
3.0
mA
ISB1
Standby Current
VCC = 1.7V, VIN = VCC/ VSS
1.0
µA
ISB2
Standby Current
VCC = 3.6V, VIN = VCC/ VSS
3.0
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL1
Input Low Level
VIH1
Input High Level
VOL1
Output Low Level
VOL2
Output Low Level
1.7
Max
VIN = VCC/VSS
0.10
3.0
µA
VOUT = VCC/ VSS
0.05
3.0
µA
-0.6
VCCx0.3
V
VCCx0.7
5.5
V
VCC = 3.0V, IOL = 2.1 mA
0.4
V
VCC = 1.7V, IOL = 0.15 mA
0.2
V
Note: 1. VIL min and VIH max are reference only and are not tested.
AC Characteristics
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +3.6V, CL = 1 TTL Gate and 100
pF (unless otherwise noted). Test conditions are listed in Note 2.
1.7-volt
2.5-volt
3.6-volt
Symbol
Parameter
fSCL
Clock Frequency, SCL
TLOW
Clock Pulse Width Low
1.3
0.4
0.4
µs
THIGH
Clock Pulse Width High
0.6
0.4
0.4
µs
TAA
Clock Low to Data Out Valid
TBUF1
Time the bus must be free before a new
transmission can Start
Min Max Min Max Min Max
400
1000
1000
Units
kHz
0.1 0.9 0.05 0.55 0.05 0.55
µs
1.2
0.5
0.5
µs
THD.STA
Start Hold Time
0.6
0.25
0.25
µs
TSU.STA
Start Setup Time
0.6
0.25
0.25
µs
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Two-wire Serial EEPROM
THD.DAT
Data In Hold Time
0
0
0
µs
TSU.DAT
Data In Setup Time
100
100
100
ns
TR
Inputs Rise Time
0.3
0.3
0.3
µs
TF
Inputs Fall Time
300
100
100
ns
TSU.STO
Stop Setup Time
0.6
0.25
0.25
µs
TDH
Data Out Hold Time
50
50
50
ns
TWR
Write Cycle Time
Endurance1
3.3V, 25℃, Page Mode
5
5
1,000,000
5
ms
Write
Cycles
Notes:1. This parameter is characterized and not 100% tested.
2.AC measurement conditions:
RL (connects to Vcc): 1.3kΩω (2.5V, 3.6V), 10kΩ (1.7V)
Input pulse voltages: 0.3 Vcc to 0.7 Vcc
Input rise and fall times: ≦50 ns
Input and output timing reference voltages: 0.5Vcc
Device Operation
Clock and Data Transitions:
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only
during SCL low time periods (refer to Figure 4). Data changes during SCL high periods will indicate a
start or stop condition as defined below.
Start Condition:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (refer to Figure 5).
Stop Condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Figure 5).
Acknowledge:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. The
happens during the ninth clock cycle. Following receipt each word from the EEPROM, the
microcontroller should send a zero to EEPROM and continue to output the next data word or send a
stop condition to finish the read cycle.
Standby Mode :
The ACE24LC02 features a low-power standby mode which is enabled: (a) upon power-up and (b) after
the receipt of the stop bit and the completion of any internal operations.
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Two-wire Serial EEPROM
Device Reset :
After an interruption in protocol power loss or system reset, any two-wire part can be protocol reset by following
these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high and then.
3. Create a start condition.
Bus Timing
Figure 2．SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 3．SCL: Serial Clock, SDA: Serial Data I/O
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
Figure 4．Data Validity
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Two-wire Serial EEPROM
Figure 5．Start and Stop Definition
Figure 6．Output Acknowledge
Device Addressing
The 2K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (refer to Figure 7).
The device address word consists of a mandatory one, zero sequence for the first four most
significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must
compare to their corresponding hard-wired input pins (The A2, A1 and A0 device address bits are “0”
for the 2K EEPROM of SOT-23-5 package).
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the
chip will return to a standby state.
Write Operations
Byte Write:
A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a
zero and the addressing device, such as a microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (refer to Figure 8).
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Page Write:
The 2K EEPROM is capable of an 8-byte page write, devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the
first data word, the microcontroller can transmit up to seven (2K) or fifteen more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must terminate the
page write sequence with a stop condition (refer to Figure 9).
The data word address lower three (2K) or four bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the following
byte is placed at the beginning of the same page. If more than eight (2K) or sixteen data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
Acknowledge Polling:
Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge
polling can be initiated. This involves sending a start condition followed by the device address word.
The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
Read Operations:
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to one. There are three read operations: current address
read, random address read and sequential read.
Current Address Read:
The internal data word address counter maintains the last address accessed during the last read or
write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address “roll over” during read is from the last byte of the last memory page
to the first byte of the first page. The address “roll over” during write is from the last byte of the current
page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is serially clocked out. The microcontroller does not
respond with an input zero but does generate a following stop condition (refer to Figure 10).
Random Read:
A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current
address read by sending a device address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out the data word. The microcontroller does not
respond with a zero but does generate a following stop condition (refer to Figure 11).
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Sequential Read:
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM
receives an acknowledge, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address limit (2K,8K,16K) is reached, the data word address
will “roll over” and the sequential read will continue. The sequential read operation is terminated when
the microcontroller does not respond with a zero but does generate a following stop condition (refer to
Figure 12).
2K
MSB
LSB
Figure 7．Device Address
Figure 8．Byte Write
Figure 9．Page Write
Figure 10．Current Address Read
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Two-wire Serial EEPROM
Figure 11． Random Read
Figure 12． Sequential Read
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Technology
Packaging information
SOT-23-5
*Control Dimensions: Millimeter
Symbol
A
A1
A2
b
c
D
E1
E
e
e1
L
θ
Millimeter
Min.
0.700
0.000
0.700
0.350
0.080
2.820
1.600
2.650
Max.
0.900
0.100
0.800
0.500
0.200
3.020
1.700
2.950
0.950(BSC)
1.900(BSC)
0.300
。
0
0.600
。
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Two-wire Serial EEPROM
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
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