Fairchild ML6554 3a bus termination regulator Datasheet

www.fairchildsemi.com
ML6554
3A Bus Termination Regulator
Features
Description
• Can source and sink up to 3A, no heat sink required
• Integrated Power MOSFETs
• Generates termination voltages for DDR SDRAM,
SSTL-2 SDRAM, SGRAM, or equivalent memories
• Generates termination voltages for active termination
schemes for DDR SDRAM, GTL+, Rambus, VME,
LV-TTL, HSTL, PECL and other high speed logic
• VREF input available for external voltage divider
• Separate voltages for VCCQ and PVDD
• Buffered VREF output
• VOUT of ±3% or less at 3A
• Minimum external components
• Shutdown for standby or suspend mode operation
• 0° to +70°C and -40° to +85°C temperature ranges
available
• Thermal Shutdown ≈ 130ºC
The ML6554 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output
voltage or termination voltage for various applications. The
ML6554 can be implemented to produce regulated output
voltages in two different modes. In the default mode, when
the VREF pin is open, the ML6554 output voltage is 50% of
the voltage applied to VCCQ. The ML6554 can also be used
to produce various user-defined voltages by forcing a voltage
on the VREFIN pin. In this case, the output voltage follows
the input VREFIN voltage. The switching regulator is capable of sourcing or sinking up to 3A of current while regulating an output VTT voltage to within 3% or less.
The ML6554, used in conjunction with series termination
resisitors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator can
be used as a termination voltage for other bus interface
standards such as DDR SDRAM, SSTL, CMOS, Rambus™,
GTL+, VME, LV-CMOS, LV-TTL, HSTL and PECL.
Block Diagram
15
VCCQ
16
AVCC
14
1
VREFOUT
9
VDD
12
VDD
SHDN
2
PVDD1
7
PVDD2
VL1
(VOUT)
OSCILLATOR/
RAMP
GENERATOR
3
–
200kΩ
S
+
VREF BUFFER
Q
6
VL2
(VOUT)
–
R
Q
+
VREFIN
11
+
200kΩ
AGND
–
ERROR AMP
RAMP
COMPARATOR
13
VFB
10
DGND
8
PGND2
PGND1
4
5
REV. 1.1.3 3/8/02
ML6554
PRODUCT SPECIFICATION
Pin Configuration
ML6554
16-Pin PSOP (U16)
VDD
1
16
AVCC
PVDD1
2
15
VCCQ
VL1
3
14
VREFOUT
PGND1
4
13
AGND
PGND2
5
12
SHDN
VL2
6
11
VREFIN
PVDD2
7
10
VFB
DGND
8
9
VDD
TOP VIEW
Pin Description
2
Pin
Name
Function
1
VDD
2
PVDD1
3
VL1
Output voltage/ inductor connection
4
PGND1
Ground for output power transistors
5
PGND2
Ground for output power transistors
6
VL2
Output voltage/inductor connection
7
PVDD2
Voltage supply for internal power transistors
8
DGND
Digital ground
Digital supply voltage
Voltage supply for internal power transistors
9
VDD
Digital supply voltage
10
VFB
Input for external compensation feedback
11
VREFIN
12
SHDN
Shutdown active low. CMOS input level
13
AGND
Ground for internal reference voltage divider
Input for external reference voltage
14
VREFOUT
15
VCCQ
Voltage reference for internal voltage divider
16
AVCC
Analog voltage supply
Reference voltage output
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
PVDD
Voltage on Any Other Pin
Average Switch Current (IAVG)
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance (θJC)(Note 2)
Output Current, Source or Sink
Min.
GND – 0.3
-65
Max.
4.5
VIN + 0.3
3.0
150
150
150
2
3.0
Units
V
V
A
°C
°C
°C
°C/W
A
Max.
70
+85
4.0
4.0
Units
°C
°C
V
V
Operating Conditions
Parameter
Temperature Range, CU suffix
Temperature Range, IU suffix
PVDD Operating Range
VCCQ Operating Range
Min.
0
-40
2.0
1.4
Electrical Characteristics
Unless otherwise specified, AVCC = VDD = PVDD = 3.3V ±10%, TA = Operating Temperature Range (Note 1)
Symbol
Parameter
Switching Regulator
VTT
Output Voltage, SSTL_2
(See Figure 1)
Conditions
IOUT = 0,
VREF = open
IOUT = ±3A,
VREF = open
Internal Resistor Divider
IOUT = 0
ZIN
VREF Reference Pin Input
Impedance
Switching Frequency
Offset Voltage VTT – VREFOUT
AVCC = 2.5V No Load VCCQ = 2.5
Buffer
IREF
Output Load Current
Typ.
Max. Units
VCCQ = 2.3V 1.12 1.15 1.18
VCCQ = 2.5V 1.22 1.25 1.28
VCCQ = 2.7V 1.32 1.35 1.38
VCCQ = 2.3V 1.09 1.15 1.21
VCCQ = 2.5V 1.19 1.25 1.31
VCCQ = 2.7V 1.28 1.35 1.42
VCCQ = 2.3V 1.139 1.15 1.162
VCCQ = 2.5V 1.238 1.25 1.263
VCCQ = 2.7V 1.337 1.35 1.364
VCCQ = 0
100
VREFOUT
∆VOFFSET
Supply
IQ
Quiescent Current
Min.
650
IOUT = 0, no load
VCCQ = 2.5V
–20
IVCCQ
IAVCC
IAVCC SD
IVDD
IVDD SD
IPVDD
6
0.5
0.2
0.25
0.2
100
3
V
V
V
V
V
V
V
V
V
kΩ
20
kHz
mV
10
1.0
0.5
1.0
1.0
250
µA
mA
mA
mA
mA
µA
mA
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Infinite heat sink
REV. 1.1.3 3/8/02
3
ML6554
PRODUCT SPECIFICATION
Functional Description
This switching regulator is capable of sinking and sourcing
3A of current without an external heatsink. The ML6554
uses a power surface mount package (PSOP) that includes
an integrated heat slug. The heat can be piped through the
bottom of the device and onto the PCB (Figure 1).
The ML6554 integrates two power MOSFETs that can be
used to source and sink 3A of current while maintaining a
tight voltage regulation. Using the external feedback, the
output can be regulated well within 3% or less, depending on
the external components chosen. Separate voltage supply
inputs have been added to accommodate applications with
various power supplies for the databus and power buses, see
Figure 2.
Output voltage can also be selected by forcing a voltage at
the VREFIN pin. In this case, the output voltage follows the
voltage at the VREFIN input. Simple voltage dividers can be
used this case to produce a wide variety of output voltages
between 0.7V and VDD–0.7V.
VREF Input and Output
The VREFIN input can be used to force a voltage at the
outputs (Inputs section, above). The VREFOUT pin is an
output pin that is driven by a small output buffer to provide
the VREF signal to other devices in the system. The output
buffer is capable of driving several output loads. The output
buffer can handle 3mA.
Other Supply Voltages
Several inputs are provide for the supply voltages: PVDD1,
PVDD2, AVCC, and VDD.
Outputs
The output voltage pins (VL1, VL2) are tied to the databus,
address, or clock lines via an external inductor. See the
Applications section for recommendations. Output voltage
is determined by the VCCQ or VREFIN inputs.
Inputs
The input voltage pins (VCCQ or VREFIN) determine the
output voltages (VL1 or VL2) . In the default mode, where
the VREFIN pin is floating, the output voltage is 50% of the
VCCQ input. VCCQ can be the reference voltage for the
databus.
The PVDD1 and PVDD2 provide the power supply to the
power MOSFETs. VDD provides the voltage supply to the
digital sections, while AVCC supplies the voltage for the
analog sections. Again, see the Applications section for
recommendations.
Feedback Input
The VFB pin is an input that can be used for closed loop
compensation. This input is derived from the voltage output.
See application section for recommendation.
HEAT SLUG
Figure 1. Cutaway view of PSOP Package
4
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Applications
Power Handling Capability of the PSOP
Package
Using the ML6554 for SSTL Bus Termination
Using the board layout shown in Figures 6, 7, and 8; soldering the ML6554 to the board at zero LFPM the temperature
around the package measured 55ºC for 3A loads. Note that a
1 ounce copper plane was used in the board construction.
The circuit schematic in Figure 2 shows a recommended
approach for constructing a bus terminating solution for an
SSTL-2 bus. This circuit can be used in PC memory and
Graphics memory applications as shown in Figures 4 and 5.
Note that the ML6554 can provide the voltage reference
(VREF) and terminating voltages (VTT). Using the layout
as shown in Figures 6, 7, and 8, and measuring the VTT
performance using the test setup as described in Figure 9,
the ML6554 delivered a VTT ± 20mV for 1A to 3A loads
(see Figure 10). Table 1 provides a recommended parts list
for the circuit in Figure 2.
Airflow is not likely to be needed in the operation of this
device (assuming a board layout similar to that described
above). The power handling performance of the PSOP
package is shown by a study of the package manufacturer for
various airflow vs. θJA conditions in Figure 11.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination VREF
& VTT requirements. The ML6554 can be used for those
applications.
2.5V TO 4V
C8 0.1µF
R2 100Ω
C9 0.1µF
R1 100Ω
C5
330µF
R3
100kΩ
C6
330µF
U1
ML6554
1
TPI
2
L1 3.3µH C3 0.1µF
VTT
C1
820µF
F2V
OS-CON
4
5
C2
0.1µF
C4 0.1µF
TO SDRAMS
3
6
7
8
VDD
AVCC
PVDD1
VCCQ
VL1
VREFOUT
PGND1
AGND
PGND2
SHDN
VL2
VREFIN
PVDD2
VFB
DGND
VDD
16
15
14
VCCQ
VREFOUT
13
12
11
SHDN
VREFIN
10
9
R4 100kΩ
R5 1kΩ
GND
C7 1nF
GND
Figure 2.
REV. 1.1.3 3/8/02
5
ML6554
PRODUCT SPECIFICATION
2.5V TO 4V
C5
330µF
R3
100kΩ
U1
ML6554
1
C3 10µF
2
L1 3.3µH
VTT
C1
820µF
F2V
OS-CON
3
4
5
C2
0.1µF
6
TO SDRAMS
7
8
VDD
AVCC
PVDD1
VCCQ
VL1
VREFOUT
PGND1
AGND
PGND2
SHDN
VL2
C6
330µF
VREFIN
PVDD2
VFB
DGND
VDD
16
15
14
VCCQ
VREFOUT
13
12
11
SHDN
VREFIN
10
9
R1 100kΩ
R2 1kΩ
C4 1nF
GND
GND
Figure 3. Alternate Application Circuit
An alternate application circuit for the ML6554 is shown in
Figure 3. The number of external components is reduced
compared to the circuit in Figure 2. This is achieved by
replacing four, 0.1µF bypass capacitors with one, low ESR,
10µF ceramic capacitor placed right next to U1. Two 100Ω
resistors are also eliminated. High value, surface-mount
6
MLC capacitors were not available when the original application circuit (Figure 2) was developed. Both application
circuits offer the same electrical performance but that shown
in Figure 2 has a reduced bill-of-materials. Table 2 shows the
recommended parts list for the circuit of Figure 3.
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
168/184/208-PIN DIMM CONNECTORS
AND SDRAM/SGRAM MODULES
TERMINATION
RESISTORS
PC CHIP SET
NORTHBRIDGE
DATA LINE, CLOCK LINES,
ADDRESS LINES, CONTROL LINES
TERMINATION
RESISTORS
VTT
ML6554
VREF
Figure 4. Complete Termination Solution PC Main Memory (PC Motherboard)
SO DIMM
AND MODULES
3D
GRAPHIC CHIP
TERMINATION
RESISTORS
SGRAM
DATA LINE, CLOCK LINES,
ADDRESS LINES, CONTROL LINES
TERMINATION
RESISTORS
VREF
ML6554
2.5V
VOLTAGE
REGULATOR
VTT
5V OR 3.3V
AGP/PCI BUS
Figure 5. Complete Termination Solution Graphics Memory Bus – AGP Graphics Cards
REV. 1.1.3 3/8/02
7
ML6554
PRODUCT SPECIFICATION
Figure 6. Top Silk
Figure 7. Top Layer
8
Figure 8. Bottom Layer
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
3.3V POWER
SUPPLY
V
A
ACTIVE
CLAMP
VDD
VCCQ
VCCQ
SUPPLY
ML6554
EVAL
VTT
CURRENT SOURCE/SINK
POWER SUPPLY
GND
V
ITT
A
Figure 9. Test Circuit Setup
VTT VARIANCE WITH VDD@ITT (VCCQ 2.5V)
TESTED WITH EVAL PCB
ITT
1.29
3A SINKING
2A SINKING
1.28
VTT (V)
1A SINKING
0A SINKING
1.27
3A SOURCING
2A SOURCING
1.26
2.0
2.5
3.0
3.5
4.0
1A SOURCING
VDD (V)
Figure 10. VTT Performance for SSTL-2 Bus
REV. 1.1.3 3/8/02
9
ML6554
PRODUCT SPECIFICATION
Table 1. Recommend Parts List for SSTL-2 Termination Circuit in Figure 2.
Item
Resistors
1
2
3
Capacitors
4
Qty
Description
Manufacturer / Part Number
Designator
2
1
2
100Ω1210 SMD
1kΩ 1210 SMD
100kΩ1210 SMD
Panasonic/ERJ-8ENF1000V
Panasonic/ERJ-8ENF1001V
Panasonic/ERJ-8ENF1003V
R1, R2
R5
R3, R4
3
0.1µF 1210 Film SMD
C2, C8, C9
5
6
7
8
1
2
1
2
820µF 2V Solid Elect. SMD
330µF Tant 6.3V 100mΩ
1nF 1210 Film SMD
0.1µF 0805 Film
Panasonic/ECV3VB1E104K
Panasonic/ECU-V1H104KBW
Sanyo/2SV820M Os Con
AVX/TPSE337M006R0100
Panasonic/ECU-V1H102KBM
Panasonic/ECJ-2VF1C104Z
9
1
ML6554 Bus Terminator
Power SOP Package
ML6554CU or ML6554IU
U1
Magnetics
10
1
3.3µH 5A inductor SMD
Coilcraft/D03316P-332HC
Pulse Eng./ P0751.332T
Gowanda/SMP3316-331M
XFMRS inc./XF0046-S4
L1
Other
11
12
1
1
Scope probe socket
12 Pin breakaway strip
Tektronics/131-4353-00
Sullins/PTC36SAAN (36 PINS)
TP1
I/O, standoffs
C1
C5, C6
C7
C3, C4
ICS
Table 2. Recommend Parts List for Figure 3.
Item
Resistors
1
2
Capacitors
3
Qty
Description
Manufacturer / Part Number
Designator
2
1
100kΩ 0805 SMD
1kΩ 0805 SMD
Panasonic/ERJ-8ENF1000V
Panasonic/ERJ-8ENF1000V
R1, R3
R2
1
0.1µF, 1210 Film SMD
C2
4
5
6
7
1
2
1
1
820µF 2V Solid Elect. SMD
330µF Tant 6.3V 100mΩ
1nF 1210 Film SMD
10µF 6.3V Ceramic
Panasonic/ECV3VB1E104K
Panasonic/ECU-V1H104KBW
Sanyo/2SV820M Os Con
AVX/TPSE337M006R0100
Panasonic/ECU-V1H102KBM
TDK/C2012X5R0J106M
8
1
ML6554 Bus Terminator
Power SOP Package
ML6554CU or ML6554IU
U1
Magnetics
9
1
3.3µH 5A inductor SMD
Coilcraft/D03316P-332HC
Pulse Eng./ P0751.332T
Gowanda/SMP3316-331M
XFMRS inc./XF0046-S4
L1
Other
10
11
1
1
Scope probe socket
12 Pin breakaway strip
Tektronics/131-4353-00
Sullins/PTC36SAAN (36 PINS)
TP1
I/O, standoffs
C1
C5, C6
C4
C3
ICS
10
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Vendor List
1. AVX
(207) 282-5111
2. Sanyo
(619) 661-6835
3. Tektronix
(408) 496-0800
4. Coilcraft
(847) 639-6400
5. Pulse
(800) 797-8573
6. Gowanda
(716) 532-2234
7. Xfmrs Inc.
(317) 834-1066
8. Panasonic
(714) 373-7366
9. Digikey
(800) 344-4539
60
40
40
θJA (ºC/W)
ΘJA (ºC/W)
60
20
20
16Ld PSOP2
2.3x3.1mm PAD
1.9mm DIE
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
16Ld PSOP2
2.3x3.1mm PAD
1.9mm DIE @ 0.8 WATTS
0
0
100
200
300
400
POWER (W)
AIR VELOCITY (LFPM)
NATURAL CONVECTION ΘJA TEST RESULTS
1.27mm PITCH PowerSOP™ 2
SLUG SOLDERED
FORCED CONVECTION ΘJA TEST RESULTS
1.27mm PITCH PowerSOP™ 2
SLUG SOLDERED
500
Figure 11. Graphical Results Summary – 1S2P Test Board
REV. 1.1.3 3/8/02
11
ML6554
PRODUCT SPECIFICATION
DRAWING NUMBER
ENG-CB-1007 REV A
Applicable Jedec Spec
JC 51-X (Note 1)
(Proposed Spec)
Substrate Material
FR-4
Dimensions (LxW) (Overall)
114.3 x 76.2mm
Dimensions (LxW) (Metallization)
55 x 65mm
Dimensions (LxW) (Inner Planes)
73 x 73mm
Thickness
1.6 mm
Pitch
1.27mm
Stackup (# Signal Layers, # Cu Planes)
1S2P
Cu Trace Coverage (Signal Layer)
12%
Cu Coverage (Internal Layer)
100%
Trace Width (Spec/Measured)
235.5±25.5/288µm
Trace Cu Thickness (Spec/Measured)
70±14/67µm
Inner Cu Thickness (Spec/Measured)
35±3.5/31µm
Build #
C1797
Note 1: Proposed Spec "Thermal Test Board with Two Internal Solid Copper Planes for leaded Surface Mount Packages".
Figure 12. Test Board Layout for ΘJA vs. Airflow
Table 3. Termination Solutions Summary By Buss Type
Bus
Description
Driving
Method
VDDQ
VTT
GTL+
Gunning
Transceiver
Bus Plus
Open Drain 5v or 3.3V 1.5V±10%
Note 10
Note12
SSTL_2
Series Stub
Terminated
Logic for 2V
Symmetric
Drive,
Series
Resistance
2.5V±10%
0.5x
(VDDQ)
±3%
RAMBUS
RAMBUS
Signaling
Logic
Open Drain
None
Specified
LV-TTL
Low Voltage
TTL Logic or
PECL or
3.3V VME
Symmetric
Drive
3.3±10%
12
VREF
1.0V±2%
Note 11
Fairchild
Solutions
Industry
System
Components
ML6554CU;
Mode: VREF
Input = 1.5V,
VCC = 5V
300 to 500MHz
Processor;
PC Chipsets;
GTLP 16xxx
Buffers;
Fairchild,
Texas Instr.
2.5V
ML6554CU
or ML6553CS;
Mode: VREF
Input = Floating
or Forced,
VCC = 3.3V
SSTL SDRAM;
Hitachi,
Fujitsu,
NEC, Micro,
Mitsubishi
2.5V
2.0V
ML6553CS;
Mode: VREF
Input = Open,
VCC = VDDQ
nDRAM,
RAMBUS,
Intel, Toshiba
VDDQ/2
3.3V
ML6553CS;
Mode: VREF
Input = Open,
VCC = VDDQ
Processors or
backplanes;
LV-TTL
SDRAM,
EDO RAM
REV. 1.1.3 3/8/02
PRODUCT SPECIFICATION
ML6554
Mechanical Dimensions
16-Pin PSOP
9.90 ± 0.10
A
0.60
8.89
1.95
16
9
B
3.90 ± 0.10
6.00
7.50
1.75
2.50
3.70
1
PIN ONE
INDICATOR
7.40
3.50
8
0.51
0.35
1.27
1.27
8.89
0.25 M C B A
(0.30)
LAND PATTERN RECOMMENDATION
1.75 MAX
SEE DETAIL A
+0.05
1.45 –0.20
C
0.25
0.19
0.10 C
+0.10
0.15 –0.05
(R0.10)
0.50
0.25 X 45°
GAGE PLANE
(R0.10)
8°
0°
0.36
0.70 ± 0.20
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS–012, VARIATION AC, ISSUE C,
DATED MAY 1990.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
REV. 1.1.3 3/8/02
13
ML6554
PRODUCT SPECIFICATION
Ordering Information
Part Number
Temperature Range
Package
ML6554CU
0°C to 70°C
16-Pin PSOP (U16)
ML6554IU
-40°C to +85°C
16-Pin PSOP (U16)
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
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