KEC K3520PQ-XH Common-drain dual n-channel enhancement mode field effect transistor Datasheet

SEMICONDUCTOR
K3520PQ-XH
TECHNICAL DATA
Common-Drain Dual N-Channel
Enhancement Mode Field Effect Transistor
General Description
The K3520PQ-XH is a Dual N-channel MOSFET designed for use as a
bi-directional load switch, facilitated by its common-drain configuration.
2000
S2
FEATURES
·Low on-state resistance
RDS(ON)1 = 16mΩ MAX (VGS=4.5V, IS=1.0A)
RDS(ON)2 = 17mΩ MAX (VGS=3.9V, IS=1.0A)
RDS(ON)3 = 20mΩ MAX (VGS=3.5V, IS=1.0A)
G2
1080
S1
G1
BOTTOM : COMMON DRAIN
_10 m
180 +
MAXIMUM RATING (Ta=25℃ Unless otherwise noted)
CHARACTERISTIC
SYMBOL
RATING
UNIT
Drain-Source Voltage
VDSS
24
V
Gate-Source Voltage
VGSS
±12
V
Storage Temperature Range
Tstg
-55~150
℃
Equivalent Circuit
D
G1
Rg
D
G2
S1
2010. 4. 29
Rg
S2
Revision No : 0
1/3
K3520PQ-XH
Electrical Characteristics (Ta=25℃ Unless otherwise noted)
CHARACTERISTIC
SYMBOL
TEST CONDITION
Drain to Source Breakdown Voltage
V(BR)DSS
ID = 250μA, VGS = 0V
Gate to Source Breakdown Voltage
V(BR)GSS
IG = ±100㎂, VDS = 0V
MIN
TYP
MAX
UNIT
24
-
-
V
±12
±14
-
V
Drain Cut-off Current
IDSS
VDS = 24V, VGS = 0V
-
-
1.0
㎂
Gate to Source Leakage Current
IGSS
VGS = ±12V, VDS = 0V
-
-
±10
㎂
Gate to Source Threshold Voltage
Vth
VDS=VGS, ID=250 A
0.5
1.1
1.5
V
VGS = 4.5V, ID = 1.0A
-
12.5
16.0
mΩ
VGS = 3.9V, ID = 1.0A
-
13.5
17.0
mΩ
VGS = 3.5V, ID = 1.0A
-
15.0
20.0
mΩ
f=1MHz
-
3.0
-
kΩ
-
600
-
-
115
-
RDS(on)
Drain to Source On Resistance
Gate Resistance
Rg
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
-
83
-
Total Gate Charge
Qg
-
6.0
-
Gate-Source Charge
Qgs
-
0.8
-
Gate-Drain Charge
Qgd
-
2.5
-
Source-Drain Forward Voltage
VSD
0.50
0.70
0.86
2010. 4. 29
Revision No : 0
VDS = 10V, VGS = 0V, f=1MHz
VDD=10V, VGS=3.9V, IS=4.0A
VGS = 0V, IS = 1.0A
pF
nC
V
2/3
K3520PQ-XH
DIE INFORMATION
2000
S2
G2
1080
S1
G1
BOTTOM : COMMON DRAIN
CONTENTS
VALUE
Wafer size
8 inch notch type
Wafer thickness
180um
Front Metal
Aℓ-4um
Back Metal
Ti/Ni/Ag-1.4um
Passivation Layer
Yes
Die Size (with scribe lane)
2000×1080㎛2
Scribe lane width
60㎛
Gate Pad Size
170×163㎛2
Die edge to gate Pad
93㎛
Die edge to Source Pad
70㎛
Gross Die(per Wafer)
13,470ea
2010. 4. 29
Revision No : 0
3/3
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