BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs 8k, 16k bit EEPROMs for direct connection to serial ports BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV The BR9080 and BR9016 series are serial EEPROMs that can be connected directly to a serial port and can be erased and written electrically. Writing and reading is performed in word units, using four types of operation commands. Communication occurs though CS, SK, DI, and DO pins, WC pin control is used to initiate a write disabled state, enabling these EEPROMs to be used as one-time ROMs. During writing, operation is checked via the internal status check. zApplications Movie, camera, cordless telephones, car stereos, VCRs, TVs, DIP switches, and other battery-powered equipment requiring low voltage and low current zFeatures 1) BR9080 / F / RFV (8k bit): 512 words ×16 bits BR9016 / F / RFV (16k bit): 1024 words × 16bits 2) Single power supply operation 3) Serial data input and output 4) Automatic erase-before-write 5) Low current consumption Active (5V) : 5mA (max.) Standby (5V) : 3µA (max.) 6) Noise filter built into SK pin 7) Write protection when VCC is low 8) Compact DIP8 / SOP8 / SSOP-B8 packages 9) High reliability CMOS process 10) 100,000 ERASE / WRITE cycles 11) 10 years Data Retention zBlock diagram R/B INSTRUCTION DECODE CS CONTROL DETECT SUPPLY VOLTAGE CLOCK GENERATION WRITE DISABLE SK DI DO INSTRACTION REGISTER ADD BUFFER 9bit ADD DECORDER HIGH VOLTAGE GENERATOR WC 9bit 8,192 bit EEPROM DATA REGISTER 16bit R/W AMPS 16bit BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs zPin descriptions VCC R/B WC GND WC CS SK DI DO R/B BR9016 : DIP8 GND DO VCC CS DI VCC SK CS BR9016F : SOP8 Pin name Function DIP / SSOP SOP 1 3 CS Chip Select Control 2 4 SK Serial Data Clock Input 3 5 DI Op code, address, Serial Data Input 4 6 DO Serial Data Output 5 7 GND Ground 0V 6 8 WC Write Control Input 7 1 R/B READY / BUSY Output 8 2 VCC Power supply zAbsolute maximum ratings (Ta=25°C) Parameter Supply voltage Power dissipation Symbol Limits VCC −0.3∼+7.0 Pd Unit DIP8 500∗1 SOP8 350∗2 SSOP-B8 300∗3 V mW Storage temperature Tstg −65∼+125 °C Operation temperature Topr −40∼+85 °C − −0.3∼VCC+0.3 V Input voltage ∗1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. zRecommended operating conditions (Ta=25°C) Parameter Power supply voltage Symbol WRITE VCC READ Input voltage VIN SK DI DO BR9016RFV : SSOP8 Fig.1 Pin No. R / B WC GND Min. Typ. Max. Unit 2.7 − 5.5 V 2.7 − 5.5 V 0 − VCC V BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs zElectrical characteristics BR9080 / F / RFV, BR9016 / F / RFV: 5V (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7V∼5.5V) Parameter Symbol Min. Typ. Max. Unit Conditions Input low level voltage 1 VIL1 − − 0.3×VCC V DI pin Input high level voltage 1 VIH1 0.7×VCC − − V DI pin Input low level voltage 2 VIL2 − − 0.2×VCC V CS, SK, WC pin Input high level voltage 2 VIH2 0.8×VCC − − V CS, SK, WC pin Output low level voltage VOL 0 − 0.4 V IOL=2.1mA Output high level voltage VOH VCC−0.4 − VCC V IOH=−0.4mA Input leak current ILI −1 − 1 µA VIN=0V∼VCC Output leak current ILO −1 − 1 µA VOUT=0V∼VCC, CS=VCC Consumption current during operation ICC1 − − 5 mA fSK=2MHz tE / W=10ms (WRITE) ICC2 − − 3 mA fSK=2MHz (READ) Standby current ISB − − 3 µA CS / SK / DI / WC=VCC DO, R / B=OPEN SK frequency fSK − − 2 MHz − BR9080 / F / RFV, BR9016 / F / RFV: 3V (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7V∼5.5V) Parameter Symbol Min. Typ. Max. Unit Input low level voltage 1 VIL1 − − 0.3×VCC V DI pin Input high level voltage 1 VIH1 0.7×VCC − − V DI pin Input low level voltage 2 VIL2 − − 0.2×VCC V CS, SK, WC pin Input high level voltage 2 VIH2 0.8×VCC − − V CS, SK, WC pin Output low level voltage VOL 0 − 0.4 V IOL=100µA Output high level voltage VOH VCC−0.4 − VCC V IOH=−100µA ILI −1 − 1 µA VIN=0V∼VCC Output leak current ILO −1 − 1 µA VOUT=0V∼VCC, CS=VCC Consumption current during operation ICC1 − − 3 mA fSK=2MHz tE / W=10ms (WRITE) ICC2 − − 750 µA fSK=2MHz (READ) Standby current ISB − − 2 µA CS / SK / DI / WC=VCC DO, R / B=OPEN SK frequency fSK − − 2 MHz Input leak current Not designed for radiation resistance Conditions − BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs zOperating timing characteristics BR9080 / F / RFV, BR9016 / F / RFV (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7V∼5.5V) Symbol Min. Typ. Max. Unit CS setup time Parameter fCSS 100 − − ns CS hold time tCSH 100 − − ns Data setup time tDIS 100 − − ns Data hold time tDIH 100 − − ns DO rise delay time tPD1 − − 150 ns DO fall delay time tPD0 − − 150 ns Self-timing programming cycle tE / W − − 10 ms tCS 250 − − ns CS minimum high level time READY / BUSY display valid time tSV − − 150 ns Time when DO goes HIGH-Z (via CS) tOH 0 − 150 ns Data clock high level time tWH 250 − − ns Data clock low level time tWL 250 − − ns Write control setup time tWCS 0 − − ns Write control hold time tWCH 0 − − ms zTiming chart Synchronous Data Input Output Timing CS tCS tWH tCSS tCSH tDIH SK tWL tDIS DI tPD tPD DO WC Fig.2 · Input data are clocked in to DI at the rising edge of the clock (SK). · Output data will toggle on the falling edge of the SK clock. · The WC pin does not have any effect on the READ, EWEN and EWDS operations. tOH BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs zCircuit operation (1) Command mode BR9080 Start Bit Op Code Address Read (READ) Instruction 1010 100 A0 A1 A2 A3 A4 A5 A6 A7 A8 Write (WRITE) 1010 010 A0 A1 A2 A3 A4 A5 A6 A7 A8 Erase / Write enable (EWEN) 1010 0011 Erase / Write disable (EWDS) 1010 0000 Data D0 D1 − D14 D15 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ : Means either VIH or VIL Address and data are transferred from LSB. BR9016 Start Bit Op Code Address Read (READ) Instruction 1010 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Write (WRITE) 1010 01 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Erase / Write enable (EWEN) 1010 0011 Erase / Write disable (EWDS) 1010 0000 Data D0 D1 − D14 D15 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ : Means either VIH or VIL Address and data are transferred from LSB. (2) Writing enabled / disabled H SK 1 4 12 8 16 L ENABLE = 11 DISABLE = 00 H CS L H 1 DI 0 1 0 0 0 L HIGH-Z DO H R/B WC High or LOW Fig.3 1) When CS is “HIGH” during power up, BR9080 / F / RFV, BR9016 / F / RFV comes up in the erase / write disabled (EWDS) state. In order to be programmable, it must receive an enable (EWEN) instruction. The device remains programmable until a disable (EWDS) instruction is entered, or until it is powered down. 2) It is unnecessary to add the clock after 16th clock. BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs (3) Read cycle BR9080 / F / RFV SK H 4 1 8 16 32 48 L tCS H CS L STANDBY H 0 1 DI 1 0 1 0 0 A1 A0 A7 A8 L HIGH-Z HIGH-Z D0 DO D15 D0 D15 tOH H R/B Read Data (n) Read Data (n+1) 32 48 High or LOW WC Fig.4 BR9080 / F / RFV BR9016 / F / RFV SK H 4 1 8 16 L tCS H CS L STANDBY H 1 DI 0 1 0 1 0 A0 A1 A2 A8 A9 L HIGH-Z HIGH-Z D0 DO D15 D0 D15 tOH H Read Data (n) R/B WC Read Data (n+1) High or LOW Fig.5 BR9016 / F / RFV 1) After the fall of the 16th clock pulse, 16-bit data is output from the DO pin in synchronization with the falling edge of the SK signal. (DO output changes at a time lag of tPD0, tPD1 because of internal circuit delay following the falling edge of the SK signal. During the tPD0 and tPD1 timing, the tPD time should be assured before data is read, to avoid the previous data being lost. See the synchronized data input / output timing chart in Fig.2.) 2) BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs (4) Write cycle BR9080 / F / RFV SK H 1 4 8 16 32 L H CS L tCS H 0 1 DI 1 0 0 1 0 A0 A1 A7 A8 D0 D15 L HIGH-Z HIGH-Z DO tSV tE-W H R/B tWCS WC tWCH Fig.6 BR9080 / F / RFV BR9016 / F / RFV SK H 1 4 8 16 32 L H CS L tCS H 1 DI 0 1 0 0 1 A0 A1 A2 A8 A9 D0 D15 L HIGH-Z HIGH-Z DO tSV tE-W H R/B WC tWCS tWCH Fig.7 BR9016 / F / RFV 1) At the rising edge of 32nd clock, R / B pin will be come out “LOW” after the specified time delay (tSV). 2) From above edge R / B will indicate the ready / busy status of the chip: “LOW” indicated programming is all in progress: “HIGH” indicates the write cycle is complete and this part is ready for another instruction. 3) During the input of Write command, CS must be “LOW”. However, once the write operation started, CS could be either “HIGH” or “LOW”. 4) If WC becomes “HIGH” during Write Cycle, the write operation is halted. In this case, the address data in writing is no guaranteed. It is necessary to rewrite it. BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs (5) READY / BUSY display (R / B pin and DO pin: BR9080 / F / RFV, BR9016 / F / RFV) 1) This display outputs the internal status signal; the R / B pin outputs the HIGH or LOW status at all times. The display can also be output from the DO pin. Following completion of the writing command, if CS falls while SK is LOW, either HIGH or LOW is output. (The display can also be output without using the R / B pin, leaving it open.) 2) When writing data to a memory cell, the READY / BUSY display is output from the rise of the 32nd clock pulse of the SK signal after tSV, from the R / B pin. R / B display = LOW: writing in progress (The internal timer circuit is activated, and after the tE / W timing has been created, the timer circuit stops automatically. Writing of data to the memory cell is done during the tE / W timing, during which time other commands cannot be received.) R / B display = HIGH: command standby state (Writing of data to the memory cell has been completed and the next command can be received.) SK CS Clock DI Write command tPD tOZ HIGH-Z READY DO BUSY R/B READY BUSY Fig.8 R / B Status Output timing chart 1) D0 will output R / B status after CS is held low during SK=L, until CS is held high. Note : The document may be strategic technical data subject to COCOM regulations. READY HIGH-Z BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs zOperation notes (1) Turning the power supply on and off 1) When the power supply is turned on and off, CS should be set to HIGH (=VCC). 2) When CS is LOW, the command input reception state (active) is entered. If the power supply is turned on in this state, erroneous operations and erroneous writing can occur because of noise and other factors. To avoid this, make sure CS is set to HIGH (=VCC) before turning on the power supply. (Good example) Here, the CS pin is pulled up to VCC. When turning off the power supply, wait at least 10msec before turning it on again. Failing to observe this condition can result in the internal circuit failing to be reset when the power supply is turned on. (Bad example) CS is LOW when the power supply is turned on or off. In this case, because CS remains LOW, the EEPROM may perform erroneous operations or write erroneous data because of noise or other factors. * Please be aware that the case shown in this example can also occur if CS input is HIGH-Z. VCC VCC GND VCC CS GND Good example Bad example Fig.9 (2) Noise countermeasures 1) SK noise If noise occurs at the rise of the SK clock input, the clock is assumed to be excessive, and this can cause malfunction because the bits are out of alignment. 2) WC noise During a writing operation, noise at the WC pin can be erroneously judged to be data, and this can cause writing to be forcibly interrupted. 3) VCC noise Noise and surges on the power supply line can cause malfunction. We recommend installing a bypass capacitor between the power supply and ground to eliminate this problem. BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs (3) Canceling modes 1) Read commands 32 Clock SK CS DI Start bit Operating code Address 4 bits 4 bits 8 bits 16 bits DO DO Data D15 Cancel can be performed for the entire read mode space WC HIGH or LOW Fig.10 Cancellation method: CS HIGH 2) Write commands 32 Clock SK CS DI Start bit Operating code Address 4 bits 4 bits 8 bits DO Data D15 16 bits tE / W R/B a b c d WC Fig.11 Canceling methods a : Canceled by setting CS HIGH. The WC pin is not involved. b : If the WC pin goes HIGH for even a second, writing is forcibly interrupted. Cancellation occurs even if the CS pin is HIGH. At this point, data has not been written to the memory, so the data in the designated address has not yet been changed. c : The operation is forcibly canceled by setting the WC pin to HIGH or turning off the power supply (although we do not recommend using this method). The data in the designated address is not guaranteed and should be written once again. d : If CS is set to HIGH while the R / B signal is HIGH (following the tE / W timing), the IC is reset internally, and waits for the next command to be input. BR9080 / BR9080F / BR9080RFV / BR9016 / BR9016F / BR9016RFV Memory ICs zExternal dimension (Units : mm) BR9080 BR9016 BR9080F BR9016F 9.3 ± 0.3 5.0 ± 0.2 4 0.11 6.2 ± 0.3 1.5 ± 0.1 0.51Min. 3.2 ± 0.2 3.4 ± 0.3 1 4 7.62 1.27 0.4 ± 0.1 0.3Min. 0.15 0.3 ± 0.1 2.54 0.5 ± 0.1 0 ~ 15 SOP8 DIP8 BR9080RFV BR9016RFV 3.0 ± 0.2 8 5 1 4 0.22 ± 0.1 (0.52) 0.15 ± 0.1 0.1 1.15 ± 0.1 4.4 ± 0.2 6.4 ± 0.3 5 0.15 ± 0.1 1 8 4.4 ± 0.2 5 6.5 ± 0.3 8 0.3Min. 0.65 0.1 SSOP-B8