ON NCP51401 Termination regulator Datasheet

NCP51401
3 Amp VTT Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51401 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51401 maintains a fast transient response and only requires
a minimum output capacitance of 20 mF. The NCP51401 supports a
remote sensing function and all power requirements for DDR VTT bus
termination. The NCP51401 can also be used in low−power chipsets
and graphics processor cores that require dynamically adjustable
output voltages.
The NCP51401 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
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DFN10, 3x3, 0.5P
CASE 506CL
MARKING DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
PVCC Voltage Range: 1.1 to 3.5 V
Integrated Power MOSFETs
Source and Sink Termination Regulator with Droop Compensation
Fast Load−Transient Response
PGOOD − Logic output pin to Monitor VTT Regulation
EN − Logic input pin for Shutdown mode
VRI − Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
Remote Sensing (VTTS)
Built−in Under Voltage Lockout and Over Current Limit
Thermal Shutdown
Small, Low−Profile 10−pin, 3x3 DFN Package
These Devices are Pb−Free and are RoHS Compliant
Applications
•
•
•
•
•
•
•
•
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Chipset/RAM Supplies as Low as 0.5 V
Active Bus Termination
51401
ALYWG
G
51401 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTION
VRI
1
PVCC
2
VTT
3
PGND
VTTS
+
10
VCC
9
PGOOD
8
GND
4
7
EN
5
6
VRO
GND
Exposed Pad
ORDERING INFORMATION
Device
NCP51401MNTXG
Package
Shipping†
DFN10
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 0
1
Publication Order Number:
NCP51401/D
NCP51401
(see notes on page 6)
PIN FUNCTION DESCRIPTION
Pin Number
Pin Name
Pin Function
1
VRI
2
PVCC
3
VTT
4
PGND
Power Ground. Internally connected to the output sink MOSFET.
5
VTTS
VTT Sense Input. The VTTS pin provides accurate remote feedback sensing of VTT. Connect VTTS to the
remote DDR termination bypass capacitors.
6
VRO
Independent Buffered VTT Reference Output. Sources and sinks over 5 mA. Connect to GND thru
0.1 mF ceramic capacitor.
7
EN
Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect
to VDDQ for normal operation.
8
GND
9
PGOOD
10
VCC
THERMAL
PAD
VTT External Reference Input ( set to VDDQ / 2 thru resistor network ).
Power input. Internally connected to the output source MOSFET.
Power Output of the Linear Regulator.
Common Ground.
Power Good (Open Drain output).
Analog power supply input. Connect to GND thru a 1 − 4.7 mF ceramic capacitor.
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
vias for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC, PVCC, VTT, VTTS, VRI, VRO (Note 1)
−0.3 to 6.0
V
EN, PGOOD (Note 1)
−0.3 to 6.0
V
PGND to GND (Note 1)
Storage Temperature
Operating Junction Temperature Range
ESD Capability, Human Body Model (Note 2)
−0.3 to +0.3
V
TSTG
−55 to 150
°C
TJ
150
°C
ESDHBM
2000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
TA = 255C Power Rating
Derating Factor above
TA = 255C
TA = +855C Power Rating
10−Pin DFN
1.92 W
19 mW/°C
0.79 W
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2
NCP51401
RECOMMENED OPERATING CONDITIONS
Symbol
Value
Unit
Supply Voltage
Rating
VCC
2.375 to 5.5
V
Voltage Range
VRO
−0.1 to 1.8
V
VRI
0.5 to 1.8
PVCC, VTT, VTTS, EN, PGOOD
−0.1 to 3.5
PGND
−0.1 to +0.1
TA
−40 to +125
Operating Free−Air Temperature
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.
Conditions
Parameter
Symbol
Min
Typ
Max
Units
IVCC
0.7
1
mA
IVCC SHD
65
80
mA
200
400
2.3
2.375
Supply Current
VCC Supply Current
TA = +25°C, EN = 3.3 V, No Load
VCC Shutdown Current
TA = +25°C, EN = 0 V, VRI = 0 V, No Load
TA = +25°C, EN = 0 V, VRI > 0.4 V, No Load
VCC UVLO Threshold
Wake−up, TA = +25°C
VUVLO
2.15
Hysteresis
50
V
mV
IPVCC
1
50
mA
TA = +25°C, EN = 0 V, No Load
IPVCC SHD
0.1
50
mA
VRO = 1.25 V (DDR1), ITT = 0 A
VOS
−15
+15
mV
VRO = 0.9 V (DDR2), ITT = 0 A
−15
+15
PVCC = 1.5 V, VRO = 0.75 V (DDR3),
ITT = 0 A
−15
+15
VTT Voltage Tolerance to VRO
−2 A ≤ ITT ≤ +2 A
−25
+25
mV
Source Current Limit
VTTS = 90% * VRO
3
4.5
A
Sink Current Limit
VTTS = 110% * VRO
3.5
5.5
A
VTT Rise Time
Enable to VTT = 95% of VRI, VTT has 100 mF
ceramic cap load, VRI = 600 mV
25
35
ms
Discharge MOSFET
On−resistance
VRI = 0 V, VTT = 0.3 V, EN = 0 V, TA = +25°C
18
25
W
1.8
V
+1
mA
435
mV
+15
mV
PVCC Supply Current
TA = +25°C, EN = 3.3 V, No Load
PVCC Shutdown Current
VTT Output
VTT Output Offset Voltage
RDIS
VRI − Input Reference
VRI Voltage Range
VRI
VRI Input−bias Current
EN = 3.3 V
VRI UVLO Voltage
VRI rising
VRI UVLO
Hysteresis
VRI HYS
0.5
IRI
360
390
60
VRO − Output Reference
VRO Voltage
VRI
V
VRO Voltage Tolerance to VRI
IRO = ±10 mA, 0.6 V ≤ VRI ≤ 1.25 V
−15
VRO Source Current Limit
VRO = 0 V
10
40
mA
VRO Sink Current Limit
VRO = 0 V
10
40
mA
PGOOD − Powergood Comparator
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3
NCP51401
ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
V/V
PGOOD Lower Threshold
(with respect to VRO)
−23.5%
−20%
−17.5
%
PGOOD Upper Threshold
(with respect to VRO)
17.5%
20%
23.5%
PGOOD Hysteresis
5%
PGOOD Start−up Delay
Start−up rising edge, VTTS within 15% of
VRO
PGOOD Leakage Current
VTTS = VRI (PGOOD = True)
PGOOD = VCC + 0.2 V
PGOOD = False Delay
VTTS is beyond ±20% PGOOD trip thresholds
PGOOD Output Low Voltage
IGOOD = 4 mA
2
ms
1
mA
ms
10
0.4
V
EN − Enable Logic
Logic Input Threshold
EN Logic high
VIH
EN Logic low
VIL
Hysteresis Voltage
EN pin
Logic Leakage Current
EN pin, TA = +25°C
0.3
VENHYS
IILEAK
V
1.7
0.5
−1
V
+1
mA
Thermal Shutdown
Thermal Shutdown
Temperature
TSD
150
°C
Thermal Shutdown Hysteresis
TSH
25
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Figure 1. Typical DDR−3 Application Schematic
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4
NCP51401
The NCP51401 is a sink/source tracking termination
regulator specifically designed for low input voltage and
low external component count systems where space is a key
application parameter. The NCP51401 integrates a
high−performance, low−dropout (LDO) linear regulator
that is capable of both sourcing and sinking current. The
LDO regulator employs a fast feedback loop so that small
ceramic capacitors can be used to support the fast load
transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing
terminal, VTTS, should be connected to the positive terminal
of the output capacitors as a separate trace from the high
current path from VTT.
PGOOD de−asserts within 10 ms after the output exceeds the
limits of the PowerGood window. During initial VTT
startup, PGOOD asserts high 2 ms after the VTT enters power
good window. Because PGOOD is an open−drain output, a
100 kW, pull−up resistor between PGOOD and a stable active
supply voltage rail is required.
The LDO has a constant over−current limit (OCL). Note
that the OCL level reduces by one−half when the output
voltage is not within the power good window. This reduction
is non−latch protection. For VCC under−voltage lockout
(UVLO) protection, the NCP51401 monitors VCC voltage.
When the VCC voltage is lower than the UVLO threshold
voltage, both the VTT and VRO regulators are powered off.
This shutdown is also non−latch protection.
VRI − Generation of Internal Voltage Reference
Thermal Shutdown with Hysteresis
The output voltage, VTT, is regulated to VRO. When VRI
is configured for standard DDR termination applications,
VRI can be set by an external equivalent ratio voltage divider
connected to the memory supply bus (VDDQ). The
NCP51401 supports VRI voltage from 0.5 V to 1.8 V,
making it versatile and ideal for many types of low−power
LDO applications.
If the NCP51401 is to operate in elevated temperatures for
long durations, care should be taken to ensure that the
maximum operating junction temperature is not exceeded.
To guarantee safe operation, the NCP51401 provides
on−chip thermal shutdown protection. When the chip
junction temperature exceeds 150°C, the part will shutdown.
When the junction temperature falls back to 125°C, the
device resumes normal operation. If the junction
temperature exceeds the thermal shutdown threshold then
the VTT and VRO regulators are both shut off, discharged by
the internal discharge MOSFETs. The shutdown is a
non−latch protection.
General
VRO − Reference Output
When it is configured for DDR termination applications,
VRO generates the DDR VTT reference voltage for the
memory application. It is capable of supporting both a
sourcing and sinking load of 10 mA. VRO becomes active
when VRI voltage rises to 435 mV and VCC is above the
UVLO threshold. When VRO is less than 360 mV, it is
disabled and subsequently discharges to GND through an
internal 10 kW MOSFET. VRO is independent of the EN pin
state.
Tracking Startup and Shutdown
The NCP51401 also supports tracking startup and
shutdown when EN is tied directly to the system bus and not
used to turn on or turn off the device. During tracking
startup, VTT follows VRO once VRI voltage is greater than
435 mV. VRI follows the rise of VDDQ memory supply rail
via a voltage divider. PGOOD is asserted 2 ms after VTT is
within ±20% of VRO. During tracking shutdown, VTT falls
following VRO until VRO reaches 360 mV. Once VRO falls
below 360 mV, the internal discharge MOSFETs are turned
on and quickly discharge both VRO and VTT to GND.
PGOOD is de−asserted once VTT is beyond the ±20% range
of VRO.
EN − Enable Control
When EN is driven high, the NCP51401 VTT regulator
begins normal operation. When EN is driven low, VTT is
discharges to GND through an internal 18−W MOSFET.
VREF remains on when EN is driven low.
PGOOD − PowerGood
The NCP51401 provides an open−drain PGOOD output
that goes high when the VTT output is within ±20% of VRO.
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5
NCP51401
VTT Droop Compensation
Droop compensation is a technique to reduce error voltage
due to a transient, or as a design tradeoff, to reduce system
cost for a given transient magnitude, by using smaller, less
expensive capacitors. Figure 2 shows the transient response
in a system without droop compensation and is showing a
peak−to−peak error voltage of ±30 mV. Figure 3 shows the
same magnitude of transient response, but this time the
regulation is performed *with* droop compensation. For
example the magnitude of the transient in Figure 3 is
+30 mV = +20 mV – (−10 mV) which is the same magnitude
as in Figure 2, but since the output voltage is allowed to sag
10 mV when loaded (as opposed to the “perfect” Load
Regulation, i.e. 0 mV of VTT output voltage sag as shown
in Figure 2) then this same +30 mV transient starts at
−10 mV and now only peaks to +20 mV. The net result is that
with 10 mV of droop, the overall, peak−to−peak error
voltage has been reduced from ±30 mV to ±20 mV.
VTT Startup Time
In order to speed up the time it takes a modern computer
to Boot−up or Resume after Stand−by, some newer
motherboard specs require VTT to rise from 0 V to 95% of
VTT in less than 35 msec. This new requirement is met in the
new ON Semiconductor NCP51401, NCP51402 and
NCP51403 devices.
Figure 2.
Figure 3.
Legacy DDR2/3, DDR4 and Droop Compensation
VTT Capacitor Selection
When the popular, now industry−standard, 51200−
compatible devices were first introduced, the PC memory
industry was transitioning from DDR2 (VTT = 900 mV) to
DDR3 (VTT = 750 mV) and a value of ±14 mV of droop
compensation per ±1.5 amps of DC current was
designed−in. This value of droop was appropriate for the
DDR2 and DDR3 memory in use at the time, but this amount
of droop has now become excessive for DDR4. For example
for DDR4 with a VTT voltage of 600 mV, the 5% error
tolerance is ±30 mV, which leaves no transient−response
margin for a DC load of ±2 amps. This excessive DDR2/3
droop compensation issue of using 51200 devices in newer
DDR4 applications has been solved in the new
ON Semiconductor NCP51402 and NCP51403 devices,
which have no droop compensation for improved,
high−current DDR4 transient response.
Many 51200−compatible devices have specified VTT
capacitor ESR requirements and must be loaded with at least
20 mF of ceramic capacitance in order to guarantee stability.
In contrast, the NCP51400, NCP51401 and NCP51402 were
all designed to be stable with a wide range of ESR and can
use both ceramic and higher−ESR, polymer capacitors.
Extending the NCP5140x family of parts, in applications
that have specified phase margin requirements, we have
introduced the NCP51403 which has 45° of phase margin
when VTT is loaded with a ceramic capacitance of 40 mF.
However just like our competitor’s 51200−compatible
devices, the NCP51403 cannot be loaded solely with
polymer capacitors because the 45° phase margin reduces
the ESR−stability range of the VTT capacitor.
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6
NCP51401
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 506CL
ISSUE O
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG
SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30
MICRONS ONTO BOTTOM SURFACE OF TERMINAL b.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL B
ALTERNATE CONSTRUCTION IS NOT APPLICABLE.
L
L
A
B
L1
PIN ONE
REFERENCE
0.10 C
2X
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.10 C
2X
0.05 C
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉ
ÇÇ
EXPOSED Cu
TOP VIEW
MOLD CMPD
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
DETAIL B
ALTERNATE
CONSTRUCTIONS
DETAIL B
A
10X
0.05 C
NOTE 4
SIDE VIEW
(A3)
A1
C
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
D2
DETAIL A
1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
3.00 BSC
2.40
2.60
3.00 BSC
1.40
1.60
0.50 BSC
0.25
−−−
0.25
0.45
0.00
0.03
10X
e
10X
L
2.70
0.57
5
E2
1.70 3.30
PACKAGE
OUTLINE
K
10
6
10X
1
b
0.10 C A B
BOTTOM VIEW
0.05 C
0.50
PITCH
NOTE 3
10X
0.32
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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