Automotive Body
Power Management LSI Series
LED Driver IC
rev. 0.34
0.4
rev.
BD8115F-M
●Description
The BD8115F is a serial parallel control LED driver with 35V input voltage rating.
Responding to the 3-line serial data, it turns the 8ch open drain output on/off.
Due to its compact size, it is optimal for small spaces.
●Features
1) Open Drain Output
2) 3-line Serial Control + Enable Signal
3) Internal Temperature Protection Circuit (TSD)
4) Cascade Connection Compatible
5) SOP16
6) Internal 8ch Power Transistor
zApplications
These ICs can be used with car and consumer electronic.
●Absolute Maximum Ratings (Ta=25℃)
Item
Symbol
Value
Unit
VCC
7
V
Output Voltage（Pin No : 3～6, 11～14）
VDmax
35
V
Input Voltage（Pin No : 2, 7, 8, 10, 15）
VIN
-0.3～VCC
V
Power Dissipation
Pd
560*
mW
Operating Temperature Range
Topr
-40～+105
℃
Storage Temperature Range
Tstg
-55～+150
℃
Drive Current (DC)
IomaxD
50
mA
Drive Current（Pulse）
IomaxP
150**
mA
Tjmax
150
℃
Power Supply Voltage
Junction Temperature
* Pd decreased at 4.48mW/℃ for temperatures above Ta=25℃,mounted on 70×70×1.6mm Glass-epoxy PCB.
** Do not however exceed Pd. Time to impress≦200msec
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1/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●Operational Conditions (Ta=-40~105℃)
Item
Standard Value
Symbol
Power Supply Voltage
Drive Current
Unit
Min
Typ
Max
Vcc
4.5
5
5.5
V
Io
-
20
40
mA
* This product is not designed for protection against radioactive rays.
●Electrical Characteristics (Unless specified, Ta=-40~105℃ Vcc=4.5～5.5V)
Item
Symbol
Standard Value
Unit
Conditions
Min
Typ
Max
RON
-
6
12
Ω
ID=20mA
IDL
-
0
5
uA
VD=34V
Upper limit threshold voltage
VTH
Vcc
×0.8
-
-
V
Bottom limit threshold voltage
VTL
-
-
Vcc
×0.2
V
Hysteresis width
VHYS
0.15
0.3
0.45
V
Serial clock frequency
FCLK
-
-
1.25
MHz
Input Current
IIN
20
50
100
uA
VIN=5V
Input leakage Current
IINL
-
0
5
uA
VIN=0V
Circuit Current
ICC
-
0.3
5
mA
Static Current
ISTN
-
0
50
uA
Output Voltage high
VOH
4.6
4.8
-
V
VCC=5V, ISO=-4mA
Output voltage Low
VOL
-
0.2
0.4
V
VCC=5V, ISO=4mA
【Output D0～D7】（Pin No : 3～6, 11～14）
ON Resistor
Output leakage current
【Logic input】（Pin No : 2, 7, 8, 10, 15）
VCC=5V
【WHOLE】
Serial Data Input,
VCC=5V,CLK=500KHz,
SEROUT=OPEN
RST_B=OPEN,
SEROUT=OPEN
【SER OUT】(Pin No. : 9)
* This product is not designed for protection against radioactive rays.
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2/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●Electrical Characteristic Diagrams (Unless otherwise specified Ta=25℃)
9
450
310
350
300
105℃
250
200
-40℃
150
100
5.0V
OUTPUT ON RESISTANCE：RON[Ω]
25℃
SUPPLY CURREN T：Icc[μA]
SUPPLY CURRENT ：Icc[μA]
400
5.5V
290
270
4.5V
250
230
50
210
0
0
1
2
3
4
SUPPLY VOLTAGE：Vcc[V]
6
5
4
3
25℃
2
-40℃
1
-15
10
35
60
85
4.5
4.7
4.9
5.1
5.3
SUPPLY VOLTAGE：Vcc[V]
AMBIENT TEMPERATURE ： Ta[℃]
5.5
Fig.3 Output on resistance
Fig.1 Circuit current
Fig.2 Circuit current
（VCC characteristic）
（Temperature characteristic）
（VCC characteristic @ IDD=20mA）
300
9
6.0
4.5V
250
7
5V
6
5
5.5V
4
3
2
4.5V
OUTPU T VOLTAGE ： VOH[V]
8
OUTPUT VOLTAGE ： [mV]
OUTPUT ON RESISTANCE ： RON[Ω]
7
0
-40
5
105℃
8
200
5V
150
5.5V
100
50
1
5.5
-40℃
5.0
25℃
4.5
105℃
0
0
10
-40
-15
10
35
60
85
20
30
40
INPUT CURRENT： ID[mA]
4.0
50
4.5
AMBIENT TEMPERATURE ： Ta[℃]
Fig.4 Output on resistance
Fig.5 Output on resistance
（Temperature characteristic @ IDD=20mA）
（IDD characteristic）
6.0
4.7
4.9
5.1
5.3
SUPPLY VOLTAGE： Vcc[V]
5.5
Fig.6 SEROUT high side voltage
（VCC characteristic @ ISO=-5mA）
0.30
0.30
105℃
0.25
5V
5.0
4.5
25℃
OUTPUT VOLTAGE ： VOL[V]
OUTPU T VOLTAGE ： VOL[V]
OUTPUT VOLTAGE ： VOH[V]
5.5V
5.5
0.20
0.15
-40℃
0.10
0.05
0.25
4.5V
0.20
5.5V
0.15
5V
0.10
0.05
4.5V
4.0
0.00
0.00
-40
-15
10
35
60
85
AMBIENT TEMPERATURE ： Ta[℃]
Fig.7 SEROUT high side voltage
（Temperature characteristic @ ISO=-5mA）
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© 2009 ROHM Co., Ltd. All rights reserved.
4.5
4.7
4.9
5.1
5.3
5.5
SUPPLY VOLTAGE ： Vcc[V]
Fig.8 SEROUT low side voltage
（VCC characteristic @ ISO=5mA）
3/12
-40
-15
10
35
60
85
AMBIENT TEMPERATURE ： Ta[℃]
Fig.9 SEROUT low side voltage
（Temperature characteristic @ ISO=4mA）
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●Block Diagram
TSD
VCC
SERIN
1
2
D0
3
D1
4
D2
5
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
D
Q
CK CLR
16
GND
15
CLK
14
D7
13
D6
12
D5
11
D4
D3
6
RST_B
7
10
LATCH
SDWN
8
9
SEROUT
Fig.10
●Terminal Number・Terminal Name
●Pin Setup Diagram
BD8115FV（SOP16）
Pin
Number
1
2
3
Terminal
Name
VCC
SERIN
D0
4
D1
Drain output terminal 1
5
D2
Drain output terminal 2
6
D3
Drain output terminal 3
7
RST_B
Function
Power supply voltage input terminal
Serial data input terminal
Drain output terminal 0
VCC
1
16
GND
SERIN
2
15
CLK
D0
3
14
D1
4
13
D6
D2
5
12
D5
8
SDWN
D3
6
11
D4
9
SEROUT
Serial data output terminal
RST_B
7
10
LATCH
10
LATCH
Latch signal input terminal
(H: Data latch)
SDWN
8
9
SEROUT
11
D4
Drain output terminal 4
12
D5
Drain output terminal 5
13
D6
Drain output terminal 6
14
D7
Drain output terminal 7
15
CLK
Clock input terminal
16
GND
GND terminal
D7
Fig.11
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4/12
Reset return input terminal
(L:FF data 0)
Shut down input terminal
(H: Output OFF)
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●Block Operation
1）Serial I/F
The I/F is a 3-line serial (LATCH, CLK, SERIN) style.
8-bit output ON/OFF can be set-up. This is composed of shift register. + 8-bit register.
2）Driver
It is a 8-bit open drain output.
3）TSD (Thermal Shut Down)
To prevent heat damage and overheating, when the chip temperature goes over approximately 175℃, the output turns
off. When the temperature goes back down, normal operation resumes. However, the intended use of the
temperature protection circuit is to protect the IC, so please construct thermal design with the junction temperature
Tjmax under 150℃.
●Application Circuit
VCC
10uF
VBAT
10uF
↓IF
Rres
VF
VCC
SDWN
LATCH
RST_B
CLK
SERIN
SEROUT
GND
Micro computer
D0
D1
D2
D3
D4
D5
D6
D7
VCC
10uF
VCC
SDWN
LATCH
RST_B
CLK
SERIN
SEROUT
GND
D0
D1
D2
D3
D4
D5
D6
D7
IF=
VBAT - VF
Rres + RON
Fig.12
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5/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●Serial Communication
The serial I/F is composed of a shift register which changes the CLK and SERIN serial signals to parallel signals, and a
register to remember those signals with a LATCH signal. The registers are reset by applying a voltage under VCC×0.2 to
the RST_B terminal or opening it, and D7~D0 become open. To prevent erroneous LED lighting, please apply voltage
under VCC×0.2 to RST_B or make it open during start-up.
CLK
SERIN
8bit
Shift
Register
8bit
Driver
Register
LATCH
Fig.13
1）Serial Communication Timing
The 8-bit serial data input from SERIN is taken into the shift register by the rise edge of the CLK signal, and is recorded
in the register by the rise edge of the LATCH signal. The recorded data is valid until the next rise edge of the LATCH
signal.
2）Serial Communication Data
The serial data input configuration of SERIN terminal is shown below:
First →
→Last
d7
d6
d5
d4
d3
d2
d1
d0
Data
Terminal
Name
D7
D6
D5
D4
D3
D2
D1
D0
Output
Status
d7
d6
d5
d4
Data
d3
d2
d1
d0
ON
1
*
*
*
*
*
*
*
OFF
0
*
*
*
*
*
*
*
ON
*
1
*
*
*
*
*
*
OFF
*
0
*
*
*
*
*
*
ON
*
*
1
*
*
*
*
*
OFF
*
*
0
*
*
*
*
*
ON
*
*
*
1
*
*
*
*
OFF
*
*
*
0
*
*
*
*
ON
*
*
*
*
1
*
*
*
OFF
*
*
*
*
0
*
*
*
ON
*
*
*
*
*
1
*
*
OFF
*
*
*
*
*
0
*
*
ON
*
*
*
*
*
*
1
*
OFF
*
*
*
*
*
*
0
*
ON
*
*
*
*
*
*
*
1
*
*
*
*
*
*
0
OFF
*
* represents “Don’t care”.
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6/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
3）Enable Signal
By applying voltage at least VCC×0.8 or more to the SDWN terminal, D0~D7 become open forcibly. At this time, the
temperature protection circuit (TSD) stops. D7～D0 become PWM operation by inputting PWM to SDWN.
4）SEROUT
A cascade connection can be made (connecting at least 2 or more IC’s in serial).
Serial signal input from SERIN is transferred into receiver IC by the fall edge of the CLK signal.
Since this functionality gives enough margins for the setup time prior to the rise edge of the CLK signal on the receiver
IC (using the exact same CLK signal of sender IC), the application reliability can be improved as cascade connection
functionality.
LATCH
SERIN
d7
CLK
d6
1
d5
2
d4
3
d3
4
d2
5
d1
6
d0
7
8
SEROUT
D7
Fig.14
●Cascade Connection
By using (at least) 2 ICs, each IC’s D7~D0, at (at least) 16ch, can be controlled by the 16-bit SERIN signal. The serial data
input to the sender IC can be transferred to the receiver IC by inputting 8CLK to the CLK terminal.
Send side IC
Receive side IC
LATCH
SERIN
CLK
d15 d14 d13
1
2
3
d12 d11 d10
4
5
6
d9
d8
d7
7
8
9
d6
10
d5
11
d4
12
d3
13
d2
14
d1
15
d0
16
Fig.15
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7/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●INPUT SIGNAL’S TIMING CHART
TCK
50%
CLK
TCKH
TCKL
TSESTTSEHD
SERIN
50%
TLADZ
TSEW
50%
LATCH
TLAH
Fig.16
●INPUT SIGNAL’S TIMING RULE（Ta=-40～105℃ Vcc=4.5～5.5V）
Parameter
Symbol
Min
Unit
TCK
800
ns
CLK high pulse width
TCKH
380
ns
CLK low pulse width
TCKL
380
ns
SERIN high and low pulse width
TSEW
780
ns
SERIN setup time prior to CLK rise
TSEST
150
ns
SERIN hold time after CLK rise
TSEHD
150
ns
TLAH
380
ns
TLADZ
200
ns
CLK period
LATCH high pulse time
Last CLK rise to LATCH rise
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8/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●OUTPUT SIGNAL’S DELAY CHART
SDWN
50%
TDSNL
TDSNH
OUTPUT
(D7～D0)
LATCH
50%
50%
TDLAH
OUTPUT
(D7～D0)
CLK
50%
50%
TDSOH
SEROUT
TDSOL
50%
Fig.17
●OUTPUT SIGNAL’S DELAY TIME（Ta=-40～105℃ Vcc=4.5～5.5V）
Parameter
Symbol
Max
Unit
SDWN Switching Time(L→H)
TDSNH
300
ns
SDWN Switching Time(H→L)
TDSNL
300
ns
LATCH Switching Delay Time
TDLAH
300
ns
SEROUT Propagation Delay Time(L→H)
TDSOH
350
ns
SEROUT Propagation Delay Time (H→L)
TDSOL
350
ns
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9/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●INPUT/OUTPUT EQUIVALENT CIRCUIT（PIN NAME）
10PIN（LATCH）
14PIN（D7），13PIN（D6）
7PIN（RST_B）
12PIN（D5），11PIN（D4）
8PIN（SDWN）
6PIN（D3），5PIN（D2）
2PIN（SERIN）
4PIN（D1），3PIN（D0）
15PIN（CLK）
VCC
9PIN（SEROUT）
VCC
VCC
100k
(TYP)
Fig.18
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10/12
2009.12 - Rev.0.34
Technical Note
BD8115F-M
●Operation Notes
(1)
Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in
IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is
suffered.
A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute
maximum ratings may be exceeded is anticipated.
(2) Reverse connection of a power supply connector
If the connector of power is wrong connected, it may result in IC breakage. In order to prevent the breakage from the wrong
connection, the diode should be connected between external power and the power terminal of IC as protection solution.
(3) GND potential
Ensure a minimum GND pin potential in all operating conditions.
(4) Setting of heat
Use a setting of heat that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
(5) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature
range may result in IC damage.
(6) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
(7) Thermal shutdown circuit(TSD)
This IC built-in a Thermal shutdown circuit (TSD circuit). If Chip temperature becomes 175 (TYP.), make the output an Open
state. Eventually, warmly clearing the circuit is decided by the condition of whether the heat excesses over the assigned limit,
resulting the cutoff of the circuit of IC, and not by the purpose of preventing and ensuring the IC. Therefore, the warm
switch-off should not be applied in the premise of continuous employing and operation after the circuit is switched on.
(8) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and
use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process
(9) IC terminal input
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions
are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.
For example, when a resistor and transistor are connected to pins. (See the chart below.)
{ the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
{ Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other
adjacent elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's
architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage.
For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements,
such as by the application of voltages lower than the GND (PCB) voltage to input pins.
Resistor
Transistor (NPN)
B
～
～
(Pin B)
B
E
～
～
C
(Pin B)
～
～
(Pin A)
GND
N
N
P
P
P+
N
N
Parasitic
elements
P+
N
(Pin A)
P substrate
Parasitic elements
GND
N
～
～
P+
Parasitic elements
E
GND
N
P
P+
C
Parasitic
elements
GND
GND
(10) Ground wiring patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a
single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by
large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of
any external components.
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2009.12 - Rev.0.34
Technical Note
BD8115F-M
●Ordering part number
B
D
8
Part No.
1
1
5
Part No.
F
-
Package
F: SOP8
FP: HSOP25
HFP:HRP7
M
T
E
2
Packaging and forming specification
E2: Embossed tape and reel
(SOP8/HSOP25)
TR: Embossed tape and reel
(HRP7)
None:Tray,Tube
SOP16
<Tape and Reel information>
10 ± 0.2
(MAX 10.35 include BURR)
9
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.3MIN
4.4±0.2
6.2±0.3
16
Tape
1
8
0.11
1.5±0.1
0.15 ± 0.1
1.27
0.4 ± 0.1
0.1
1pin
Reel
(Unit : mm)
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Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.12 - Rev.0.34