LINER LTC6240HVHS5 Single/dual/quad 18mhz, low noise, rail-to-rail output, cmos op amp Datasheet

LTC6240/LTC6241/LTC6242
Single/Dual/Quad 18MHz,
Low Noise, Rail-to-Rail Output,
CMOS Op Amps
DESCRIPTIO
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FEATURES
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0.1Hz to 10Hz Noise: 550nVP-P
Input Bias Current:
0.2pA (Typ at 25°C)
1pA Max (LT6240)
Low Offset Voltage: 125µV Max
Low Offset Drift: 2.5µV/°C Max
Gain Bandwidth Product: 18MHz
Output Swings Rail-to-Rail
Supply Operation:
2.8V to 6V LTC6240/LTC6241/LTC6242
2.8V to ±5.5V LTC6240HV/LTC6241HV/LTC6242HV
Low Input Capacitance
H Grade Temperature Range: –40°C to 125°C
Single LTC6240 in 5-Pin SOT-23 Package and
8-Pin SO for PCB Guard Ring
Dual LTC6241 in 8-Pin SO and Tiny DFN Packages
Quad LTC6242 in 16-Pin SSOP and 5mm × 3mm
DFN Packages
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APPLICATIO S
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These op amps have an output stage that swings within
30mV of either supply rail to maximize the signal dynamic
range in low supply applications. The input common mode
range extends to the negative supply. They are fully specified on 3V and 5V, and an HV version guarantees operation
on supplies up to ±5V.
The LTC6240 is available in the 8-pin SO and the 5-pin
SOT-23 packages. The LTC6241 is available in the 8-pin
SO, and for compact designs it is packaged in a tiny dual
fine pitch leadless (DFN) package. The LTC6242 is available in the 16-Pin SSOP as well as the 5mm × 3mm DFN
package.
Photo Diode Amplifiers
Charge Coupled Amplifiers
Low Noise Signal Processing
Medical Instrumentation
High Impedance Transducer Amplifier
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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The LTC®6240/6241/LTC6242 are single, dual and quad
low noise, low offset, rail-to-rail output, unity gain stable
CMOS op amps that feature 1pA of input bias current. Input
bias current is guaranteed to be 1pA max on the single
LTC6240. The 0.1Hz to 10Hz noise of only 550nVP-P, along
with an offset of just 125µV are significant improvements
over traditional CMOS op amps. Additionally, noise is
guaranteed to be less than 10nV/√Hz at 1kHz. An 18MHz
gain bandwidth, and 10V/µs slew rate, along with the wide
supply range and low input capacitance, make them perfect
for use as fast signal processing amplifiers.
TYPICAL APPLICATIO
Low Noise Single-Ended Input to Differential Output Amplifier
Noise Voltage vs Frequency
60
C3
10pF
C1
10pF
R4
4.99k
R3
4.99k
VIN
+2.5V
–
1/2
LTC6241
+
–
40
30
20
10
–2.5V
1/2
LTC6241
+
VOUT+
NOISE VOLTAGE (nV/√Hz)
50
C4
10pF
R1
200k
TA = 25°C
VS = ±2.5V
VCM = 0V
VOUT–
0
R2
200k
1
C2
10pF
10
100
1k
FREQUENCY (Hz)
10k
100k
6241 TA01b
6241 TA01a
624012fc
1
LTC6240/LTC6241/LTC6242
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ABSOLUTE
AXI U RATI GS
(Note 1)
Total Supply Voltage (V+ to V–)
LTC6240/LTC6241/LTC6242 ...................................7V
LTC6240HV/LTC6241HV/LTC6242HV ...................12V
Input Voltage.......................... (V+ + 0.3V) to (V– – 0.3V)
Input Current........................................................±10mA
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range
LTC6240C/LTC6241C/LTC6242C.......... –40°C to 85°C
LTC6240I/LTC6241I/LTC6242I ............. –40°C to 85°C
LTC6240H/LTC6241H/LTC6242H ....... –40°C to 125°C
Specified Temperature Range (Note 3)
LTC6240C/LTC6241C/LTC6242C.............. 0°C to 70°C
LTC6240I/LTC6241I/LTC6242I ............. –40°C to 85°C
LTC6240H/LTC6241H/LTC6242H ....... –40°C to 125°C
Junction Temperature ........................................... 150°C
DHC, DD Package ............................................. 125°C
Storage Temperature Range....................–65ºC to 150°C
DHC, DD Package ...............................–65ºC to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER S5 PART MARKING*
TOP VIEW
TOP VIEW
–
+
+IN 3
4 –IN
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 250°C/W
–IN 2
–
V– 2
NC 1
+IN 3
+
5 V+
OUT 1
V–
4
8
NC
7
V+
6
OUT
5
NC
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 190°C/W
LTC6240CS5
LTC6240HVCS5
LTC6240IS5
LTC6240HVIS5
LTC6240HS5
LTC6240HVHS5
LTCRR
LTCRS
LTCRR
LTCRS
LTCRR
LTCRS
ORDER PART NUMBER
S8 PART MARKING
LTC6240CS8
LTC6240HVCS8
LTC6240IS8
LTC6240HVIS8
LTC6240HS8
LTC6240HVHS8
6240
6240HV
6240I
240HVI
6240H
240HVH
ORDER PART NUMBER DD PART MARKING*
TOP VIEW
TOP VIEW
8 V+
OUT A 1
–IN A 2
+IN A 3
V
–
4
7 OUT B
A
B
6 –IN B
5 +IN B
OUT A 1
–IN A 2
+IN A 3
V–
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
UNDERSIDE METAL CONNECTED TO V–
(PCB CONNECTION OPTIONAL)
4
A
B
8
V+
7
OUT B
6
–IN B
5
+IN B
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 190°C/W
LTC6241CDD
LTC6241HVCDD
LTC6241IDD
LTC6241HVIDD
LBPD
LBRR
LBPD
LBRR
ORDER PART NUMBER
S8 PART MARKING
LTC6241CS8
LTC6241HVCS8
LTC6241IS8
LTC6241HVIS8
LTC6241HS8
LTC6241HVHS8
6241
6241HV
6241I
241HVI
6241H
241HVH
624012fc
2
LTC6240/LTC6241/LTC6242
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PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER DHC PART MARKING*
TOP VIEW
TOP VIEW
OUT A
–IN A
2
+IN A
3
V
+
16 OUT D
1
A
D
15 –IN D
14 +IN D
4
13 V
17
–
+IN B
5
–IN B
6
11 –IN C
OUT B
7
10 OUT C
NC
8
B
C
12 +IN C
9
NC
DHC16 PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
UNDERSIDE METAL CONNECTED TO V–
(PCB CONNECTION OPTIONAL)
OUT A
1
–IN A
2
+IN A
3
14 +IN D
V+
4
13 V –
+IN B
5
16 OUT D
A
B
D
C
15 –IN D
12 +IN C
–IN B
6
11 –IN C
OUT B
7
10 OUT C
NC
8
9
NC
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 135°C/W
LTC6242CDHC
LTC6242HVCDHC
LTC6242IDHC
LTC6242HVIDHC
6242
6242HV
6242
6242HV
ORDER PART NUMBER
GN PART MARKING
LTC6242CGN
LTC6242HVCGN
LTC6242IGN
LTC6242HVIGN
LTC6242HGN
LTC6242HVHGN
6242
6242HV
6242I
242HVI
6242H
242HVH
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
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AVAILABLE OPTIO S
PART NUMBER
LTC6240CS5
LTC6240CS8
LTC6240HVCS5
LTC6240HVCS8
LTC6240IS5
LTC6240IS8
LTC6240HVIS5
LTC6240HVIS8
LTC6240HS5
LTC6240HS8
LTC6240HVHS5
LTC6240HVHS8
LTC6241CS8
LTC6241CDD
LTC6241HVCS8
LTC6241HVCDD
LTC6241IS8
LTC6241IDD
LTC6241HVIS8
LTC6241HVIDD
LTC6241HS8
LTC6241HVHS8
AMPS/PACKAGE
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
SPECIFIED TEMP RANGE
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
SPECIFIED SUPPLY VOLTAGE
3V, 5V
3V, 5V
3V, 5V, ±5V
3V, 5V, ±5V
3V, 5V
3V, 5V
3V, 5V, ±5V
3V, 5V, ±5V
3V, 5V
3V, 5V
3V, 5V, ±5V
3V, 5V, ±5V
3V, 5V
3V, 5V
3V, 5V, ±5V
3V, 5V, ±5V
3V, 5V
3V, 5V
3V, 5V, ±5V
3V, 5V, ±5V
3V, 5V
3V, 5V, ±5V
PACKAGE
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SOT-23
SO-8
SO-8
DD
SO-8
DD
SO-8
DD
SO-8
DD
SO-8
SO-8
PART MARKING
LTCRR
6240
LTCRS
6240HV
LTCRR
6240I
LTCRS
240HVI
LTCRR
6240H
LTCRS
240HVH
6241
LBPD
6241HV
LBRR
6241I
LBPD
241HVI
LBRR
6241H
241HVH
624012fc
3
LTC6240/LTC6241/LTC6242
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AVAILABLE OPTIO S
PART NUMBER
LTC6242CGN
LTC6242CDHC
LTC6242HVCGN
LTC6242HVCDHC
LTC6242IGN
LTC6242IDHC
LTC6242HVIGN
LTC6242HVIDHC
LTC6242HGN
LTC6242HVHGN
AMPS/PACKAGE
4
4
4
4
4
4
4
4
4
4
SPECIFIED TEMP RANGE
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
SPECIFIED SUPPLY VOLTAGE
3V, 5V
3V, 5V
3V, 5V, ±5V
3V, 5V, ±5V
3V, 5V
3V, 5V
3V, 5V, ±5V
3V, 5V, ±5V
3V, 5V
3V, 5V, ±5V
PACKAGE
GN
DHC
GN
DHC
GN
DHC
GN
DHC
GN
GN
PART MARKING
6242
6242
6242HV
6242HV
6242I
6242
242HVI
6242HV
6242H
242HVH
ELECTRICAL CHARACTERISTICS
(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,
LTC6242HVC/I) The ● denotes the specifications which apply over the specified temperature range, otherwise specifications are at
TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VOS
Input Offset Voltage (Note 4)
LTC6241 S8
0°C to 70°C
–40°C to 85°C
●
●
LTC6242 GN
0°C to 70°C
–40°C to 85°C
●
●
LTC6240
0°C to 70°C
–40°C to 85°C
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
●
●
VOS Match Channel-to-Channel (Note 5) LTC6241 S8
0°C to 70°C
–40°C to 85°C
●
●
LTC6242 GN
0°C to 70°C
–40°C to 85°C
●
●
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
●
●
TC VOS
Input Offset Voltage Drift (Note 6)
IB
Input Bias Current (Notes 4, 7)
●
LTC6241, LTC6242
TYP
MAX
UNITS
40
125
250
300
µV
µV
µV
50
150
275
300
µV
µV
µV
50
175
300
350
µV
µV
µV
100
550
650
725
µV
µV
µV
40
160
300
375
µV
µV
µV
50
185
325
400
µV
µV
µV
150
650
700
750
µV
µV
µV
0.7
2.5
µV/°C
75
pA
pA
1
75
pA
pA
75
pA
pA
1
75
pA
pA
0.2
●
LTC6240
0.2
●
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
0.2
●
LTC6240
0.2
●
Input Noise Voltage
0.1Hz to 10Hz
550
nVP-P
624012fc
4
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,
LTC6242HVC/I) The ● denotes the specifications which apply over the specified temperature range, otherwise specifications are at
TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
en
Input Noise Voltage Density
f = 1kHz
MIN
TYP
MAX
UNITS
7
10
nV/√Hz
in
Input Noise Current Density (Note 8)
RIN
Input Resistance
Common Mode
CIN
Input Capacitance
Differential Mode
Common Mode
f = 100kHz
Input Voltage Range
Guaranteed by CMRR
●
0
Common Mode Rejection
0V ≤ VCM ≤ 3.5V
●
80
105
dB
●
76
95
dB
VO = 1V to 4V
RL = 10k to VS/2
0°C to 70°C
–40°C to 85°C
425
300
200
1600
●
●
V/mV
V/mV
V/mV
VO = 1.5V to 3.5V
RL = 1k to VS/2
0°C to 70°C
–40°C to 85°C
90
60
50
215
●
●
V/mV
V/mV
V/mV
VCM
CMRR
CMRR Match
Channel-to-Channel (Note 5)
AVOL
Large Signal Voltage Gain
0.56
fA/√Hz
1012
Ω
3.5
3
pF
pF
3.5
V
VOL
Output Voltage Swing Low (Note 9)
No Load
ISINK = 1mA
ISINK = 5mA
●
●
●
7
40
190
30
75
325
mV
mV
mV
VOH
Output Voltage Swing High (Note 9)
No Load
ISOURCE = 1mA
ISOURCE = 5mA
●
●
●
11
45
190
30
75
325
mV
mV
mV
PSRR
Power Supply Rejection
VS = 2.8V to 6V, VCM = 0.2V
●
80
104
dB
PSRR Match
Channel-to-Channel (Note 5)
●
74
100
dB
Minimum Supply Voltage (Note 10)
●
2.8
ISC
Short-Circuit Current
●
15
IS
Supply Current per Amplifier
GBW
Gain Bandwidth Product
LTC6241, LTC6242
0°C to 70°C
–40°C to 85°C
●
●
LTC6240
0°C to 70°C
–40°C to 85°C
●
●
Frequency = 20kHz, RL = 1kΩ
●
SR
Slew Rate (Note 11)
AV = –2, RL = 1kΩ
●
FPBW
Full Power Bandwidth (Note 12)
VOUT = 3VP-P, RL = 1kΩ
●
ts
Settling Time
VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1%
13
V
30
mA
1.8
2.2
2.3
2.4
mA
mA
mA
2
2.4
2.5
2.6
mA
mA
mA
18
MHz
5
10
V/µs
0.53
1.06
MHz
1100
ns
624012fc
5
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,
LTC6242HVC/I) The ● denotes the specifications which apply over the specified temperature range, otherwise specifications are at
TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL
VOS
TC VOS
IB
PARAMETER
Input Offset Voltage (Note 4)
CONDITIONS
LTC6241 S8
0°C to 70°C
–40°C to 85°C
LTC6242 GN
0°C to 70°C
–40°C to 85°C
LTC6240
0°C to 70°C
–40°C to 85°C
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
VOS Match Channel-to-Channel (Note 5) LTC6241 S8
0°C to 70°C
–40°C to 85°C
LTC6242 GN
0°C to 70°C
–40°C to 85°C
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
LTC6241, LTC6242
MIN
TYP
40
●
0
78
100
UNITS
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV/°C
pA
pA
pA
pA
pA
pA
pA
pA
V
dB
●
76
95
dB
140
100
75
600
●
●
V/mV
V/mV
V/mV
mV
mV
mV
mV
dB
●
●
60
●
●
50
●
●
100
●
●
40
●
●
60
●
●
150
●
●
●
0.7
0.2
●
LTC6240
0.2
●
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
0.2
●
AVOL
Input Voltage Range
Common Mode Rejection
CMRR Match
Channel-to-Channel (Note 5)
Large Signal Voltage Gain
VOL
Output Voltage Swing Low (Note 9)
VOH
Output Voltage Swing High (Note 9)
PSRR
Power Supply Rejection
PSRR Match
Channel-to-Channel (Note 5)
Minimum Supply Voltage (Note 10)
Short-Circuit Current
Supply Current per Amplifier
ISC
IS
GBW
Gain Bandwidth Product
Guaranteed by CMRR
0V ≤ VCM ≤ 1.5V
VO = 1V to 2V
RL = 10k to VS/2
0°C to 70°C
–40°C to 85°C
No Load
ISINK = 1mA
No Load
ISOURCE = 1mA
VS = 2.8V to 6V, VCM = 0.2V
●
●
●
●
●
●
80
●
74
2.8
3
●
●
LTC6241, LTC6242
0°C to 70°C
–40°C to 85°C
LTC6240
0°C to 70°C
–40°C to 85°C
Frequency = 20kHz, RL = 1kΩ
75
1
75
0.2
●
LTC6240
VCM
CMRR
MAX
175
275
325
200
275
325
200
325
375
550
650
725
200
325
400
225
325
400
650
700
750
2.5
3
65
4
70
104
6
1.4
1.5
●
●
12
30
110
30
120
100
●
●
●
75
1
75
1.5
17
1.7
1.8
1.9
1.9
2
2.1
dB
V
mA
mA
mA
mA
mA
mA
mA
MHz
624012fc
6
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, 0V, VCM = 0V
unless otherwise noted.
SYMBOL
VOS
TC VOS
IB
PARAMETER
Input Offset Voltage (Note 4)
CONDITIONS
LTC6241 S8
0°C to 70°C
–40°C to 85°C
LTC6242 GN
0°C to 70°C
–40°C to 85°C
LTC6240
0°C to 70°C
–40°C to 85°C
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
VOS Match Channel-to-Channel (Note 5) LTC6241 S8
0°C to 70°C
–40°C to 85°C
LTC6242 GN
0°C to 70°C
–40°C to 85°C
LTC6241 DD, LTC6242 DHC
0°C to 70°C
–40°C to 85°C
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
LTC6241, LTC6242
MIN
TYP
50
●
●
60
●
●
60
●
●
100
●
●
50
●
●
60
●
●
150
●
●
●
0.7
0.5
●
0.5
LTC6240
●
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
0.2
●
VCM
CMRR
AVOL
VOL
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density (Note 8)
Input Resistance
Input Capacitance
Differential Mode
Common Mode
Input Voltage Range
Common Mode Rejection
CMRR Match
Channel-to-Channel (Note 5)
Large Signal Voltage Gain
Output Voltage Swing Low (Note 9)
75
1
75
0.2
●
LTC6240
en
in
RIN
CIN
MAX
175
275
325
200
275
325
250
350
400
550
650
725
200
325
400
225
325
400
650
700
750
2.5
0.1Hz to 10Hz
f = 1kHz
550
7
0.56
1012
Common Mode
f = 100kHz
75
1
75
10
3.5
3
Guaranteed by CMRR
–5V ≤ VCM ≤ 3.5V
VO = –3.5V to 3.5V
RL = 10k
0°C to 70°C
–40°C to 85°C
RL = 1k
0°C to 70°C
–40°C to 85°C
No Load
ISINK = 1mA
ISINK = 10mA
UNITS
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV/°C
pA
pA
pA
pA
pA
pA
pA
pA
nVP-P
nV/√Hz
fA/√Hz
Ω
●
–5
83
105
pF
pF
V
dB
●
76
95
dB
775
600
500
150
90
75
2700
●
●
●
●
●
●
●
●
3.5
360
15
45
360
30
75
550
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
mV
mV
mV
624012fc
7
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, 0V, VCM = 0V
unless otherwise noted.
SYMBOL
VOH
PARAMETER
Output Voltage Swing High (Note 9)
PSRR
Power Supply Rejection
PSRR Match
Channel-to-Channel (Note 5)
Minimum Supply Voltage (Note 10)
Short-Circuit Current
Supply Current per Amplifier
ISC
IS
GBW
SR
FPBW
ts
Gain Bandwidth Product
Slew Rate (Note 11)
Full Power Bandwidth (Note 12)
Settling Time
CONDITIONS
No Load
ISOURCE = 1mA
ISOURCE = 10mA
VS = 2.8V to 11V, VCM = 0.2V
MIN
●
●
●
●
85
●
82
2.8
15
●
●
LTC6241, LTC6242
0°C to 70°C
–40°C to 85°C
LTC6240
0°C to 70°C
–40°C to 85°C
Frequency = 20kHz, RL = 1kΩ
AV = –2, RL = 1kΩ
VOUT = 3VP-P, RL = 1kΩ
VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1%
TYP
15
45
360
110
106
35
2.5
●
●
2.7
●
●
●
●
●
13
5.5
0.58
MAX
30
75
550
3.2
3.3
3.7
3.3
3.4
3.8
18
10
1.06
900
UNITS
mV
mV
mV
dB
dB
V
mA
mA
mA
mA
mA
mA
mA
MHz
V/µs
MHz
ns
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The ● denotes the specifications which apply from –40°C
to 125°C, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage (Note 4)
LTC6241 S8
MIN
TYP
MAX
UNITS
40
125
400
150
400
175
450
160
400
185
400
2.5
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV/°C
pA
nA
pA
nA
pA
pA
pA
pA
V
dB
●
50
LTC6242 GN
●
50
LTC6240
●
VOS Match Channel-to-Channel (Note 5) LTC6241 S8
40
●
50
LTC6242 GN
●
TC VOS
IB
Input Offset Voltage Drift (Note 6)
Input Bias Current (Notes 4, 7)
●
0.7
0.2
LTC6241, LTC6242
●
0.2
LTC6240
●
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
0.2
●
0.2
LTC6240
●
VCM
CMRR
AVOL
Input Voltage Range
Common Mode Rejection
CMRR Match
Channel-to-Channel (Note 5)
Large Signal Voltage Gain
Guaranteed by CMRR
0V ≤ VCM ≤ 3.5V
VO = 1V to 4V
RL = 10k to VS/2
VO = 1.5V to 3.5V
RL = 1k to VS/2
1.5
1
2.5
●
150
1
750
3.5
●
0
78
●
74
425
200
1600
●
V/mV
V/mV
90
40
215
●
V/mV
V/mV
dB
624012fc
8
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)
The ● denotes the specifications which apply from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOL
Output Voltage Swing Low (Note 9)
VOH
Output Voltage Swing High (Note 9)
PSRR
Power Supply Rejection
PSRR Match
Channel-to-Channel (Note 5)
Minimum Supply Voltage (Note 10)
Short-Circuit Current
Supply Current per Amplifier
No Load
ISINK = 1mA
ISINK = 5mA
No Load
ISOURCE = 1mA
ISOURCE = 5mA
VS = 2.8V to 6V, VCM = 0.2V
ISC
IS
MIN
TYP
●
●
●
●
●
●
●
78
●
74
2.8
15
●
●
LTC6241, LTC6242
1.8
●
2
LTC6240
●
GBW
SR
FPBW
Gain Bandwidth Product
Slew Rate (Note 11)
Full Power Bandwidth (Note 12)
Frequency = 20kHz, RL = 1kΩ
AV = –2, RL = 1kΩ
VOUT = 3VP-P, RL = 1kΩ
●
●
●
MAX
UNITS
30
85
325
30
85
325
mV
mV
mV
mV
mV
mV
dB
2.2
2.4
2.4
2.8
12
4.5
0.48
dB
V
mA
mA
mA
mA
mA
MHz
V/µs
MHz
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH) The ● denotes the specifications which apply from –40°C
to 125°C, otherwise specifications are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage (Note 4)
LTC6241 S8
MIN
TYP
MAX
UNITS
40
175
400
µV
µV
60
200
400
µV
µV
50
200
450
µV
µV
40
200
400
µV
µV
60
225
400
µV
µV
0.7
2.5
µV/°C
1.5
pA
nA
1
2.5
pA
nA
150
pA
pA
1
750
pA
pA
1.5
V
●
LTC6242 GN
●
LTC6240
●
VOS Match Channel-to-Channel (Note 5) LTC6241 S8
●
LTC6242 GN
●
TC VOS
Input Offset Voltage Drift (Note 6)
IB
Input Bias Current (Notes 4, 7)
●
LTC6241, LTC6242
0.2
●
LTC6240
0.2
●
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
0.2
●
LTC6240
0.2
●
VCM
Input Voltage Range
Guaranteed by CMRR
●
0
CMRR
Common Mode Rejection
0V ≤ VCM ≤ 1.5V
●
75
dB
●
74
dB
●
140
65
CMRR Match
Channel-to-Channel (Note 5)
AVOL
Large Signal Voltage Gain
VO = 1V to 2V
RL = 10k to VS/2
600
V/mV
V/mV
624012fc
9
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)
The ● denotes the specifications which apply from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOL
Output Voltage Swing Low (Note 9)
No Load
ISINK = 1mA
VOH
Output Voltage Swing High (Note 9)
PSRR
Power Supply Rejection
MAX
UNITS
●
●
30
130
mV
mV
No Load
ISOURCE = 1mA
●
●
30
130
mV
mV
VS = 2.8V to 6V, VCM = 0.2V
●
78
dB
PSRR Match Channel-to-Channel
(Note 5)
●
74
dB
Minimum Supply Voltage (Note 10)
●
2.8
V
●
2.5
ISC
Short-Circuit Current
IS
Supply Current per Amplifier
MIN
LTC6241, LTC6242
TYP
mA
1.4
1.7
1.9
mA
mA
1.5
1.9
2.1
mA
mA
●
LTC6240
●
GBW
Gain Bandwidth Product
Frequency = 20kHz, RL = 1kΩ
●
10
MHz
(LTC6240HVH/LTC6241HVH/LTC6242HVH) The ● denotes the specifications which apply from –40°C to 125°C, otherwise specifications
are at TA = 25°C. VS = ±5V, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage (Note 4)
LTC6241 S8
MIN
TYP
MAX
UNITS
50
175
400
µV
µV
60
200
400
µV
µV
60
250
450
µV
µV
50
200
400
µV
µV
60
225
400
µV
µV
0.7
2.5
µV/°C
1.5
pA
nA
1
2.5
pA
nA
150
pA
pA
1
750
pA
pA
3.5
V
●
LTC6242 GN
●
LTC6240
●
VOS Match Channel-to-Channel (Note 5) LTC6241 S8
●
LTC6242 GN
●
TC VOS
Input Offset Voltage Drift (Note 6)
IB
Input Bias Current (Notes 4, 7)
●
LTC6241, LTC6242
0.5
●
0.5
LTC6240
●
IOS
Input Offset Current (Notes 4, 7)
LTC6241, LTC6242
0.2
●
LTC6240
0.2
●
VCM
CMRR
Input Voltage Range
Common Mode Rejection
Guaranteed by CMRR
●
–5
–5V ≤ VCM ≤ 3.5V
●
80
dB
●
76
dB
775
350
2700
●
V/mV
V/mV
150
60
360
●
V/mV
V/mV
CMRR Match
Channel-to-Channel (Note 5)
AVOL
Large Signal Voltage Gain
VO = –3.5V to 3.5V
RL = 10k
RL = 1k
624012fc
10
LTC6240/LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6240HVH/LTC6241HVH/LTC6242HVH) The ● denotes the specifications
which apply from –40°C to 125°C, otherwise specifications are at TA = 25°C. VS = ±5V, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MAX
UNITS
VOL
Output Voltage Swing Low (Note 9)
No Load
ISINK = 1mA
ISINK = 10mA
●
●
●
MIN
TYP
30
85
600
mV
mV
mV
VOH
Output Voltage Swing High (Note 9)
No Load
ISOURCE = 1mA
ISOURCE = 10mA
●
●
●
30
85
600
mV
mV
mV
PSRR
Power Supply Rejection
VS = 2.8V to 11V, VCM = 0.2V
●
83
dB
PSRR Match
Channel-to-Channel (Note 5)
●
82
dB
Minimum Supply Voltage (Note 10)
●
2.8
V
ISC
Short-Circuit Current
●
15
mA
IS
Supply Current per Amplifier
LTC6241, LTC6242
2.5
3.2
3.7
mA
mA
2.7
3.3
3.8
mA
mA
●
LTC6240
●
GBW
Gain Bandwidth Product
Frequency = 20kHz, RL = 1kΩ
●
12
MHz
SR
Slew Rate (Note 11)
AV = –2, RL = 1kΩ
●
5
V/µs
FPBW
Full Power Bandwidth (Note 12)
VOUT = 3VP-P, RL = 1kΩ
●
0.53
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 3: The LTC6240C/LTC6240HVC/LTC6241C/LTC6241HVC, LTC6242C/
LTC6242HVC are guaranteed to meet specified performance from 0°C to
70°C. They are designed, characterized and expected to meet specified
performance from –40°C to 85°C, but are not tested or QA sampled at
these temperatures. The LTC6240I/LTC6240HVI, LTC6241I/LTC6241HVI,
LTC6242I/LTC6242HVI are guaranteed to meet specified performance
from –40°C to 85°C. All versions of the LTC6240H/LTC6241H/LTC6242H
are guaranteed to meet specified performance
from –40°C to 125°C.
Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6240/LTC6241/LTC6242;
however, high electrostatic discharge can damage or degrade the device.
Use proper ESD handling precautions.
Note 5: Matching parameters are the difference between the two amplifiers
A and D and between B and C of the LTC6242; between the two amplifiers
of the LTC6241. CMRR and PSRR match are defined as follows: CMRR
and PSRR are measured in µV/V on the matched amplifiers. The difference
is calculated between the matching sides in µV/V. The result is converted
to dB.
Note 6: This parameter is not 100% tested.
Note 7: Bias current at TA = 25°C is 100% tested and guaranteed for the
LTC6240 in the S8 package. The LTC6240S5, LTC6241 and LTC6242 are
expected to achieve the same performance as the LTC6240S8. All parts are
guaranteed to meet specifications over temperature.
Note 8: Current noise is calculated from the formula: in = (2qIB)1/2
where q = 1.6 × 10–19 coulomb. The noise of source resistors up to
50GΩ dominates the contribution of current noise. See also Typical
Characteristics curve Noise Current vs Frequency.
Note 9: Output voltage swings are measured between the output and
power supply rails.
Note 10: Minimum supply voltage is guaranteed by the power supply
rejection ratio test.
Note 11: Slew rate is measured in a gain of –2 with RF = 1k and RG =
500Ω. On the LTC6240/LTC6241/LTC6242, VS = ±2.5V, VIN is ±1V and
VOUT slew rate is measured between –1V and +1V. On the LTC6240HV/
LTC6241HV/LTC6242HV, VIN is ±2V and VOUT slew rate is measured
between –2V and +2V.
Note 12: Full-power bandwidth is calculated from the slew rate:
FPBW = SR/πVP-P.
624012fc
11
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VOS Distribution LTC6241
VOS Temperature Coefficient
Distribution LTC6241
VOS Distribution LTC6241
120
90
VS = ±2.5V
80 SO-8 PACKAGE
16
VS = ±2.5V
DD PACKAGE
14
100
60
50
40
30
NUMBER OF UNITS
12
NUMBER OF UNITS
NUMBER OF UNITS
70
80
60
40
20
0
0
–50 –30 –10 10
30
50
INPUT OFFSET VOLTAGE (µV)
–350 –250 –150 –50 50 150 250
INPUT OFFSET VOLTAGE (µV)
70
6
0
350
–1.0 –0.6 –0.2 0.2 0.6 1.0
DISTRIBUTION (µV/°C)
18
VS = ±2.5V
30
14
NUMBER OF UNITS
20
15
10
Supply Current vs Supply Voltage
3.5
VS = 5V, 0
VCM = 2.5V
2 LOTS
–40°C TO 125°C
SO-8 AND SOT23
PACKAGES
16
12
10
8
6
4
5
2
0
–110 –90 –70 –50 –30 –10 10 30 50
INPUT OFFSET VOLTAGE (µV)
0
–0.6
70
0.2
0.6
1.0
1.4
DISTRIBUTION (µV/°C)
150
100
50
TA = 25°C
0
–50
TA = –55°C
–100
–150
1000
2
8
6
10
4
TOTAL SUPPLY VOLTAGE (V)
600
10
TA = 85°C
1
400
300
200
TA = 25°C
TA = 125°C
100
0
–100
–200
TA = 85°C
–300
0.1
0
VS = 5V, 0V
500
100
–250
12
Input Bias Current vs
Common Mode Voltage
700
TA = 25°C
6241 G05
0.5
6241 G04
VS = 5V, 0V
–200
–300
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT COMMON MODE VOLTAGE (V)
1.0
0
TA = 125°C
TA = 125°C
TA = 125°C
1.5
Input Bias Current vs Common
Mode Voltage
INPUT BIAS CURRENT (pA)
200
2.0
6241 G44
VS = 5V, 0V
250
TA = –55°C
2.5
1.8
INPUT BIAS CURRENT (pA)
300
TA = 25°C
3.0
0
–0.2
6241 G43
Offset Voltage vs Input Common
Mode Voltage
1.8
6241 G03
VOS Temperature Coefficient
Distribution LTC6240
VOS Distribution LTC6240
25
1.4
6241 G02
6241 G01
SUPPLY CURRENT PER AMP (mA)
–70
PERCENT OF UNITS
8
2
10
OFFSET VOLTAGE (µV)
10
4
20
35
VS = ±2.5V
2 LOTS
–55°C TO 125°C
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON MODE VOLTAGE (V)
6241 G06
–400
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
COMMON MODE VOLTAGE (V)
6241 G07
624012fc
12
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Saturation Voltage vs
Load Current (Output Low)
Input Bias Current vs Temperature
10
100
VS = 10V
VS = 5V
10
1
0.1
TA = 25°C
1
TA = 125°C
0.1
TA = –55°C
0.01
0.001
0.1
25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE (°C)
10
VS = 5V, 0V
OUTPUT HIGH SATURATION VOLTAGE (V)
VCM = VS/2
OUTPUT LOW SATURATION VOLTAGE (V)
INPUT BIAS CURRENT (pA)
1000
Output Saturation Voltage vs
Load Current (Output High)
10
1
LOAD CURRENT (mA)
6241 G08
VS = 5V, 0V
TA = 25°C
1
TA = 125°C
TA = –55°C
0.1
0.01
0.1
100
10
1
LOAD CURRENT (mA)
100
6241 G10
6241 G09
Gain Bandwidth and Phase
Margin vs Temperature
30
VS = ±5V
GAIN BANDWIDTH
VS = ±1.5V
10
0
–55 –35 –15
50
60
VS = ±5V
GAIN
40
10
0
–20
–40
–10
5 25 45 65 85 105 125
TEMPERATURE (°C)
10k
100k
VS = ±5V RISING
VS = ±2.5V RISING
OUTPUT IMPEDANCE (Ω)
VS = ±2.5V FALLING
20
GAIN BANDWIDTH
0
0
2
4
6
8
10
TOTAL SUPPLY VOLTAGE (V)
6241 G14
100
TA = 25°C
VS = ±2.5V
1
TA = 25°C
VS = ±2.5V
90
100
10
AV = 10
12
Common Mode Rejection Ratio vs
Frequency
AV = 2
AV = 1
0.10
6
4
–55 –35 –15
30
10
–80
100M
1M
10M
FREQUENCY (Hz)
1k
VS = ±5V FALLING
10
40
6241 G13
AV = –2
18 RF = 1k, RG = 500Ω
CONDITIONS: SEE NOTE 12
14
50
PHASE MARGIN
Output Impedance vs Frequency
16
60
–60
–20
10k
20
SLEW RATE (V/µs)
0
VS = ±1.5V
Slew Rate vs Temperature
8
20
VS = ±5V
20
6241 G12
12
40
VS = ±1.5V
30
70
TA = 25°C
CL = 5pF
RL = 1k
COMMON MODE REJECTION (dB)
20
60
GAIN (dB)
30
40
70
PHASE (DEG)
40
VS = ±1.5V
120
CL = 5pF
100
RL = 1k
VCM = VS/2
80
PHASE
80
70
60
50
40
30
20
10
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
6241 G15
0.01
10k
100k
1M
FREQUENCY (Hz)
10M
6241 G16
–10
10k
100k
1M
10M
FREQUENCY (Hz)
100M
6241 G17
624012fc
13
PHASE MARGIN (DEG)
50
PHASE MARGIN
80
GAIN BANDWIDTH (MHz)
70
CL = 5pF
RL = 1k 60
PHASE MARGIN (DEG)
GAIN BANDWIDTH (MHz)
VS = ±5V
Gain Bandwidth and Phase
Margin vs Supply Voltage
Open Loop Gain vs Frequency
LTC6240/LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Power Supply Rejection Ratio vs
Frequency
Channel Separation vs Frequency
–20
–40
–50
–60
–70
–80
–90
–100
–110
TA = 25°C
VS = ±2.5V
80
70
60
50
POSITIVE SUPPLY
40
30
20
NEGATIVE SUPPLY
100k
1M
10M
FREQUENCY (Hz)
1k
100M
10k
100k
1M
FREQUENCY (Hz)
40
TA = 25°C
0
TA = –55°C
TA = 125°C
–60
–80
1
2 3 4 5 6 7 8
TOTAL SUPPLY VOLTAGE (V)
9
40
SINKING
30
10
TA = 25°C
0
–10
–20
TA = 125°C
SOURCING
–30
–40
10
INPUT VOLTAGE (µV)
INPUT VOLTAGE (µV)
80
80
RL = 10k
40
RL = 1k
20
RL = 100k
60
RL = 10k
40
20
TA = –55°C
0
2.0 2.5 3.0 3.5 4.0 4.5
POWER SUPPLY VOLTAGE (±V)
5.0
0
0.5
1.0
1.5
2.0
OUTPUT VOLTAGE (V)
TA = 25°C
VS = ±5V
VS = ±5V
400
300
40
0
3.0
Offset Voltage vs Output Current
500
60
20
2.5
6241 G23
Open Loop Gain
100
TA = 25°C
VS = 5V, 0V
60
80
6241 G22
Open Loop Gain
100
TA = 25°C
VS = 3V, 0V
100
TA = 125°C
20
100M
10M
Open Loop Gain
TA = –55°C
6241 G21
120
100k
1M
FREQUENCY (Hz)
120
–50
1.5
–100
0
10k
6241 G20
INPUT VOLTAGE (µV)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
CHANGE IN OFFSET VOLTAGE (µV)
60
–40
4
Output Short Circuit Current vs
Power Supply Voltage
VCM = VS/2
–20
6
1k
50
20
8
6241 G19
Minimum Supply Voltage
80
10
0
100M
10M
6241 G18
100
CCM
12
2
10
0
–120
10k
VS = ±1.5V
14
OFFSET VOLTAGE (µV)
VOLTAGE GAIN (dB)
–30
Input Capacitance vs Frequency
16
INPUT CAPACITANCE (pF)
TA = 25°C
VS = ±2.5V
AV = 1
–10
90
POWER SUPPLY REJECTION RATIO (dB)
0
RL = 10k
RL = 1k
–20
TA = 125°C
200
100
TA = 25°C
0
–100
TA = –55°C
–200
–300
0
–40
–20
–60
0
1
2
3
4
OUTPUT VOLTAGE (V)
5
6241 G24
–400
–5 –4 –3 –2 –1 0 1 2 3
OUTPUT VOLTAGE (V)
4
5
6241 G25
–500
–50 –40 –30 –20 –10 0 10 20 30 40 50
OUTPUT CURRENT (mA)
6241 G26
624012fc
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Warm-Up Drift vs Time
Noise Voltage vs Frequency
60
20
15
VS = ±2.5V
10
5
VS = ±1.5V
0
TA = 25°C
VS = ±2.5V
VCM = 0V
50
VS = ±5V
0.1Hz to 10Hz Voltage Noise
40
30
20
10
0
–5
10
1
5 10 15 20 25 30 35 40 45 50 55 60
TIME AFTER POWER UP (s)
100
1k
FREQUENCY (Hz)
10k
TIME (1s/DIV)
6241 G27
6241 G28
50
10
Minimum Output Series
Resistance vs Capacitive Load
1000
75pF
1k
100
OVERSHOOT (%)
1k
–
RS
+
40
CL
30
RS = 10Ω
20
RS = 50Ω
1
10
VS = ±2.5V
AV = –1
0
10k
1k
FREQUENCY (Hz)
100
CAPACITIVE LOAD (pF)
10
100k
6241 G42
–
+
40
RS
CL
30
RS = 10Ω
20
RS = 50Ω
10
VS = ±2.5V
AV = –2
0
10
100
CAPACITIVE LOAD (pF)
1000
6241 G30
2.5
–
VIN
Settling Time vs Output Step
(Inverting)
+
TA = 25°C
VS = ±5V
2.5 AV = –1
VOUT
1k
1mV
1.5
2.0
1k
VOUT
1k
1mV
1.5
1mV
1.0
10mV
0.5
10mV
10mV
–
+
1mV
0.5
1k
VIN
2.0
1.0
10µF
1µF
3.0
TA = 25°C
VS = ±5V
3.0 A = 1
V
1k
1
6241 G45
3.5
SETTLING TIME (µs)
500Ω
10
Settling Time vs Output Step
(Non-Inverting)
75pF
50
100
6241 G29
Series Output Resistance and
Overshoot vs Capacitive Load
60
VS = ±2.5V
<30% OVERSHOOT
0.1
10pF 100pF 1000pF 0.01µF 0.1µF
CAPACITIVE LOAD
1000
SETTLING TIME (µs)
NOISE CURRENT (fA/√Hz)
60
TA = 25°C
VS = ±2.5V
VCM = 0V
0.1
100
6241 G11
Series Output Resistance and
Overshoot vs Capacitive Load
Noise Current vs Frequency
OVERSHOOT (%)
100k
OUTPUT SERIES RESISTANCE (Ω)
0
1000
VS = 5V, 0V
VOLTAGE NOISE (200nV/DIV)
TA = 25°C
NOISE VOLTAGE (nV/√Hz)
CHANGE IN OFFSET VOLTAGE (µV)
25
10mV
0
0
–4
–3
–2
–1
0
1
2
OUTPUT STEP (V)
3
4
6241 G31
–4
–3
–2
–1
0
1
2
OUTPUT STEP (V)
3
4
6241 G32
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Maximum Undistorted Output
Signal vs Frequency
Distortion vs Frequency
8
AV = –1
7
AV = +2
6
5
4
VS = ±2.5V
AV = 1
–40 V
OUT = 2VP-P
–30
–50
–50
VS = ±5V
AV = 1
–40 V
OUT = 2VP-P
RL = 1k, 2ND
–60
–70
RL = 1k, 3RD
–80
–60
RL = 1k, 2ND
–70
RL = 1k, 3RD
–80
3
TA = 25°C
2 VS = ±5V
HD2, HD3 < –40dBc
1
10k
100k
1M
FREQUENCY (Hz)
–90
10M
–90
–100
10k
100k
1M
FREQUENCY (Hz)
6241 G33
–100
10k
100k
1M
FREQUENCY (Hz)
–30
–50
–50
10M
6241 G35
Distortion vs Frequency
–30
Small Signal Response
VS = ±5V
AV = 2
–40 V
OUT = 2VP-P
DISTORTION (dBc)
VS = ±2.5V
AV = 2
–40 V
OUT = 2VP-P
–60
RL = 1k, 2ND
–70
–80
10M
6241 G34
Distortion vs Frequency
DISTORTION (dBc)
Distortion vs Frequency
–30
DISTORTION (dBc)
9
DISTORTION (dBc)
OUTPUT VOLTAGE SWINGING (VP-P)
10
0V
RL = 1k, 2ND
–60
–70
RL = 1k, 3RD
–80
RL = 1k, 3RD
VS = ±2.5V
AV = 1
RL = ∞
–90
–90
–100
10k
100k
1M
FREQUENCY (Hz)
10M
–100
10k
100k
1M
FREQUENCY (Hz)
10M
6241 G37
6241 G36
Large Signal Response
Large Signal Response
0V
6241 G38
Output Overdrive Recovery
0V
VIN
(1V/DIV)
0V
0V
VOUT
(2V/DIV)
VS = ±5V
AV = 1
RL = ∞
6241 G39
VS = ±2.5V
AV = –1
RL = 1k
6241 G40
VS = ±2.5V
AV = 3
RL = ∞
500ns/DIV
6241 G41
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Amplifier Characteristics
Figure 1 is a simplified schematic of the amplifier, which
has a pair of low noise input transistors M1 and M2. A
simple folded cascode Q1, Q2 and R1, R2 allow the input
stage to swing to the negative rail, while performing level
shift to the Differential Drive Generator. Low offset voltage
is accomplished by laser trimming the input stage.
Capacitor C1 reduces the unity cross frequency and improves the frequency stability without degrading the gain
bandwidth of the amplifier. Capacitor Cm sets the overall
amplifier gain bandwidth. The differential drive generator
supplies signals to transistors M3 and M4 that swing the
output from rail-to-rail.
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
follower. If the negative going input signal is less than
a diode drop below V–, no phase inversion occurs. For
input signals greater than a diode drop below V–, limit the
current to 3mA with a series resistor RS to avoid phase
inversion.
ESD
The LTC6240/LTC6241/LTC6242 have reverse-biased ESD
protection diodes on all input and outputs as shown in
Figure 1. If these pins are forced beyond either supply,
unlimited current will flow through these diodes. If the
current is transient and limited to one hundred milliamps
or less, no damage to the device will occur.
The amplifier input bias current is the leakage current of
these ESD diodes. This leakage is a function of the temperature and common mode voltage of the amplifier, as
shown in the Typical Performance Curves.
Noise
The LTC6240/LTC6241/LTC6242 exhibit exceptionally
low 1/f noise in the 0.1Hz to 10Hz region. This 550nVP-P
noise allows these op amps to be used in a wide variety
of high impedance low frequency applications, where
Zero-Drift amplifiers might be inappropriate due to their
charge injection.
In the frequency region above 1kHz the LTC6240/LTC6241/
LTC6242 also show good noise voltage performance. In
this frequency region, noise can easily be dominated by
the total source resistance of the particular application.
Specifically, these amplifiers exhibit the noise of a 3.1kΩ
resistor, meaning it is desirable to keep the source and
feedback resistance at or below this value, i.e. RS + RG||RFB
≤ 3.1kΩ. Above this total source impedance, the noise
voltage is not dominated by the amplifier.
Noise current can be estimated from the expression in =
√2qIB, where q = 1.6 • 10–19 coulombs. Equating √4kTRΔf
and R√2qIBΔf shows that for source resistors below 50GΩ
the amplifier noise is dominated by the source resistance.
See the Typical Characteristics curve Noise Current vs
Frequency.
VDD =
+2.5V
V+
ITAIL
M3
CM
V–
V+
DESD1
V+
DESD2
VIN+
DESD5
M1
VIN–
DIFFERENTIAL
DRIVE
GENERATOR
M2
VO
DESD6
C1
DESD3
DESD4
V–
V+
VSS =
–2.5V
V–
–
VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE
V
Q1
Q2
M4
BIAS
+2.5V
RS
R1
VIN
R2
V–
+
VOUT
LTC6240
–
6241 F01
–2.5V
Figure 1. Simplified Schematic
6241 F02
Figure 2. Unity Gain Follower Test Circuit
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Proprietary design techniques are used to obtain simultaneous low 1/f noise and low input capacitance. Low input
capacitance is important when the amplifier is used with
high value source and feedback resistors. High frequency
noise from the amplifier tail current source, ITAIL in Figure 1, couples through the input capacitance and appears
across these large source and feedback resistors. As an
example, the photodiode amplifier of Figure 15 on the last
page of this data sheet shows the noise results from the
LTC6241 and the results of a competitive CMOS amplifier.
The LTC6241 output is the ideal noise of a 1MΩ resistor
at room temperature, 130nV√Hz.
+2.5
+
1/4
LTC6242
1k
–
–2.5
1k
10Ω
+
1/4
LTC6242
1k
–
VIN
The circuit shown in Figure 3 can be used to achieve even
lower noise voltage. By paralleling 4 amplifiers the noise
voltage can be lowered by √4, or half as much noise. The
√ comes about from an RMS summing of uncorrelated
noise sources. This circuit maintains extremely high input
resistance, and has a 250Ω output resistance. For lower
output resistance, a buffer amplifier can be added without
influencing the noise.
Stability
The good noise performance of these op amps can be attributed to large input devices in the differential pair. Above
several hundred kilohertz, the input capacitance rises and
can cause amplifier stability problems if left unchecked.
When the feedback around the op amp is resistive (RF), a
pole will be created with RF , the source resistance, source
capacitance (RS, CS), and the amplifier input capacitance.
In low gain configurations and with RF and RS in even
the kilohm range (Figure 4), this pole can create excess
phase shift and possibly oscillation. A small capacitor CF
in parallel with RF eliminates this problem.
Low Noise Single-Ended Input to Differential Output
Amplifier
VO
1k
10Ω
Half the Noise
+
1/4
LTC6242
1k
–
The circuit on the first page of the data sheet is a low noise
single-ended input to differential output amplifier, with a
200k input impedance. The very low input bias current
of the LTC6241 allows for these large input and feedback
resistors. The 200k resistors, R1 and R2, along with C1
and C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is
used to cancel effects of input capacitance, while C4 adds
1k
10Ω
CF
RF
+
1/4
LTC6242
1k
–
–
RS
CIN
CS
OUTPUT
+
6241 F04
10Ω
1k
Figure 4. Compensating Input Capacitance
6241 F03
Figure 3. Parallel Amplifier Lowers Noise by 2x
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DIFFERENTIAL OUTPUT VOLTAGE DENSITY (nV/√Hz)
phase lead to compensate the phase lag of the second
amplifier. The op amp’s good input offset voltage match
and low input bias current means that the typical differential
output offset voltage is less than 40µV. A noise spectrum
plot of the differential output is shown in Figure 5.
140
VS = ±2.5V
TA = 25°C
120 –3dB BW = 80kHz
100
source equal to the input voltage prevents such leakage
problems. The guard ring should extend as far as necessary to shield the high impedance signal from any and
all leakage paths. Figure 6 shows the use of a guard ring
on the LTC6241 in a unity gain configuration. In this case
the guard ring is connected to the output and is shielding
the high impedance non-inverting input from V–. Figure 7
shows the inverting gain configuration.
A Digitally Programmable AC Difference Amplifier
80
60
40
20
0
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
The LTC6241 configured as a difference amplifier, can
be combined with a programmable gain amplifier (PGA)
to obtain a low noise high speed programmable difference amplifier. Figure 8 shows the LTC6241 based as a
single-supply AC amplifier. One LTC6241 op amp is used
at the circuit’s input as a standard four resistor difference
6241 F05
Figure 5. Differential Output Noise
LTC6241 S8
OUT+
NO SOLDER MASK
OVER THE GUARD RING
Achieving Low Input Bias Current
The DD package is leadless and makes contact to the PCB
beneath the package. Solder flux used during the attachment of the part to the PCB can create leakage current
paths and can degrade the input bias current performance
of the part. All inputs are susceptible because the backside
paddle is connected to V– internally. As the input voltage
changes or if V– changes, a leakage path can be formed
and alter the observed input bias current. For lowest bias
current, use the LTC6240/LTC6241 in the SO-8 and provide
a guard ring around the inputs that are tied to a potential
near the input voltage.
NO LEAKAGE
CURRENT
IN–
R
IN+
LEAKAGE
CURRENT
GUARD
RING
V–
LTC6241 F06
Figure 6. Sample Layout. Unity Gain Configuration, Using Guard
Ring to Shield High Impedance Input from Board Leakage
LTC6241 S8
OUT+
R
Layout Considerations and a PCB Guard Ring
In high source impedance applications such as pH probes,
photodiodes, strain gauges, et cetera, the low input bias
current of these parts requires a clean board layout to
minimize additional leakage current into a high impedance signal node. A mere 100GΩ of PC board resistance
between a 5V supply trace and an input trace adds 50pA
of leakage current, far greater then the input bias current of the operational amplifier. A guard ring around the
high-impedance input traces driven by a low-impedance
R
IN–
VIN
IN+
GND
V–
LTC6241 F07
Figure 7. Sample Layout. Inverting Gain Configuration, Using
Guard Ring to Shield High Impedance Input from Board Leakage
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V+
R3
C1
R1
G2
G1
G0
7
6
5
0.1µF
8
V1
LTC6910-2
OUT AGND IN V–
1
2
3
4
+
1/2
LTC6241
–
VOUT
R2
100Ω
R4
R7
C3
V2
C2
V+
R1 = R2 = R3 = R4
0.1µF
R5
–
1/2
LTC6241
1000pF
+
R6
20k
1
LT6650
2
5
VREF
1µF
3
1k
4
Example Design: Design a programmable gain AC difference amplifier, with a bandwidth of at least 10Hz to 100kHz,
an input impedance equal to or greater than 100kΩ, and
an output DC reference equal to 1V.
V+
1µF
DIGITAL INPUTS
G2 G1 GO
GAIN
0
0
1
1
0
0
1
1
0
–1
–2
–4
–8
–16
–32
–64
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
VOUT = (V1 – V2) GAIN + VREF
⎛ R5 ⎞
VREF = 0.4 • ⎜
+1
⎝ R6 ⎟⎠
R5 = 10k • ( 5 • VREF – 2) R6 = 20k
–3d BANDWIDTH = ( fHIGH – fLOW )
fHIGH =
contribute any significant error to the LT6650 reference
voltage. The LT6650 VREF voltage has a maximum error
of ±2% with 1% resistors. The upper –3dB frequency of
the amplifier is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
to twice the VREF voltage. At the maximum gain setting of
64, the maximum peak-to-peak difference between inputs
V1 and V2 is equal to twice VREF divided by 64.
1
GAIN
=
f
2 • π • R3 • C1 LOW 2 • π • R7 • C3
6241 F08
Figure 8. Wideband Difference Amplifier with High
Input Impedance and Digitally Programmable Gain
amplifier. The low bias current and current noise of the
LTC6241 allow the use of high valued input resistors, 100k
or greater. Resistors R1, R2, R3 and R4 are equal and the
gain of the difference amplifier is one. An LTC6910-2 PGA
amplifies the difference amplifier output with inverting
gains of –1, –2, –4, –8, –16, –32 and –64. The second
LTC6241 op amp is used as an integrator to set the DC
output voltage equal to the LT6650 reference voltage VREF.
The integrator drives the PGA analog ground to provide
a feedback loop, in addition to blocking any DC voltage
through the PGA. The reference voltage of the LT6650
can be set to a voltage from 400mV to V+ – 350mV with
resistors R5 and R6. If R6 is 20k or less, the error due
to the LT6650 op amp bias current is negligible. The low
voltage offset and drift of the LTC6241 integrator will not
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
• R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
c. Select R7 equal to one 1M and set the lower –3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz)
= 1uF. Lower gains settings will give a lower f3dB.
d. Calculate the value of R5 to set the LT6650 reference
equal to 1V;
VREF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF – 1). For
R6 = 20kΩ, R5 = 30kΩ
With VREF = 1V the maximum input difference voltage
is equal to 2V/64 = 31.2mV.
40nVpp Noise, 0.05µV/°C Drift, Chopped FET
Amplifier
Figure 9’s circuit combines the ±5V rail-to-rail performance
of the LTC6241HV with a pair of extremely low noise JFETs
configured in a chopper based carrier modulation scheme
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to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demanding transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifier.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1µV offset specification.
The LTC1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelated to 60Hz, provides excellent immunity to harmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
5V
TO LTC201 V + PIN
–5V
TO LTC201 V – PIN
1µF
5V
5V
18.5kHz
V+
74C90 ÷ 10
DIV LTC1799 OUT
RSET
5V
+
+
1µF
74C74 ÷ 2
Q
Q
925Hz
54.2k*
TO
Ø1
POINTS
5V
Ø1
TO
Ø2
POINTS
8
898Ω**
30.1Ω
INPUT
898Ω**
6
7
Ø2
S1
S2
0.01µF
11
10
9
Ø2
1µF
1
–
LSK389
499Ω**
1µF
A1
LTC6241HV
+
3
2
S3
S4
10M
–5V
240k
14
15
16
10k
Ø1
1µF
* = 0.1% METAL FILM RESISTOR
** = 1% METAL FILM RESISTOR
= LTC201 QUAD
= LSK389
= LINEAR INTEGRATED SYSTEMS
FREMONT, CA
NOISE = 40nVP-P 0.1Hz TO 10Hz
OFFSET = 1µV
DRIFT = 0.05µV/°C
R2 +1
GAIN =
10
OPEN-LOOP GAIN = 10 9
I BIAS = 500pA
–
A2
LTC6241HV
OUTPUT
+
R2
10k
R1
10Ω
6241 F09
Figure 9. Ultra Low Noise Chopper Amplifier
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The noise measured over a 50 second interval, in Figure 10,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is attributed to the input JFET’s die size and current density.
VERT = 20nV/DIV
HORIZ = 5s/DIV
6241 F10
Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth
Low Noise Shock Sensor Amplifiers
Figures 11 and 12 show the amplifiers realizing two different approaches to amplifying signals from a capacitive
sensor. The sensor in both cases is a 770pF piezoelectric
shock sensor accelerometer, which generates charge under
physical acceleration.
Figure 11 shows the classical “charge amplifier” approach.
The LTC6240 is in the inverting configuration so the sensor
looks into a virtual ground. All of the charge generated
by the sensor is forced across the feedback capacitor
by the op amp action. Because the feedback capacitor
is 100 times smaller than the sensor, it will be forced to
100 times what would have been the sensor’s open circuit
voltage. So the circuit gain is 100. The benefit of this approach is that the signal gain of the circuit is independent
of any cable capacitance introduced between the sensor
and the amplifier. Hence this circuit is favored for remote
accelerometers where the cable length may vary. Difficulties
with the circuit are inaccuracy of the gain setting with the
small capacitor, and low frequency cutoff due to the bias
resistor working into the small feedback capacitor.
Figure 12 shows a non-inverting amplifier approach. This
approach has many advantages. First of all, the gain is set
accurately with resistors rather than with a small capacitor. Second, the low frequency cutoff is dictated by the
bias resistor working into the large 770pF sensor, rather
than into a small feedback capacitor, for lower frequency
response. Third, the non-inverting topology can be paralleled and summed (as shown) for scalable reductions in
voltage noise. The only drawback to this circuit is that the
parasitic capacitance at the input reduces the gain slightly.
This circuit is favored in cases where parasitic input
capacitances such as traces and cables will be relatively
small and invariant.
VS+
+
+
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
CABLE HAS
UNKNOWN C
LTC6240
–
Cf
7.7pF
Rf
1G
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
1/2
LTC6241HV
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
–
100Ω
VOUT = 110mV/g
MAIN
GAIN-SETTING
ELEMENT IS A
CAPACITOR
1G
Figure 11. Classical Inverting Charge Amplifier
10k
VOUT
1k
+
1/2
LTC6241HV
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
–
100Ω
6241 F11
1k
VOUT = 110mV/g
VS = ±1.4V to ±5.5V
BW = 0.2Hz to 10kHz
VS–
10k
6241 F12
Figure 12. Low Noise Non-Inverting Shock Sensor Amplifier
624012fc
22
LTC6240/LTC6241/LTC6242
U
U
W
U
APPLICATIO S I FOR ATIO
1M Transimpedance Amplifier with 43nV/√Hz
Output Noise
By achieving an output swing of 50V before attenuation,
the circuit provides an output swing to 5V after attenuation. The 10M resistor sets the gain of the TIA stage
and has a noise density of 400nV/√Hz. After attenuation,
the effective TIA gain drops to 1M while the noise floor
drops to 40nV/√Hz, which clearly dominates the observed
43nV/√Hz. Note the additional benefit that the offset voltage
of the op amp is divided by 10. Worst case output offset
for this circuit is 150µV over temperature.
In a normal 1M transimpedance amplifier, like that shown
on the back page of this data sheet, the output noise density
must be at least 130nV/√Hz at room temperature. This is
true even should the op amp be perfectly noiseless, because
the 1M resistor provides 130nV/√Hz of voltage noise at
room temperature independently of the op amp.
The circuit of Figure 13 provides an overall transimpedance
gain of 1MΩ, but it has an output noise density of only
43nV/√Hz, about 1/3 of the normal transimpedance amplifier. It does this by taking a higher initial transimpedance
gain of 10M and then attenuating by a factor of 10. The
transistor section provides voltage gain and works on a
54V supply voltage to guarantee adequate output swing.
Reference Buffer
Figure 14 shows the LTC6240 being utilized as a buffer
in conjunction with the LT1019 reference. The passive
R-C filter attenuates the reference noise and the LTC6240
provides a low noise buffer, resulting in an output noise
of 8nV/√Hz.
54V
33k
0.3pF
MPSA06
10M
1%
5V
10M GAIN
(10V/µA)
+
3pF
PHOTODIODE
MPSA06
LTC6240HV
10k
–
–1.5V
10k
–5V
2.4k 43k
VOUT
1M GAIN
(1V/µA)
1k
1%
100pF
1k
9.09k
1%
1/4W
–5V
6241 F13
Figure 13. 1M Transimpedance Amplifier with 43nV/√Hz Output Noise
5V
LT1019-2.5
180nV/√Hz
1M
+
1µF
LTC6240HV
8nV/√Hz
–
–5V
0.2Ω
VOUT
10µF
CERAMIC
OR FILM
6241 F14
Figure 14. Low Noise Reference Buffer
624012fc
23
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 ±0.05
3.50 ±0.05
1.65 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
5.00 ±0.10
(2 SIDES)
R = 0.20
TYP
3.00 ±0.10
(2 SIDES)
0.40 ± 0.10
9
16
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
4.40 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 ±.005
.254 MIN
.150 – .165
.0165 ± .0015
.0250 BSC
.189 – .196*
(4.801 – 4.978)
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
16 15 14 13 12 11 10 9
.004 – .0098
(0.102 – 0.249)
.009
(0.229)
REF
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
GN16 (SSOP) 0204
1
2 3
4
5 6
7
8
624012fc
24
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
5
0.38 ± 0.10
8
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 1203
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
624012fc
25
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1.90 BSC
S5 TSOT-23 0302 REV B
624012fc
26
LTC6240/LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
2
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
624012fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC6240/LTC6241/LTC6242
U
TYPICAL APPLICATIO
150kHz 3RD ORDER BUTTERWORTH FILTER
1MΩ TIA
R1
866Ω
+
1/2
LTC6241
–
RF
1M
C1
1500pF
R2
1.69k
R3
2k
C2
1500pF
+1.5V
+
1/2
LTC6241
C3
180pF
–
SFH213FA
OR EQUIVALENT
(≤4pF)
–1.5V
6241 TA02a
CF
1pF
–1.5V
Figure 15. Ultralow Noise 1MΩ 150kHz Photodiode Amplifier
Competition Output Noise Spectrum. Op Amp Noise Dominates;
Performance Compromised
30nV/√Hz PER DIV
30nV/√Hz PER DIV
LTC6241 Output Noise Spectrum. 1MΩ Resistor Noise
Dominates; Ideal Performance
0V
0V
1kHz
10kHz/DIV
101kHz
1kHz
10kHz/DIV
101kHz
6241 TA02b
6241 TA02c
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1151
±15V Zero-Drift Op Amp
Dual High Voltage Operation ±18V
LT1792
Low Noise Precision JFET Op Amp
6nV/√Hz Noise, ±15V Operation
LTC2050
Zero-Drift Op Amp
2.7 Volt Operation, SOT-23
LTC2051/LTC2052
Dual/Quad Zero-Drift Op Amp
Dual/Quad Version of LTC2050 in MS8/GN16 Packages
LTC2054/LTC2055
Single/Dual Zero-Drift Op Amp
Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages
LTC6244
Dual 50MHz Rail-to-Rail Op Amp
100µV VOS(MAX), 1pA IBIAS, 40V/µV, Slew Rate
624012fc
28 Linear Technology Corporation
LT 0107 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2005