LTC3561A 1A, 4MHz, Synchronous Step-Down DC/DC Converter FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The LTC®3561A is a constant frequency, synchronous step-down DC/DC converter. Intended for medium power applications, it operates from a 2.5V to 5.5V input voltage range and has a user configurable operating frequency up to 4MHz, allowing the use of tiny, low cost capacitors and inductors 1mm or less in height. The output voltage is adjustable from 0.8V to 5.5V. Internal synchronous power switches provide high efficiency. The LTC3561A’s current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Uses Tiny Capacitors and Inductor High Frequency Operation: Up to 4MHz Low RDS(ON) Internal Switches: 0.15Ω High Efficiency: Up to 96% Stable with Ceramic Capacitors Current Mode Operation for Excellent Line and Load Transient Response Short-Circuit Protected Low Dropout Operation: 100% Duty Cycle Low Shutdown Current: IQ ≤ 1μA Low Quiescent Current: 330μA Output Voltages from 0.8V to 5V VIN: 2.5V to 5.5V Small 8-Lead 3mm × 3mm DFN Package To further maximize battery life, the P-channel MOSFET is turned on continuously in dropout (100% duty cycle). In shutdown, the device draws <1μA. APPLICATIONS ■ ■ ■ ■ ■ , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6498466, 6611131. Notebook Computers Digital Cameras Cellular Phones Handheld Instruments Board Mounted Power Supplies TYPICAL APPLICATION Efficiency and Power Loss vs Output Current Step-Down 2.5V/1A Regulator 100 VIN 2.5V TO 5.5V 80 10μF 22pF LTC3561A ITH 16.9k 680pF 249k SHDN/RT SGND 549k VFB VOUT 2.5V 1A 22μF EFFICIENCY (%) 2.2μH SW 0.1 70 60 0.01 50 40 VOUT = 2.5V fO = 1MHz 30 20 PGND 118k 0.001 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 1 3561a TA01a POWER LOSS (W) PVIN SVIN 1 90 100 1000 10 OUTPUT CURRENT (mA) 0.0001 10000 3561A TA01b 3561af 1 LTC3561A ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) PVIN, SVIN Voltages ..................................... –0.3V to 6V VFB, ITH, SHDN/RT Voltages ..........–0.3V to (VIN + 0.3V) SW Voltage ..................................–0.3V to (VIN + 0.3V) Operating Junction Temperature Range (Notes 2, 5, 8) ........................................ –40°C to 125°C Storage Temperature Range................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) .................. 300°C TOP VIEW SHDN/RT 1 8 ITH SGND 2 9 SW 3 7 VFB 6 SVIN 5 PVIN PGND 4 DD PACKAGE 8-LEAD (3mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W EXPOSED PAD (PIN 9) IS SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3561AEDD#PBF LTC3561AEDD#TRPBF LDKB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3561AIDD#PBF LTC3561AIDD#TRPBF LDKB 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2) SYMBOL PARAMETER VIN Operating Voltage Range CONDITIONS IFB Feedback Pin Input Current (Note 3) VFB Feedback Voltage (Note 3) ΔVLINEREG Reference Voltage Line Regulation VIN = 2.5V to 5.5V ΔVLOADREG Output Voltage Load Regulation ITH = 0.55V to 0.9V gm(EA) Error Amplifier Transconductance ITH Pin Load = ±5μA (Note 3) MIN TYP 2.5 ● ● 0.784 MAX UNITS 5.5 V ±0.1 μA 0.8 0.816 V 0.04 0.2 %/V 0.02 0.2 % 300 μS 3561af 2 LTC3561A ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2) SYMBOL PARAMETER IS fOSC Input DC Supply Current (Note 4) Active Mode Shutdown Shutdown Threshold High Active Oscillator Resistor Oscillator Frequency ILIM Peak Switch Current Limit RT = 125k (Note 7) VFB = 0.5V RDS(ON) Top Switch On-Resistance (Note 6) Bottom Switch On-Resistance (Note 6) ISW(LKG) Switch Leakage Current VIN = 5V, VSHDN/RT = 3.6V, VSW = 0V or 5V VUVLO Undervoltage Lockout Threshold VIN Ramping Down 10% to 90% of Regulation VSHDN/RT tSOFT-START CONDITIONS MIN TYP MAX 2.25 330 0.1 VIN – 0.6 125k 2.5 2.0 450 1 VIN – 0.4 1M 2.8 4 2.5 0.15 0.18 Ω 0.13 0.16 Ω 0.01 1 μA 1.8 2.1 2.4 V 0.5 0.8 1 VFB = 0.75V VSHDN/RT = 3.6V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3561AEDD is guaranteed to meet specified performance specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3561AIDD is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: The LTC3561A is tested in a feedback loop which servos VFB to the midpoint for the error amplifier (VITH = 0.7V). Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. 1.3 UNITS μA μA V Ω MHz MHz A ms Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formulas: TJ = TA + (PD • 43°C/W) Note 6: Switch on-resistance is sampled at wafer level measurements and assured by design, characterization and correlation with statistical process controls. Note 7: 4MHz operation is guaranteed by design but not production tested and is subject to duty cycle limitations (see Applications Information). Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3561af 3 LTC3561A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 3.6V, fO = 1MHz, unless otherwise noted. Efficiency vs Input Voltage 100 VOUT = 1.8V IOUT = 100mA EFFICIENCY (%) EFFICIENCY (%) IOUT = 1A 85 80 75 VOUT = 1.8V 90 90 IOUT = 10mA 70 65 80 70 70 60 50 40 30 20 55 10 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 100 1000 10 OUTPUT CURRENT (mA) 1 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 10000 100 1000 10 OUTPUT CURRENT (mA) 1 10000 3561A G03 Load Regulation 0.4 VOUT = 1.8V ILOAD = 400mA Line Regulation 0.6 VOUT = 1.8V 0.3 0.4 VOUT = 1.8V ILOAD = 400mA 2.2μH 92 91 1μH 90 VOUT ERROR (%) VOUT ERROR (%) 4.7μH 93 EFFICIENCY (%) 40 3561A G02 Efficiency vs Frequency 94 50 20 VIN = 2.7V VIN = 3.6V VIN = 4.2V 3561A G01 95 60 30 0 5.5 VOUT = 1.5V 90 80 60 50 0.2 0.1 0 –0.1 89 –0.2 88 0 1 3 2 FREQUENCY (MHz) 4 5 0 200 –0.6 2.5 400 600 800 1000 1200 1400 OUTPUT CURRENT(mA) 4 805 800 795 100 125 3561A G08 4.5 4.0 3.5 INPUT VOLTAGE(V) 5.5 Frequency Variation vs VIN 4 2 0 –2 –6 –50 5.0 6 –4 790 3.0 3561A G07 FREQUENCY VARIATION (%) 810 FREQUENCY VARIATION (%) 6 50 25 75 0 TEMPERATURE(°C) –0.2 Frequency Variation vs Temperature 815 –25 0.0 3561A G06 Reference Voltage vs Temperature 785 –50 0.2 –0.4 3561A G05 REFERENCE VOLTAGE (mV) Efficiency vs Output Current 100 EFFICIENCY (%) 95 Efficiency vs Output Current 100 2 0 –2 –4 –6 –25 50 25 75 0 TEMPERATURE(°C) 100 125 3561A G09 –8 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 3561A G10 3561af 4 LTC3561A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 3.6V, fO = 1MHz, unless otherwise noted. 0.30 0.20 0.25 RDS(ON) (Ω) RDS(ON) (Ω) MAIN SWITCH 0.15 SYNCHRONOUS SWITCH 300 DYNAMIC SUPPLY CURRENT (μA) 0.25 0.10 Dynamic Supply Current vs Input Voltage RDS(ON) vs Temperature RDS(ON) vs Input Voltage 0.20 MAIN SWITCH 0.15 SYNCHRONOUS SWITCH 0.10 0.05 0.05 4.5 4.0 3.5 INPUT VOLTAGE (V) 3.0 5.0 0.0 –50 5.5 –25 50 25 75 0 TEMPERATURE (°C) 100 3561A G11 240 230 300 280 260 240 100 3.5 4 VIN (V) 4.5 125 Switch Leakage vs Temperature MAIN SWITCH 1500 1000 0 5.5 5 500 SYNCHRONOUS SWITCH 500 220 75 50 25 TEMPERATURE (°C) 3 600 2000 320 0 250 3561A G13 2500 VOUT = 1.8V ILOAD = 0A 200 –50 –25 260 Switch Leakage vs Input Voltage SWITCH LEAKAGE (pA) SUPPLY CURRENT (mA) 340 270 3561A G12 Supply Current vs Temperature 360 280 220 2.5 125 SWITCH LEAKAGE (nA) 0.0 2.5 VOUT = 1.8V 290 ILOAD = 0A 0 1 400 300 SYNCHRONOUS SWITCH 200 MAIN SWITCH 100 4 3 2 INPUT VOLTAGE(V) 5 3561A G14 6 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 125 3561A G16 3561A G15 Switching Waveforms 100 Start-Up from Shutdown SHDN/RT 2V/DIV SW 2V/DIV VOUT 50mV/DIV AC COUPLED VOUT 1V/DIV IL 200mA/DIV IL 1A/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 5mA 4μs/DIV 3561A G18 VIN = 3.6V VOUT = 1.8V ILOAD = 0A 200μs/DIV 3561A G20 3561af 5 LTC3561A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 3.6V, fO = 1MHz, unless otherwise noted. Start-Up from Shutdown Load Step Load Step SHDN/RT 2V/DIV VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED VOUT 1V/DIV IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV IL 1A/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 1A 200μs/DIV 3561A G21 3561A G23 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 0A to 1A Load Step 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 20mA to 1A 3561A G24 VOUT Short to Ground VOUT 100mV/DIV AC COUPLED VOUT 1V/DIV IL 1A/DIV IL 2A/DIV ILOAD 1A/DIV 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 200mA to 1A 3561A G25 VIN = 3.6V VOUT = 1.8V ILOAD = 0A 40μs/DIV 3561A G26 3561af 6 LTC3561A PIN FUNCTIONS SHDN/RT (Pin 1): Combination Shutdown and Timing Resistor Pin. The oscillator frequency is programmed by connecting a resistor from this pin to ground. Forcing this pin to SVIN causes the device to be shut down. In shutdown all functions are disabled. SVIN (Pin 6): The Signal Power Pin. All active circuitry is powered from this pin. Must be closely decoupled to SGND. SVIN must be greater than or equal to PVIN. VFB (Pin 7): Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.8V. SGND (Pin 2): Signal Ground. All SGND and PGND pins must be connected together through a thick copper trace or ground plane. ITH (Pin 8): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0.4V to 1.4V. SW (Pin 3): The Switch Node Connection to the Inductor. This pin swings from PVIN to PGND. Exposed Pad (Pin 9): Signal Ground. All small-signal components and compensation components should be connected to this ground (see Board Layout Considerations). Must be soldered to electrical ground on PCB. All SGND and PGND pins must be connected together through a thick copper trace or ground plane. PGND (Pin 4): Power Ground. Connect to the (–) terminal of COUT, and (–) terminal of CIN. All SGND and PGND pins must be connected together through a thick copper trace or ground plane. PVIN (Pin 5): Main Supply Pin. Must be closely decoupled to PGND. PIN NAME 1 SHDN/RT 2 SGND DESCRIPTION MIN NOMINAL (V) TYP MAX MIN MAX Shutdown/Timing Resistor –0.3 0.8 SVIN –0.3 SVIN + 0.3 PVIN –0.3 PVIN + 0.3 Signal Ground Switch Node ABSOLUTE MAX (V) 0 3 SW 4 PGND Main Power Ground 0 5 PVIN Main Power Supply –0.3 5.5 –0.3 SVIN + 0.3 6 SVIN Signal Power Supply 2.5 5.5 –0.3 6 7 VFB Output Feedback Pin 0 1.0 –0.3 SVIN + 0.3 8 ITH Error Amplifier Compensation and Run Pin 1.4 –0.3 SVIN + 0.3 0 0.4 0.8 3561af 7 LTC3561A BLOCK DIAGRAM 0.8V SVIN SGND ITH PVIN 6 2 8 5 PMOS CURRENT COMPARATOR ITH LIMIT VOLTAGE REFERENCE BCLAMP + + – VFB 7 – ERROR AMPLIFIER VB – + BURST COMPARATOR SLOPE COMPENSATION OSCILLATOR 3 SW + LOGIC NMOS COMPARATOR – – REVERSE COMPARATOR + 4 PGND 1 3561A BD SHDN/RT 3561af 8 LTC3561A OPERATION The LTC3561A uses a constant frequency, current mode architecture. The operating frequency is determined by the value of the RT resistor. VFB decrease slightly. This decrease in VFB causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. The output voltage is set by an external divider returned to the VFB pin. An error amplifier compares the divided output voltage with the reference voltage of 0.8V and adjusts the peak inductor current accordingly. The main control loop is shut down by pulling the SHDN/RT pin to SVIN, resetting the internal soft-start. Re-enabling the main control loop by releasing the SHDN/RT pin activates the internal soft-start, which slowly ramps the output voltage over approximately 0.8ms until it reaches regulation. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle. Current flows through this switch into the inductor and the load, increasing until the peak inductor current reaches the limit set by the voltage on the ITH pin. Then the top switch is turned off, the bottom switch is turned on, and the energy stored in the inductor forces the current to flow through the bottom switch, and the inductor, out into the load until the next clock cycle. The peak inductor current is controlled by the voltage on the ITH pin, which is the output of the error amplifier. The output is developed by the error amplifier comparing the feedback voltage, VFB, to the 0.8V reference voltage. When the load current increases, the output voltage and Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC3561A incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2.1V to prevent unstable operation. 3561af 9 LTC3561A APPLICATIONS INFORMATION A general LTC3561A application circuit is shown in Figure 4. External component selection is driven by the load requirement, and begins with the selection of the inductor L1. Once L1 is chosen, CIN and COUT can be selected. Operating Frequency Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency, fO, of the LTC3561A is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: RT ≈ 5 × 107 (fO)–1.6508 (kΩ) Inductor Selection The operating frequency, fO, has a direct effect on the inductor value, which in turn influences the inductor ripple current, ΔIL: ΔIL = A reasonable starting point for setting ripple current is ΔIL = 0.4 • IOUT(MAX), where IOUT(MAX) is 1A. The largest ripple current ΔIL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: where fO is in kHz, or can be selected using Figure 1. The minimum frequency is internally set at around 200kHz 5000 ⎛ V ⎞ • ⎜1− OUT ⎟ V IN ⎠ ⎝ The inductor ripple current decreases with larger inductance or frequency, and increases with higher VIN or VOUT. Accepting larger values of ΔIL allows the use of lower inductances, but results in higher output ripple voltage, greater core loss and lower output capability. L= The maximum usable operating frequency is limited by the minimum on-time and the duty cycle. This can be calculated as: V fO(MAX) ≈ 6.67 • OUT (MHz) VIN(MAX) VOUT fO • L VOUT fO • ΔIL ⎛ VOUT ⎞ • ⎜1− ⎟ ⎝ V IN(MAX) ⎠ Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs TA = 25°C 4500 FREQUENCY (kHz) 4000 3500 3000 2500 2000 1500 1000 500 0 0 400 800 1200 RT (kΩ) 1600 3561A F01 Figure 1. Frequency vs RT 10 3561af LTC3561A APPLICATIONS INFORMATION size requirements and any radiated field/EMI requirements than on what the LTC3561A requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3561A applications. Table 1. Representative Surface Mount Inductors MANUFACTURER PART NUMBER MAX DC VALUE CURRENT Toko A914BYW-1R2M=P3: D52LC 1.2μH A960AW-1R2M=P3: D518LC Coilcraft Sumida Taiyo Yuden DCR HEIGHT 2.15A 44mΩ 2mm 1.2μH 1.8A 46mΩ 1.8mm DB3015C-1068AS-1R0N 1.0μH 2.1A 43mΩ 1.5mm DB3018C-1069AS-1R0N 1.0μH 2.1A 45mΩ 1.8mm DB3020C-1070AS-1R0N 1.0μH 2.1A 47mΩ 2mm A914BYW-2R2M-D52LC 2.2μH 2.05A 49mΩ 2mm A915AY-2ROM-D53LC 3.3A 22mΩ 3mm 2.0μH LPO1704-122ML 1.2μH 2.1A 80mΩ 1mm D01608C-222 2.2μH 2.3A 70mΩ 3mm LP01704-222M 2.2μH 2.4A 120mΩ 1mm CR32-1R0 1.0μH 2.1A 72mΩ CR5D11-1R0 1.0μH 2.2A 40mΩ 1.2mm 3mm CDRH3D14-1R2 1.2μH 2.2A 36mΩ 1.5mm CDRH4D18C/LD-1R1 1.1μH 2.1A 24mΩ CDRH4D28C/LD-1R0 1.0μH 3.0A 2mm 17.5mΩ 3mm CDRH4D28C-1R1 1.1μH 3.8A CDRH4D28-1R2 1.2μH 2.56A 23.6mΩ 3mm 22mΩ 3mm CDRH6D12-1R0 1.0μH 2.80A 37.5mΩ 1.5mm CDRH4D282R2 2.2μH 2.04A 23mΩ CDC5D232R2 2.2μH 2.16A 30mΩ 2.5mm 3mm NPO3SB1ROM 1.0μH 2.6A 27mΩ 1.8mm N06DB2R2M 2.2μH 3.2A 29mΩ 3.2mm N05DB2R2M 2.2μH 2.9A 32mΩ 2.8mm Murata LQN6C2R2M04 2.2μH 3.2A 24mΩ 5mm FDK MIPW3226DORGM 0.9μH 1.4A 80mΩ 1mm Catch Diode Selection Although unnecessary in most applications, a small improvement in efficiency can be obtained in a few applications by including the optional diode D1 shown in Figure 4, which conducts when the synchronous switch is off. In pulse skip mode, the synchronous switch is turned off at a low current and the remaining current will be carried by the optional diode. It is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. The main problem with Schottky diodes is that their parasitic capacitance reduces the efficiency, usually negating the possible benefits for LTC3561A circuits. Another problem that a Schottky diode can introduce is higher leakage current at high temperatures, which could reduce the low current efficiency. Remember to keep lead lengths short and observe proper grounding (see Board Layout Considerations) to avoid ringing and increased dissipation when using a catch diode. Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS ≈ IMAX VOUT (VIN − VOUT ) VIN where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ΔIL/2. This formula has a maximum at VIN = 2VOUT, where IRMS ≅ IOUT/2. This simple worst case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1μF to 1μF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. Output Capacitor (COUT) Selection The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance 3561af 11 LTC3561A APPLICATIONS INFORMATION is adequate for filtering. The output ripple (ΔVOUT) is determined by: ⎛ 1 ⎞ ΔVOUT ≈ ΔIL ⎜ESR + ⎟ 8fO COUT ⎠ ⎝ where fO = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. With ΔIL = 0.4 • IOUT(MAX) the output ripple will be less than 100mV at maximum VIN, a minimum COUT value of 10μF and fO = 1MHz with: ESRCOUT < 150mΩ Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and is often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, a high voltage and temperature coefficient and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer (SP) capacitors. In most cases, 0.1μF to 1μF of ceramic capacitors should also be placed close to the LTC3561A in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before their ESR becomes effective. Also, ceramic caps are prone to temperature effects which require the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, TDK and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation 3561af 12 LTC3561A APPLICATIONS INFORMATION components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2 to 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor value of approximately: COUT ≈ 2.5 ΔIOUT fO • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10μF ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3561A develops a 0.8V reference voltage between the feedback pin, VFB, and the signal ground as shown in Figure 4. The output voltage is set by a resistive divider according to the following formula: ⎛ R2⎞ VOUT ≈ 0.8V ⎜1+ ⎟ ⎝ R1⎠ Keeping the current small (<5μA) in these resistors maximizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Shutdown and Soft-Start The SHDN/RT pin is a dual purpose pin that sets the oscillator frequency and provides a means to shut down the LTC3561A. This pin can be interfaced with control logic in several ways, as shown in Figure 2 and Figure 3. In both configurations, Run = “0” shuts down the LTC3561A and Run = “1” activates the LTC3561A. By activating the LTC3561A, an internal soft-start slowly ramps the output voltage up until regulation. Soft-start prevents surge currents from VIN by gradually ramping the output voltage up during start-up. The output will ramp from zero to full scale over a time period of approximately 0.8ms. This prevents the LTC3561A from having to quickly charge the output capacitor and thus supplying an excessive amount of instantaneous current. SHDN/RT SHDN/RT RT RT RUN SVIN 1M RUN 3561A F02 3561A F03 Figure 2. SHDN/RT Pin Activated with a Logic Input Figure 3. SHDN/RT Pin Activated with a Switch 3561af 13 LTC3561A APPLICATIONS INFORMATION Checking Transient Response The OPTI-LOOP® compensation allows the transient response to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling time at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the circuit on page 1 of this data sheet will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where VIN + C6 The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with R and the bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor CF can be added to improve the high frequency response, as shown in Figure 4. Capacitor CF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. Although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage VIN drops toward VOUT, the load step capability OPTI-LOOP is a registered trademark of Linear Technology Corporation. R6 CIN SVIN PVIN C8 PGND ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. SW PGND LTC3561A SGND + D1 OPTIONAL VOUT COUT C5 CF ITH RC CITH VFB R2 SGND PGND SHDN/RT RT CC PGND PGND R1 3561A F04 SGND SGND GND SGND SGND Figure 4. LTC3561A General Schematic 3561af 14 LTC3561A APPLICATIONS INFORMATION does decrease due to the decreasing voltage across the inductor. Applications that require large load step capability near dropout should use a different topology such as SEPIC, Zeta or single inductor, positive buck/boost. In some applications, a more severe transient can be caused by switching in loads with large (>1μF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot Swap™ controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. 1 POWER LOSS (W) VIN = 3.6V VOUT = 1.2V TO 1.8V fO = 1MHz 0.1 0.01 0.001 0.1 1 10 100 1000 LOAD CURRENT (mA) 10000 3561A F01 Figure 5. Power Loss vs Load Currrent Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3561A circuits: 1) LTC3561A VIN current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R Losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. Hot Swap is a trademark of Linear Technology Corporation. 3561af 15 LTC3561A APPLICATIONS INFORMATION Thermal Considerations In a majority of applications, the LTC3561A does not dissipate much heat due to its high efficiency. However, in applications where the LTC3561A is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3561A from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3561A is in dropout at an input voltage of 3.3V with a load current of 1A. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the P-channel switch is 0.17Ω. Therefore, power dissipated by the part is: PD = I2 • RDS(ON) = 170mW The DD8 package junction-to-ambient thermal resistance, θJA, will be in the range of about 43°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125°C. Design Example As a design example, consider using the LTC3561A in a portable application with a Li-Ion battery. The battery provides a VIN = 2.5V to 4.2V. The load requirement is a maximum of 1A, but most of the time it will be in standby mode, requiring only 10mA. The output voltage is VOUT = 1.8V. Since the load still needs power in standby, Burst Mode operation is selected for good low load efficiency. First, calculate the timing resistor for 1MHz operation: RT = 5 • 107 (103)–1.6508 = 557.9k Use a standard value of 549k. Next, calculate the inductor value for about 40% ripple current at maximum VIN: L= 1.8V ⎛ 1.8V ⎞ • ⎜1− = 2.57μH 1MHz • 400mA ⎝ 4.2V ⎟⎠ Choosing the closest inductor from a vendor of 2.2μH, results in a maximum ripple current of: ΔIL = 1.8V ⎛ 1.8V ⎞ • ⎜1− = 468mA 1MHz • 2.2μH ⎝ 4.2V ⎟⎠ For cost reasons, a ceramic capacitor will be used. COUT selection is then based on load step droop instead of ESR requirements. For a 5% output droop: COUT ≈ 2.5 1A ≅ 27μF 1MHz • (5% • 1.8V) TJ = 0.17 • 43 + 70 = 77.31°C 3561af 16 LTC3561A APPLICATIONS INFORMATION The closest standard value is 22μF. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10μF. In noisy environments, decoupling SVIN from PVIN with an R6/C8 filter of 1Ω/0.1μF may help, but is typically not needed. 1. Does the capacitor CIN connect to the power VIN (Pin 5) and power GND (Pin 4) as close as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are the COUT and L1 closely connected? The (–) plate of COUT returns current to PGND and the (–) plate of CIN. For the feedback resistors, choose R1 = 200k, R2 can be calculated from: 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near SGND (Exposed Pad). The feedback signal VFB should be routed away from noisy components and traces, such as the SW line (Pin 3), and its trace should be minimized. ⎛V ⎞ ⎛ 1.8 V ⎞ – 1 • 200k = 250k R2 = ⎜ OUT – 1⎟ • R1 = ⎜ ⎝ 0.8 V ⎟⎠ ⎝ 0.8 ⎠ Choose a standard value of 249k for R2. The compensation should be optimized for these components by examining the load step response but a good place to start for the LTC3561A is with a 16.9kΩ and 680pF filter. The output capacitor may need to be increased depending on the actual undershoot during a load step. 4. Keep sensitive components away from the SW pin. The input capacitor CIN, the compensation capacitor CC and CITH and all the resistors R1, R2, RT, and RC should be routed away from the SW trace and the inductor L1. The SW pin pad should be kept as small as possible. Board Layout Considerations 5. A ground plane is preferred, but if not available, route all small-signal components back to the SGND pin (Exposed Pad). All SGND and PGND pins must be connected together through a thick copper trace or ground plane. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3561A. These items are also illustrated graphically in the layout diagram of Figure 6. Check the following in your layout: 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to the Exposed Pad for best results. CIN VIN PVIN PGND COUT L1 SVIN SW LTC3561A VFB SGND ITH R2 C4 R1 SHDN/RT RC CC VOUT RT CITH 3561A F06 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 6. LTC3561A Layout Diagram (See Board Layout Checklist) 3561af 17 LTC3561A TYPICAL APPLICATION General Purpose Buck Regulator Using Ceramic Capacitors VIN 2.5V TO 5.5V C1 22μF PVIN SVIN PGND L1 2.2μH LTC3561A VOUT 1.2V/1.5V/1.8V AT 1A SW R2 249k VFB ITH SHDN/RT 1.8V SGND 1.5V 1.2V PGND C2 22μF C4 22pF R3 16.9k C3 680pF R4 549k R1A 200k R1B 287k R1C 499k 3561A TA02a SGND GND SGND PGND NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE C1, C2: TAIYO YUDEN JMK325BJ226MM L1: TOKO A914BYW-2R2M (D52LC SERIES) Efficiency vs Output Current 100 VOUT = 1.2V 90 80 EFFICIENCY (%) 70 60 50 40 30 20 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 1 10 100 1000 OUTPUT CURRENT (mA) 10000 3561A TA02b VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV 40μs/DIV VIN = 3.6V VOUT = 1.2V ILOAD = 20mA TO 1A 3561A TA02c VIN = 3.6V 40μs/DIV VOUT = 1.2V ILOAD = 200mA TO 1A 3561A TA02d 3561af 18 LTC3561A PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.115 TYP 5 0.38 ± 0.10 8 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD) DFN 1203 0.200 REF 0.75 ±0.05 4 0.25 ± 0.05 1 0.50 BSC 0.00 – 0.05 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 3561af Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3561A TYPICAL APPLICATIONS 1mm Height, 2MHz, Li-Ion to 1.8V Converter VIN 2.5V TO 4.2V L1 0.9μH PVIN C1 10μF SVIN SW C4 22pF LTC3561A ITH R3 16.9k SGND PGND C3 470pF C2 10μF s2 VOUT 1.8V AT 1A VFB SHDN/RT R4 178k R2 R1 200k 249k 3561A TA04a C1, C2: TAIYO YUDEN JMK107BJ106MA L1: FDK MIPW3226DORGM Efficiency vs Output Current 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 1 10 100 1000 OUTPUT CURRENT (mA) 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 30mA TO 1A 3561A TA04c 40μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 200mA TO 1A 3561A TA04d 10000 3561A TA04b RELATED PARTS PART NUMBER LTC3406/LTC3406B DESCRIPTION 600mA (IOUT), 1.5MHz Synchronous Step-Down DC/DC Converters COMMENTS 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD < 1μA, ThinSOT™ LTC3407/LTC3407B LTC3410/LTC3410B Dual 600mA/800mA (IOUT), 1.5MHz/2.25MHz Synchronous Step-Down DC/DC Converters 300mA (IOUT), 2.25MHz Synchronous Step-Down DC/DC Converters LTC3411A 1.25A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter LTC3412A 2.5A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter LTC3531/LTC3531-3 LTC3531-3.3 LTC3532 200mA (IOUT), 1.5MHz Synchronous Buck-Boost DC/DC Converters LTC3542 500mA (IOUT), 2.25MHz Synchronous Step-Down DC/DC Converter LTC3544 LTC3547/LTC3547B Quad 300mA + 2× 200mA + 100mA, 2.25MHz Synchronous Step-Down DC/DC Converter Dual 300mA, 2.25MHz Synchronous Step-Down DC/DC Converters LTC3548/LTC3548-1 LTC3548-2 LTC3560 Dual 400mA/800mA, (IOUT), 2.25MHz Synchronous Step-Down DC/DC Converters 800mA (IOUT), 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD < 1μA, MS10E, DFN 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26μA, ISD < 1μA, SC70 96% Efficiency, VIN: 2.6V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD < 1μA, MS10, 3mm × 3mm DFN 96% Efficiency, VIN: 2.6V to 5.5V, VOUT(MIN) = 0.8V, IQ = 62μA, ISD < 1μA, TSSOP16E, 4mm × 4mm QFN 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN) = 2V to 5V, IQ = 16μA, ISD < 1μA, ThinSOT, DFN 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN) = 2.4V to 5.25V, IQ = 35μA, ISD < 1μA, MS10, DFN 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 26μA, ISD < 1μA, 2mm × 2mm DFN 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 70μA, ISD < 1μA, 3mm × 3mm QFN 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD < 1μA, 2mm × 3mm DFN 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD < 1μA, MS10E, DFN 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 16μA, ISD < 1μA, ThinSOT 500mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter ThinSOT is a trademark of Linear Technology Corporation. 3561af 20 Linear Technology Corporation LT 0708 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008