STMicroelectronics M95320-RDW3G/PC 32 kbit serial spi bus eeproms with high-speed clock Datasheet

M95320
M95320-W M95320-R
32 Kbit serial SPI bus EEPROMs
with high-speed clock
Features
■
Compatible with SPI bus serial interface
(positive clock SPI modes)
■
Single supply voltage:
– 4.5 to 5.5 V for M95320
– 2.5 to 5.5 V for M95320-W
– 1.8 to 5.5 V for M95320-R
SO8 (MN)
150 mil width
■
10 MHz, 5 MHz or 2 MHz clock rates
■
5 ms write time
■
Status Register
■
Hardware protection of the Status Register
■
Byte and Page Write (up to 32 bytes)
■
Self-timed programming cycle
■
Adjustable size read-only EEPROM area
■
Enhanced ESD protection
■
More than 1 million Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK2® (RoHS-compliant and
Halogen-free)
December 2009
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2 x 3 mm
Doc ID 5711 Rev 12
1/44
www.st.com
1
Contents
M95320, M95320-W, M95320-R
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
4.2
4.1.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
2/44
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Contents
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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List of tables
M95320, M95320-W, M95320-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
4/44
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating conditions (M95320) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95320-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95320-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M95320, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95320-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95320-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC characteristics (M95320, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics (M95320-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (M95320-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M95320-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 36
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 37
UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Available M95320x products (package, voltage range, temperature grade) . . . . . . . . . . . 40
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 36
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 37
UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 5711 Rev 12
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Description
1
M95320, M95320-W, M95320-R
Description
The M95320, M95320-W and M95320-R are electrically erasable programmable memory
(EEPROM) devices. They are accessed by a high-speed SPI-compatible bus. The devices
are 32 Kbit devices organized as 4096 × 8 bits.
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 1.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
Figure 1.
Logic diagram
VCC
D
Q
C
S
M95xxx
W
HOLD
VSS
AI01789C
Figure 2.
8-pin package connections
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01790D
1. See Package mechanical data section for package dimensions and how to identify pin-1.
6/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Table 1.
Description
Signal names
Signal name
Description
C
Serial Clock
D
Serial data input
Q
Serial data output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply voltage
VSS
Ground
Doc ID 5711 Rev 12
7/44
Signal description
2
M95320, M95320-W, M95320-R
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Table 13 to Table 16). These signals are described next.
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
8/44
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M95320, M95320-W, M95320-R
2.6
Signal description
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write operations.
2.7
VSS ground
VSS is the reference for the VCC supply voltage.
2.8
VCC supply voltage
Refer to Section 4.1: Supply voltage (VCC) on page 12.
Doc ID 5711 Rev 12
9/44
Connecting to the SPI bus
3
M95320, M95320-W, M95320-R
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the
others being high impedance.
Figure 3.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI bus master
SPI memory
device
R
CS3
CS2
VCC
C Q D
VSS
C Q D
VCC
VSS
SPI memory
device
R
VSS
SPI memory
device
R
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
The pull-up resistor R (represented in Figure 3) ensures that a device is not selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master might enter a state where all inputs/outputs SPI bus
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this will ensure that S and C do not become high at the
same time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.
10/44
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M95320, M95320-W, M95320-R
3.1
Connecting to the SPI bus
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
Doc ID 5711 Rev 12
11/44
Operating features
M95320, M95320-W, M95320-R
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9 and
Table 10). This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
4.1.2
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the internal threshold voltage (this threshold is defined in DC characteristics tables
13, 14, 15 and 16 as VRES).
When VCC passes over the POR threshold, the device is reset and in the following state:
●
in the Standby Power mode
●
deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
●
Status register values:
–
the Write Enable Latch (WEL) bit is reset to 0
–
the Write In Progress (WIP) bit is reset to 0
–
the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode. The device must not be accessed until VCC reaches a valid and stable VCC
voltage within the specified [VCC(min), VCC(max)] range defined in Table 8, Table 9 and
Table 10.
4.1.3
Power-up conditions
When the power supply is turned on, VCC continuously rises from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 3).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edgesensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 8, Table 9 and Table 10 and the rise time must not vary faster than 1 V/µs.
12/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
4.1.4
Operating features
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 8, Table 9 and Table 10), the device must be:
4.2
●
deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
●
in Standby Power mode (there should not be any internal write cycle in progress).
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC, as specified in Table 13 to Table 16.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption
drops to ICC1.
4.2.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
Figure 5.
Hold condition activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
Doc ID 5711 Rev 12
13/44
Operating features
4.3
M95320, M95320-W, M95320-R
Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.4
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
●
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-protected block size
Status Register bits
Array addresses protected
Protected block
14/44
BP1
BP0
32 Kbit devices
0
0
none
none
0
1
Upper quarter
0C00h - 0FFFh
1
0
Upper half
0800h - 0FFFh
1
1
Whole memory
0000h - 0FFFh
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
Y Decoder
5
Memory organization
1 Page
X Decoder
AI01272C
Doc ID 5711 Rev 12
15/44
Instructions
6
M95320, M95320-W, M95320-R
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in <Blue>Table 3.), the device
automatically deselects itself.
Table 3.
Instruction set
Instruction
6.1
Description
Instruction format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
16/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
6.2
Instructions
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
Doc ID 5711 Rev 12
17/44
Instructions
6.3
M95320, M95320-W, M95320-R
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The Status Register format is shown in Table 4 and the status and control bits of the Status
Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
18/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Figure 9.
Instructions
Read Status Register (RDSR) sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB
MSB
AI02031E
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
sending the instruction code followed by the data byte on Serial Data input (D), and driving
the Chip Select (S) signal high. Chip Select (S) must be driven high after the rising edge of
Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not
executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed write cycle that takes tW to complete (as specified in Table 17, Table 18, Table 19,
Table 20). The instruction sequence is shown in Figure 10.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle tW, and is 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
reset at the end of the write cycle tW.
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits and the SRWD bit:
●
The Block protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in Table 2.
●
The SRWD bit (Status register write disable bit), in accordance with the signal read on
the Write protect pin (W), allows the user to set or reset the write protection mode of the
Status Register itself, as shown in Table 5. When in the Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0
bits in the Status Register. Bits b6, b5, b4 are always read as 0.
Doc ID 5711 Rev 12
19/44
Instructions
Table 5.
M95320, M95320-W, M95320-R
Protection modes
W
SRWD
signal
bit
1
0
0
0
1
1
0
1
Memory content
Mode
Write protection of the Status Register
Status Register is Writable (if the WREN
Software
instruction has set the WEL bit)
protected
The values in the BP1 and BP0 bits can be
(SPM)
changed
Protected area(1) Unprotected area(1)
Write Protected
Ready to accept
Write instructions
Hardware Status Register is Hardware write protected
protected The values in the BP1 and BP0 bits cannot Write Protected
(HPM) be changed
Ready to accept
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 5.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
If Write Protect (W) is driven high, it is possible to write to the Status Register provided
that the Write enable latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the Write Enable latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register,
are also hardware-protected against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered:
●
by setting the Status register write disable (SRWD) bit after driving Write Protect (W)
low
●
or by driving Write Protect (W) low after setting the Status register write disable
(SRWD) bit.
The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write
Protect (W) high.
If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can
never be activated, and only the Software-protected mode (SPM), using the Block protect
(BP1, BP0) bits in the Status Register, can be used.
Table 6.
Address range bits(1)
Device
32 Kbit devices
Address bits
A11-A0
1. b15 to b12 are Don’t Care.
20/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Instructions
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
6.5
Read from Memory Array (READ)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
1
0
MSB
Data Out 1
High Impedance
7
Q
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI01793D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Doc ID 5711 Rev 12
21/44
Instructions
6.6
M95320, M95320-W, M95320-R
Write to Memory Array (WRITE)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts from the rising edge of Chip Select (S), and continues for a period tWC (as
specified in Table 18 to Table 20), at the end of which the Write in Progress (WIP) bit is reset
to 0.
If, though, Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
Note:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI01795D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
22/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Instructions
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
AI01796D
1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.
Doc ID 5711 Rev 12
23/44
Power-up and delivery state
M95320, M95320-W, M95320-R
7
Power-up and delivery state
7.1
Power-up state
After Power-up, the device is in the following state:
●
Standby Power mode
●
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
●
not in the Hold condition
●
the Write Enable Latch (WEL) is reset to 0
●
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
register write disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.
24/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
8
Maximum rating
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Absolute maximum ratings
Symbol
TSTG
TA
TLEAD
Parameter
Min.
Max.
Unit
Storage temperature
–65
150
°C
Ambient operating temperature
–40
130
°C
Lead temperature during soldering
See
note (1)
°C
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
6.5
V
IOL
DC output current (Q = 0)
5
mA
IOH
DC output current (Q = 1)
–5
mA
VCC
Supply voltage
–0.50
6.5
V
VESD
Electrostatic discharge voltage (human body
model)(2)
–4000
4000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 , R2 = 500 )
Doc ID 5711 Rev 12
25/44
DC and AC parameters
9
M95320, M95320-W, M95320-R
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (M95320)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
4.5
5.5
V
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (M95320-W)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Min.(1)
Max. (1)
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Operating conditions (M95320-R)
Symbol
VCC
TA
Parameter
1. This product is under development. For more information, please contact your nearest ST sales office.
Table 11.
AC measurement conditions(1)
Symbol
CL
Parameter
Load capacitance
Typ.
Max.
30
Input rise and fall times
Unit
pF
50
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
26/44
Min.
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
DC and AC parameters
Figure 14. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 12.
Symbol
COUT
CIN
Capacitance(1)
Parameter
Test condition
Max.
Unit
VOUT = 0 V
8
pF
Input capacitance (D)
VIN = 0 V
8
pF
Input capacitance (other pins)
VIN = 0 V
6
pF
Output capacitance (Q)
Min.
1. Sampled only, not 100% tested.
Table 13.
Symbol
DC characteristics (M95320, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5V, Q = open
4
mA
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 5V, Q = open
8
mA
S = VCC, VCC = 5 V,
VIN = VSS or VCC
5
µA
ICC
Supply current
ICC1
Supply current
(Standby)
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL(1)
Output low voltage
IOL = 2 mA, VCC = 5 V
0.4
V
Output high voltage
IOH = –2 mA, VCC = 5 V
VOH
(1)
VRES(2)
Internal reset threshold
voltage
0.8 VCC
2.5
V
4.0
V
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Characterized only, not 100% tested.
Doc ID 5711 Rev 12
27/44
DC and AC parameters
Table 14.
Symbol
M95320, M95320-W, M95320-R
DC characteristics (M95320-W, device grade 6)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
3
mA
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 3.0 V, Q = open
4
mA
S = VCC, VCC = 2.5 V
VIN = VSS or VCC
1
µA
S = VCC, VCC = 5.0 V
VIN = VSS or VCC
2
µA
ICC
ICC1
Supply current
Supply current
(Standby)
VIL
Input low voltage
–0.45
0.3VCC
V
VIH
Input high voltage
0.7VCC
VCC+1
V
VOL
Output low voltage
IOL = 1.5 mA, VCC = 2.5 V or
IOL = 2 mA, VCC = 5.5 V
0.4
V
VOH
Output high voltage
IOH = –0.4 mA, VCC = 2.5 V or
IOH = –2 mA, VCC = 5.5 V
VRES(1)
Internal reset threshold
voltage
V
0.8VCC
1.0
1.65
V
1. Characterized only, not 100% tested.
Table 15.
Symbol
DC characteristics (M95320-W, device grade 3)
Parameter
Test condition
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
3
mA
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 2.5 V, Q = open
6
mA
2
µA
0.3VCC
V
0.7VCC VCC+1
V
ICC
Supply current
ICC1
Supply current (Standby) S = VCC, VCC = 2.5 V, VIN = VSS or VCC
VIL
Input low voltage
VIH
Input high voltage
VOL
Output low voltage
IOL = 1.5 mA, VCC = 2.5 V
VOH
Output high voltage
IOH = –0.4 mA, VCC = 2.5 V
VRES(1)
–0.45
Internal reset threshold
voltage
1. Characterized only, not 100% tested.
28/44
Min.
Doc ID 5711 Rev 12
0.4
0.8VCC
1.0
V
V
1.65
V
M95320, M95320-W, M95320-R
Table 16.
Symbol
DC and AC parameters
DC characteristics (M95320-R)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, voltage applied on Q =
VSS or VCC
±2
µA
VCC = 2.5 V, C = 0.1VCC/0.9VCC
at maximum clock frequency,
Q = open
3
mA
VCC = 1.8 V, C = 0.1VCC/0.9VCC
at maximum clock frequency,
Q = open
2
mA
VCC = 5 V, S = VCC,
VIN = VSS or VCC
2
µA
VCC = 2.5 V, S = VCC,
VIN = VSS or VCC
1
µA
VCC = 1.8 V, S = VCC,
VIN = VSS or VCC
1
µA
ICCR
ICC1
Supply current (Read)
Supply current (Standby)
VIL
Input low voltage
VIH
Input high voltage
VOL
Output low voltage
1.8 V < VCC < 2.5 V
–0.45
0.25VCC
V
2.5 V < VCC < 5.5 V
–0.45
0.3VCC
V
1.8 V < VCC < 2.5 V
0.75VCC
VCC+1
V
2.5 V < VCC < 5.5 V
0.7 VCC
VCC+1
V
0.2VCC
V
0.3
V
VCC = 2.5 V, IOL = 1.5 mA or
VCC = 5.5 V, IOL = 2 mA
VCC = 1.8 V, IOL = 0.15 mA
VOH
VRES(1)
VCC = 2.5 V, IOH = –0.4 mA or
VCC = 5.5 V, IOH = –2 mA or
VCC = 1.8 V, IOH = –0.1 mA
Output high voltage
Internal reset threshold
voltage
0.8 VCC
1.0
V
1.65
V
1. Characterized only, not 100% tested.
Doc ID 5711 Rev 12
29/44
DC and AC parameters
Table 17.
M95320, M95320-W, M95320-R
AC characteristics (M95320, device grade 3)
Test conditions specified in Table 10 and Table 11
Max.
Min.(1)
Max.(1)
Unit
D.C.
5
D.C.
10
MHz
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
30
ns
tSHCH
tCSS2
S not active setup time
90
30
ns
tSHSL
tCS
S deselect time
100
40
ns
tCHSH
tCSH
S active hold time
90
30
ns
S not active hold time
90
30
ns
tCHSL
Parameter
Min.
Symbol
tCH(2)
tCLH
Clock high time
90
42
ns
tCL(2)
90
40
ns
tCLL
Clock low time
tCLCH
(3)
tRC
Clock rise time
1
2
µs
tCHCL
(3)
tFC
Clock fall time
1
2
µs
tDVCH
tDSU
Data in setup time
20
10
ns
tCHDX
tDH
Data in hold time
30
10
ns
tHHCH
Clock low hold time after HOLD not active
70
30
ns
tHLCH
Clock low hold time after HOLD active
40
30
ns
tCLHL
Clock low set-up time before HOLD active
0
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
0
ns
tSHQZ(3)
tDIS
tCLQV(4)
tV
tCLQX
Output disable time
100
40
ns
Clock low to output valid
60
40
ns
tHO
Output hold time
(3)
tRO
Output rise time
50
40
ns
tQHQL(3)
tFO
Output fall time
50
40
ns
tHHQV
tLZ
HOLD high to output valid
50
40
ns
tHZ
HOLD low to output high-Z
100
40
ns
tWC
Write time
5
5
ms
tQLQH
tHLQZ
tW
(3)
0
0
ns
1. These timings are offered with grade3 devices referenced with “/PC” process letters only (see the last digits in the Part
numbering).
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Value guaranteed by characterization, not 100% tested in production.
4. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
30/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Table 18.
DC and AC parameters
AC characteristics (M95320-W, device grade 6)
Test conditions specified in Table 9 and Table 11
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
30
ns
tSHCH
tCSS2
S not active setup time
30
ns
tSHSL
tCS
S deselect time
40
ns
tCHSH
tCSH
S active hold time
30
ns
S not active hold time
30
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
10
MHz
tCH(1)
tCLH
Clock high time
42
ns
tCL(1)
40
ns
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
2
µs
tCHCL
(2)
tFC
Clock fall time
2
µs
tDVCH
tDSU
Data in setup time
10
ns
tCHDX
tDH
Data in hold time
10
ns
tHHCH
Clock low hold time after HOLD not active
30
ns
tHLCH
Clock low hold time after HOLD active
30
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tSHQZ(2)
tDIS
tCLQV(3)
tV
tCLQX
Output disable time
40
ns
Clock low to output valid
40
ns
tHO
Output hold time
(2)
tRO
Output rise time
40
ns
tQHQL(2)
tFO
Output fall time
40
ns
tHHQV
tLZ
HOLD high to output valid
40
ns
tHZ
HOLD low to output high-Z
40
ns
tWC
Write time
5
ms
tQLQH
tHLQZ
tW
(2)
0
ns
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0
ns, tCL can be equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than)
tCLQV+tSU.
Doc ID 5711 Rev 12
31/44
DC and AC parameters
Table 19.
M95320, M95320-W, M95320-R
AC characteristics (M95320-W, device grade 3)
Test conditions specified in Table 9 and Table 11
2.5 V to 5.5 V
Symbol
fC
Alt.
fSCK
3.0 V to 5.5 V(1)
Parameter
Clock frequency
Unit
Min.
Max.
Min.
Max.
D.C.
5
D.C.
10
MHz
tSLCH
tCSS1 S active setup time
90
30
ns
tSHCH
tCSS2 S not active setup time
90
30
ns
tSHSL
tCS
S deselect time
100
40
ns
tCHSH
tCSH
S active hold time
90
30
ns
S not active hold time
90
30
ns
tCHSL
(2)
tCLH
Clock high time
90
42
ns
tCL(2)
tCLL
Clock low time
90
40
ns
tCLCH(3)
tRC
Clock rise time
1
2
µs
tCHCL(3)
tFC
Clock fall time
1
2
µs
tDVCH
tDSU
Data in setup time
20
10
ns
tCHDX
tDH
Data in hold time
30
10
ns
tHHCH
Clock low hold time after HOLD not active
70
30
ns
tHLCH
Clock low hold time after HOLD active
40
30
ns
tCLHL
Clock low set-up time before HOLD active
0
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
0
ns
tCH
tSHQZ
(3)
tDIS
Output disable time
100
40
ns
Clock low to output valid
60
40
ns
tCLQV(4)
tV
tCLQX
tHO
Output hold time
tQLQH(3)
tRO
Output rise time
50
40
ns
tQHQL(3)
tFO
Output fall time
50
40
ns
tHHQV
tLZ
HOLD high to output valid
50
40
ns
tHLQZ(3)
tHZ
HOLD low to output high-Z
100
40
ns
tW
tWC
Write time
5
5
ms
0
0
ns
1. These timings are offered with grade3 devices referenced with “/PC” process letters only (see the last digits in the Part
numbering).
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Value guaranteed by characterization, not 100% tested in production.
4. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
32/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Table 20.
DC and AC parameters
AC characteristics (M95320-R)
Test conditions specified in Table 10 and Table 11 (1)
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
60
ns
tSHCH
tCSS2
S not active setup time
60
ns
tSHSL
tCS
S deselect time
90
ns
tCHSH
tCSH
S active hold time
60
ns
S not active hold time
60
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
5
MHz
tCH(2)
tCLH
Clock high time
90
ns
tCL(2)
90
ns
tCLL
Clock low time
tCLCH
(3)
tRC
Clock rise time
2
µs
tCHCL
(3)
tFC
Clock fall time
2
µs
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
20
ns
tHHCH
Clock low hold time after HOLD not active
60
ns
tHLCH
Clock low hold time after HOLD active
60
ns
tCLHL
Clock low set-up time before HOLD active
0
0
tCLHH
Clock low set-up time before HOLD not active
0
0
tSHQZ(3)
tDIS
tCLQV
tV
tCLQX
Output disable time
80
ns
Clock low to output valid
80
ns
tHO
Output hold time
tQLQH
(3)
0
ns
tRO
Output rise time
80
ns
tQHQL
(3)
tFO
Output fall time
80
ns
tHHQV
tLZ
HOLD high to output valid
80
ns
tHLQZ(3)
tHZ
HOLD low to output high-Z
80
ns
tW
tWC
Write time
5
ms
1. If the application uses the M95320-R device with 2.5 V  VCC  5.5 V and –40 °C  TA  +85 °C, please
refer to Table 18: AC characteristics (M95320-W, device grade 6) instead of the above table.
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Value guaranteed by characterization, not 100% tested in production.
Doc ID 5711 Rev 12
33/44
DC and AC parameters
M95320, M95320-W, M95320-R
Figure 15. Serial input timing
tSHSL
S
tCHSL
tCH
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCL
tCLCH
tCHDX
D
Q
LSB IN
MSB IN
High impedance
AI01447d
Figure 16. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQV
Q
HOLD
AI01448c
34/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
DC and AC parameters
Figure 17. Serial output timing
S
tCH
tSHSL
C
tCLQV
tCLCH
tCHCL
tCL
tSHQZ
tCLQX
Q
tQLQH
tQHQL
ADDR
D LSB IN
AI01449f
Doc ID 5711 Rev 12
35/44
Package mechanical data
10
M95320, M95320-W, M95320-R
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 21.
SO8N – 8-lead plastic small outline, 150 mils body width, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
1.75
Max
0.0689
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.10
0.0039
D
4.90
4.80
5.00
0.1929
0.189
0.1969
E
6.00
5.80
6.20
0.2362
0.2283
0.2441
E1
3.90
3.80
4.00
0.1535
0.1496
0.1575
e
1.27
–
–
0.05
-
-
h
0.25
0.50
0.0098
0.0197
k
0°
8°
0°
8°
L
0.40
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
36/44
Min
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Package mechanical data
Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 22.
TSSOP8 – 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
A
Max.
Min.
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°

0.0394
0°
8°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 5711 Rev 12
37/44
Package mechanical data
M95320, M95320-W, M95320-R
Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 23.
UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.55
0.45
0.6
0.0217
0.0177
0.0236
A1
0.02
0
0.05
0.0008
0
0.002
b
0.25
0.2
0.3
0.0098
0.0079
0.0118
D
2
1.9
2.1
0.0787
0.0748
0.0827
D2
1.6
1.5
1.7
0.063
0.0591
0.0669
E
3
2.9
3.1
0.1181
0.1142
0.122
E2
0.2
0.1
0.3
0.0079
0.0039
0.0118
e
0.5
-
-
0.0197
-
-
L
0.45
0.4
0.5
0.0177
0.0157
0.0197
L1
L3
(2)
ddd
0.15
0.0059
0.3
0.0118
0.08
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measurement.
38/44
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
11
Part numbering
Part numbering
Table 24.
Ordering information scheme
Example:
M95320
–
W MN 6
T
P
/P
Device type
M95 = SPI serial access EEPROM
Device function
320 = 32 Kbit (4096 × 8)
Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package(1)
MN = SO8 (150 mils width)
DW = TSSOP8 (169 mils width)
MB = MLP8 (2 × 3 mm)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with high reliability certified flow(2)automotive temperature range
(–40 to 125 °C)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK (RoHS compliant)
Process letter(3)
/P or /PC = DP26% Chartered
1. All packages are ECOPACK2® (RoHS compliant and Halogen-free).
2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
3. The process letter only concerns Grade-3 devices.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 5711 Rev 12
39/44
Part numbering
M95320, M95320-W, M95320-R
Table 25.
Available M95320x products (package, voltage range, temperature grade)
M95320-R
1.8 V to 5.5 V
Range 3
Range 6
Range 3
Range 6
TSSOP (DW)
-
Range 6
Range 3
Range 6
MLP 2 × 3 mm (MB)
-
-
Range 6
SO8 (MN)
40/44
M95320
M95320-W
2.5 V to 5.5 V
Package
4.5 V to 5.5 V
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
12
Revision history
Revision history
Table 26.
Document revision history
Date
Revision
Changes
13-Jul-2000
1.2
Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp
1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2,
Ordering Info, Mechanical Data
16-Mar-2001
1.3
Test condition added ILI and ILO, and specification of tDLDH and tDHDL
removed.
tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range.
“-V” Voltage range changed to “2.7V to 3.6V” throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
“Bus Master and Memory Devices on the SPI bus” illustration updated.
Package Mechanical data updated
19-Jul-2001
1.4
M95160 and M95080 devices removed to their own data sheet
06-Dec-2001
1.5
Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
18-Dec-2001
2.0
Document reformatted using the new template. No parameters changed.
08-Feb-2002
2.1
Announcement made of planned upgrade to 10MHz clock for the 5V, –40
to 85°C, range.
Endurance set to 100K write/erase cycles
18-Dec-2002
2.2
10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write
cycles distinguished on front page, and in the DC and AC Characteristics
tables
26-Mar-2003
2.3
Process identification letter corrected in footnote to AC Characteristics
table for temp. range 3
26-Jun-2003
2.4
-S voltage range upgraded by removing it and inserting -R voltage range
in its place
15-Oct-2003
3.0
Table of contents, and Pb-free options added. VIL(min) improved to -0.45V
21-Nov-2003
3.1
VI(min) and VO(min) corrected (improved) to -0.45V
28-Jan-2004
4.0
TSSOP8 connections added to DIP and SO connections
5.0
M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and
related characteristics added.
20MHz Clock rate added.TSSOP14 package removed and MLP8 package
added.
Description of Power On Reset: VCC Lock-Out Write Protect updated.
Product List summary table added. Absolute Maximum Ratings for
VIO(min) and VCC(min) improved. Soldering temperature information
clarified for RoHS compliant devices. Device Grade 3 clarified, with
reference to HRCF and automotive environments. AEC-Q100-002
compliance. tCHHL(min) and tCHHH(min) is tCH for products under “S”
process. tHHQX corrected to tHHQV.
Figure 16: Hold timing updated.
24-May-2005
Doc ID 5711 Rev 12
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Revision history
Table 26.
Date
07-Jul-2006
09-Oct-2007
17-Dec-2007
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M95320, M95320-W, M95320-R
Document revision history (continued)
Revision
Changes
6
Document converted to new ST template.
Packages are ECOPACK® compliant. PDIP package removed.
SO8N package specifications updated (see Table 21 and Figure 18).
M95640-S and M95320-S part numbers removed (DC and AC parameters
updated accordingly).
How to identify previous, current and new products by the Process
identification letter Table removed.
Figure 4: SPI modes supported updated and Note 2 added. First three
paragraphs of Section 4: Operating features replaced by Section 4.1:
Supply voltage (VCC).
TA added to Table 7: Absolute maximum ratings. ICC and ICC1 updated in
Table 13, Table 13, Table 14 and Table 16. VOL and VOH updated in
Table 14. ICC updated in Table 15. Data in Table 16 is no longer
preliminary.
tCH updated in Table 18. Table 21: AC characteristics (M95640-R) added.
Timing line of tSHQZ modified in Figure 17: Serial output timing.
Process letter added to Table 24: Ordering information scheme, Note 2
removed. Note 2 removed from Figure 2.
7
JEDEC standard revision updated to D in Note 1 below Table 7: Absolute
maximum ratings.
Note 2 removed below Figure 3 and explanatory paragraph added.
Section 4.1: Supply voltage (VCC) updated. Table 6: Address range bits
corrected.
Products operating at VCC = 4.5 V to 5.5 V are no longer available in the
device grade 6 TA temperature range.
ICC and ICC1 parameters modified in Table 14: DC characteristics
(M95320-W, device grade 6).
Maximum frequency for M95320-W and M95640-W upgraded from 5 MHz
to 10 MHz in the device grade 6 TA temperature range (Table 18: AC
characteristics (M95320-W, device grade 6) modified accordingly).
Table 27: Available M95640x products (package, voltage range,
temperature grade): /PB process letter added, /P process letter removed.
Blank option removed below Plating technology in Table 24: Ordering
information scheme.
Table 25 and Table 27 added. Small text changes.
Table 23: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead,
package mechanical data updated.
Package mechanical inch values calculated from mm and rounded to 4
decimal digits in Section 10: Package mechanical data.
8
Section 2.7: VSS ground added.
Device behavior when VCC passes over the POR threshold updated (see
Section 4.1.2: Device reset and Section 4.1.4: Power-down).
VIL and VIH modified in Table 16: DC characteristics (M95320-R).
tW, write time, modified in Table 20: AC characteristics (M95320-R) and
Table 21: AC characteristics (M95640-R). Small text changes.
Doc ID 5711 Rev 12
M95320, M95320-W, M95320-R
Table 26.
Date
20-Mar-2008
23-Jun-2008
17-Feb-2009
07-Dec-2009
Revision history
Document revision history (continued)
Revision
Changes
9
Section 4.1: Supply voltage (VCC) updated.
10 MHz frequencies added to Table 17: AC characteristics (M95320,
device grade 3) and Table 19: AC characteristics (M95320-W, device
grade 3).
Small text changes.
10
Section 4.1: Supply voltage (VCC) updated.
Table 16: DC characteristics (M95320-R) modified.
Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial
output timing modified.
11
Section 4.1: Supply voltage (VCC) and Section 6.4: Write Status Register
(WRSR) updated.
Note added to Section 6.6: Write to Memory Array (WRITE).
Section 7.2: Initial delivery state specified.
Note modified in Table 12: Capacitance. ICC at 10 MHz added to Table 13:
DC characteristics (M95320, device grade 3).
VRES parameter added to DC characteristics tables 13, 14, 15 and 16.
Note added to tCLQV in AC characteristics tables 17, 18, 19 and 21.
Note added to Table 20: AC characteristics (M95320-R) and Table 21: AC
characteristics (M95640-R).
Process letter modified in Table 24: Ordering information scheme.
12
64 Kbit densities removed from datasheet.
ECOPACK status of packages specified in Features and in Table 24:
Ordering information scheme.
IOL and IOH added to Table 7: Absolute maximum ratings.
Note 2 added below Figure 20: UFDFPN8 (MLP8) - 8-lead ultra thin fine
pitch dual flat no lead, package outline.
Small text changes.
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M95320, M95320-W, M95320-R
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