AD AD7981HFZ High temperature, 16-bit, 600 ksps pulsar adc Datasheet

High Temperature, 16-Bit,
600 kSPS PulSAR ADC
AD7981
Data Sheet
TYPICAL APPLICATION CIRCUIT
Extreme high temperature operation
Specified temperature range
−55°C to +210°C (10-lead FLATPACK)
−55°C to +175°C (10-Lead MSOP)
High performance
16-bit resolution with no missing codes
600 kSPS throughput with no latency/pipeline delay
SNR: 91 dB typical at 1 kHz input frequency
THD: −102 dB typical at 1 kHz input frequency
INL: ±2.5 LSB maximum, DNL: ±0.9 LSB maximum
Low power
2.25 mW typical at 600 kSPS (VDD only)
4.65 mW typical at 600 kSPS (total)
75 µW typical at 10 kSPS
Small footprint
10-lead, 3 mm × 3 mm, monometallic wire bonding MSOP
10-lead, 0.255 mm × 0.255 mm, monometallic wire
bonding FLATPACK
Pseudo differential analog input range
0 V to VREF with VREF between 2.4 V and 5.1 V
Single-supply 2.5 V operation with 1.8 V to 5 V logic interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible digital interface
Daisy-chain multiple ADCs and busy indicator
2.5V to 5.0V
0V TO VREF
IN+
IN–
2.5V
REF VDD VIO
SDI
AD7981
SCK
SDO
GND
1.8V TO 5.0V
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
CNV
12479-001
FEATURES
Figure 1.
APPLICATIONS
Downhole drilling and instrumentation
Avionics
Heavy industrial
High temperature environments
GENERAL DESCRIPTION
The AD7981 is a 16-bit, successive approximation, PulSAR®
analog-to-digital converter (ADC) designed for high temperature
operation. The AD7981 is capable of sample rates of up to 600 kSPS
while maintaining low power consumption from a single power
supply, VDD. It is a fast throughput, high accuracy, high temperature, successive approximation register (SAR) ADC, packaged in a
small form factor with a versatile serial port interface (SPI).
1
On the CNV rising edge, the AD7981 samples an analog input,
IN+, between 0 V and REF with respect to a ground sense, IN−.
The reference voltage, REF, is applied externally and can be set
independent of the supply voltage, VDD. The device power
scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
1
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply, VIO.
For space constrained applications, the AD7981 is available in a
10-lead mini small outline package (MSOP) with operation specified from −55°C to +175°C and 10-lead ceramic flat package
(FLATPACK) with operation specified from −55°C to +210°C.
These packages are designed for robustness at extreme temperatures, including monometallic wire bonding, and are qualified
for up to 1000 hours of operation at the maximum temperature
rating.
The AD7981 is a member of a growing series of high temperature
qualified products offered by Analog Devices, Inc. For a complete
selection of available high temperature products, see the high
temperature product list and qualification data available at
www.analog.com/hightemp.
Protected by U.S. Patent 6,703,961.
Rev. B
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AD7981
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input ............................................................................... 16
Applications ....................................................................................... 1
Driver Amplifier Choice ........................................................... 16
Typical Application Circuit ............................................................. 1
Voltage Reference Input ............................................................ 17
General Description ......................................................................... 1
Power Supply............................................................................... 17
Revision History ............................................................................... 2
Digital Interface .......................................................................... 17
Specifications..................................................................................... 3
CS Mode, 3-Wire Without a Busy Indicator........................... 18
Timing Specifications .................................................................. 5
CS Mode, 3-Wire with a Busy Indicator ................................. 19
Absolute Maximum Ratings ............................................................ 6
CS Mode, 4-Wire Without a Busy Indicator........................... 20
ESD Caution .................................................................................. 6
CS Mode, 4-Wire with a Busy Indicator ................................. 21
Pin Configuration and Function Descriptions ............................. 7
Chain Mode Without a Busy Indicator ................................... 22
Typical Performance Characteristics ............................................. 8
Chain Mode with a Busy Indicator .......................................... 23
Terminology .................................................................................... 13
Applications Information .............................................................. 24
Theory of Operation ...................................................................... 14
Printed Circuit Board (PCB) Layout ....................................... 25
Circuit Information .................................................................... 14
Outline Dimensions ....................................................................... 26
Converter Operation .................................................................. 14
Ordering Guide .......................................................................... 26
Typical Connection Diagram.................................................... 15
REVISION HISTORY
7/2017—Rev. A to Rev. B
Change to Conversion Time: CNV Rising Edge to Data Available
Parameter; Table 3 .............................................................................. 5
10/2016—Rev. 0 to Rev. A
Added 10-Lead FLATPACK.............................................. Universal
Changes to Features Section and General Description Section . 1
Changes to Integral Nonlinearity (INL) Parameter, Table 1....... 3
Changes to Power Dissipation Parameter and Temperature
Range, Specified Performance Parameter, Table 2 ....................... 4
Changes to Table 4 ............................................................................ 6
Added Figure 5; Renumbered Sequentially .................................. 7
Changes to Figure 6, Figure 7, and Figure 8 ................................. 8
Added Figure 9, Figure 10, and Figure 11 ..................................... 8
Changes to Figure 12.........................................................................9
Added Figure 15 ................................................................................9
Changes to Figure 18 and Figure 21 ............................................ 10
Added Figure 22 and Figure 23 .................................................... 10
Change to Figure 26 ....................................................................... 11
Added Figure 27, Figure 28, Figure 29 ........................................ 11
Added Figure 33 and Figure 34 .................................................... 12
Change to Figure 35 Caption ....................................................... 12
Changes to Circuit Information Section ..................................... 14
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
10/2014—Revision 0: Initial Version
Rev. B | Page 2 of 26
Data Sheet
AD7981
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input Common-Mode Rejection Ratio (CMRR)
Leakage Current at 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
10-Lead MSOP 2
10-Lead FLATPACK2
Transition Noise
Gain Error 3
Gain Error Temperature Drift
Zero Error3
Zero Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY 4
Dynamic Range
Oversampled Dynamic Range 5
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise-and-Distortion (SINAD) Ratio
Test Conditions/Comments
Min
16
IN+ − IN−
IN+
IN−
fIN = 100 kHz
Acquisition phase
0
−0.1
−0.1
VREF = 5 V
VREF = 2.5 V
Typ
Unit
Bits
VREF
VREF + 0.1
+0.1
V
V
V
dB
nA
60
1
See the Analog Input section
16
−0.9
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
TMIN to TMAX
−2.0
TMIN to TMAX
−1
−2.5
VDD = 2.5 V ± 5%
±0.4
±0.5
+0.9
±0.7
±0.6
±0.7
±0.6
0.75
1.2
±2
±0.35
±0.08
0.45
±0.1
+2.0
0
89
+2.5
+1
600
290
Full-scale step
VREF = 5 V
VREF = 2.5 V
OSR = 256
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
Max
92
87
110
91
86
104
−102
90.5
85.5
Bits
LSB 1
LSB1
LSB1
LSB1
LSB1
LSB1
LSB1
LSB1
LSB1
ppm/°C
mV
ppm/°C
LSB1
kSPS
ns
dB
dB
dB
dB
dB
dB
dB
dB
dB
LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
MSOP operation is specified from −55°C to +175°C and FLATPACK operation specified is specified from −55°C to +210°C.
3
See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.
4
All ac accuracy specifications (in dB) are referred to an input full-scale range (FSR). Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5
The oversampled dynamic range is the ratio of the peak signal power to the noise power (for a small input) measured in the ADC output fast Fourier transform (FFT)
from dc up to fS/(2 × OSR), where fS is the ADC sample rate and OSR is the oversampling ratio.
1
2
Rev. B | Page 3 of 26
AD7981
Data Sheet
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
REFERENCE
Voltage Range (VREF)
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
Input Voltage
Low (VIL)
High (VIH)
Test Conditions/Comments
Min
2.4
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance 3
10-Lead FLATPACK
10-Lead MSOP
Max
Unit
5.1
600 kSPS, VREF = 5 V
330
V
µA
VDD = 2.5 V
10
2
MHz
ns
VIO > 3 V
VIO ≤ 3 V
VIO > 3 V
VIO ≤ 3 V
Input Current
Low (IIL)
High (IIH)
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Output Voltage
Low (VOL)
High (VOH)
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 1, 2
Power Dissipation
Total
Typ
–0.3
–0.3
0.7 × VIO
0.9 × VIO
0.3 × VIO
0.1 × VIO
VIO + 0.3
VIO + 0.3
V
V
V
µA
−1
−1
+1
+1
µA
µA
Serial, 16 bits, straight binary
Conversion results available immediately
after completed conversion
ISINK = 500 µA
ISOURCE = −500 µA
0.4
V
V
2.625
5.5
5.5
V
V
V
µA
VIO − 0.3
2.375
2.3
1.8
Specified performance
VDD and VIO = 2.5 V
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
10 kSPS
600 kSPS (MSOP)
600 kSPS (FLATPACK)
600 kSPS
600 kSPS
600 kSPS
2.5
0.35
75
4.65
4.65
2.25
1.5
0.9
7.75
7
12
µW
mW
mW
mW
mW
mW
nJ/sample
TMIN to TMAX
−55
−55
With all digital inputs forced to VIO or GND as required.
During the acquisition phase.
3
Qualified for up to 1000 hours of operation at the maximum temperature rating.
1
2
Rev. B | Page 4 of 26
+210
+175°C
°C
°C
Data Sheet
AD7981
TIMING SPECIFICATIONS
VDD = 2.375 V to 2.625 V, VIO = 3.3 V to 5.5 V, TMIN to TMAX, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 3.
Parameter
CONVERSION AND ACQUISITION TIMES
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV PULSE WIDTH (CS MODE)
SCK
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CS MODE
CNV or SDI Low to SDO D15 MSB Valid
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge
CHAIN MODE
SDI Valid Hold Time from CNV Rising Edge
SCK Valid Setup Time from CNV Rising Edge
SCK Valid Hold Time from CNV Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
SDI High to SDO High (Chain Mode with Busy Indicator)
Min
tCONV
tACQ
tCYC
tCNVH
800
290
1667
10
tSCKL
tSCKH
tHSDO
tDSDO
1200
ns
ns
ns
ns
10.5
12
13
15
ns
ns
ns
ns
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
9.5
11
12
14
ns
ns
ns
ns
10
15
20
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
5
2
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
0
5
5
2
3
15
ns
ns
ns
ns
ns
ns
Y% VIO1
X% VIO1
tDELAY
VIH2
VIL2
1.4V
12479-002
CL
20pF
IOH
Unit
tSCK
tDELAY
500µA
Max
tSCK
IOL
TO SDO
Typ
VIH2
VIL2
1FOR
VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 2.
2MINIMUM
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
Rev. B | Page 5 of 26
12479-003
500µA
Symbol
AD7981
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Analog Inputs
IN+, IN− to GND1
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature2
10-Lead MSOP
10-Lead FLATPACK
Thermal Impedance
10-Lead MSOP
θJA
θJC
10-Lead FLATPACK
θJA
θJC
Lead Temperature Soldering
ESD Ratings
Human Body Model
Machine Model
Field Induced Charged Device
Model
Rating
−0.3 V to VREF + 0.3 V or ±130 mA
−0.3 V to +6 V
−0.3 V to +3 V
+3 V to −6 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
175.12°C
210.13°C
146.76°C/W
38.12°C/W
107.5°C/W
25.5°C/W
260°C reflow as per
JEDEC J-STD-020
2 kV
200 V
1.25 kV
See the Analog Input section. A transient with a very short duration of 10 ms
applied on the analog inputs, IN+ and IN−, during latch-up testing shows
that these diodes can then handle a forward-biased current of 130 mA
maximum.
2
The maximum junction temperature consists of the maximum specified
ambient temperature plus self heating rise under normal operating
conditions.
1
Rev. B | Page 6 of 26
Data Sheet
AD7981
REF 1
10 VIO
REF 1
10
VIO
VDD 2
9
SDI
VDD 2
9
SDI
8
SCK
IN+ 3
8
SCK
7
SDO
7
SDO
6
CNV
6
CNV
IN– 4
AD7981
TOP VIEW
(Not to Scale)
GND 5
IN– 4
12479-004
IN+ 3
GND 5
Figure 4. 10-Lead MSOP Pin Configuration
AD7981
TOP VIEW
(Not to Scale)
12479-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. 10-Lead FLATPACK Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type1
AI
2
3
VDD
IN+
P
AI
4
5
6
IN−
GND
CNV
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
Description
Reference Input Voltage. The REF range, VREF, is from 2.4 V to 5.1 V. VREF is referred to the GND pin.
Decouple REF with a 10 μF capacitor as close as possible to the pin.
Power Supply.
Analog Input. This pin is referred to IN−. The voltage range, for example, the difference between IN+ and
IN−, is 0 V to VREF.
Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Conversion Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the device: chain or CS mode. In CS mode, it enables the SDO pin when low.
In chain mode, read the data when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input
to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
Input/Output Interface Digital Power. VIO is nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
1
AI is the analog input, P is the power, DI is the digital input, and DO is the digital output.
Rev. B | Page 7 of 26
AD7981
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, TA = 25°C, unless otherwise noted.
0.75
0.4
0.50
0.2
0.25
INL (LSB)
0.6
0
–0.2
–0.25
–0.50
–0.6
–0.75
–0.8
–1.00
6901 13801 20701 27601 34501 41401 48301 55201 62101
–1.25
12479-006
1
CODE
Figure 6. Integral Nonlinearity (INL) vs. Code and Temperature, VREF = 5.0 V,
MSOP
1.0
0.4
0.2
0.2
INL (LSB)
0.4
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
12793 19189 25585 31981 38377 44773 51169 57565 63961
CODE
–1.0
12479-007
6397
0.6
–55°C
+25°C
+210°C
0.4
0.3
0.2
0.2
0.1
DNL (LSB)
DNL (LSB)
7089 14177 21265 28353 35441 42529 49617 56705 63793
Figure 10. Integral Nonlinearity (INL) vs. Code and Temperature, VREF = 2.5 V,
FLATPACK
25°C
175°C
0.4
1
CODE
Figure 7. Integral Nonlinearity (INL) vs. Code and Temperature, VREF = 2.5 V,
MSOP
0.5
–55°C
+25°C
+210°C
0.8
0.6
1
6901 13801 20701 27601 34501 41401 48301 55201 62101
CODE
1.0
0.6
–1.0
1
Figure 9. Integral Nonlinearity (INL) vs. Code and Temperature, VREF = 5.0 V,
FLATPACK
25°C
175°C
0.8
INL (LSB)
0
–0.4
–1.0
–55°C
+25°C
+210°C
1.00
12479-307
0.8
INL (LSB)
1.25
25°C
175°C
12479-309
1.0
0
–0.1
0
–0.2
–0.2
–0.3
–0.4
1
6901 13801 20701 27601 34501 41401 48301 55201 62101
CODE
–0.6
12479-008
–0.5
1
7285 14569 21853 29137 36421 43705 50989 58273
CODE
12479-201
–0.4
Figure 11. Differential Nonlinearity (DNL) vs. Code and Temperature,
VREF = 5.0 V, FLATPACK
Figure 8. Differential Nonlinearity (DNL) vs. Code and Temperature,
VREF = 5.0 V, MSOP
Rev. B | Page 8 of 26
Data Sheet
AD7981
0.6
0.5
0.4
0.4
0.3
0.2
0.1
DNL (LSB)
0
–0.1
–0.2
–0.2
–0.3
–0.4
–0.4
25°C
175°C
1
6557
–0.6
12479-009
–0.5
0
13113 19669 26225 32781 39337 45893 52449 59005
CODE
–55°C
+25°C
+210°C
1
12479-202
DNL (LSB)
0.2
7285 14569 21853 29137 36421 43705 50989 58273
CODE
Figure 15. Differential Nonlinearity (DNL) vs. Code and Temperature,
VREF = 2.5 V, FLATPACK
Figure 12. Differential Nonlinearity (DNL) vs. Code and Temperature,
VREF = 2.5 V, MSOP
95
70k
59691 59404
60k
94
93
92
40k
SNR (dB)
COUNTS
50k
30k
91
90
89
88
20k
87
150
2
0
86
93
0
3
7FFF 8000 8001 8002 8003 8004 8005 8006 8007 8008
CODE IN HEX
85
–10
–9
–8
–7
–6
–5
–4
–3
–2
0
–1
INPUT LEVEL (dB OF FULL SCALE)
Figure 13. Histogram of a DC Input at the Code Transition, VREF = 5.0 V
12479-046
0
6295
5428
12479-043
10k
Figure 16. SNR vs. Input Level
180k
60k
168591
52212
160k
50k
140k
40k
COUNTS
100k
80k
60k
32417
20k
52710
38751
40k
10k
7225
20k
0
0
27
1201
829
33
2
0
0
0
8003 8004 8005 8006 8007 8008 8009 800A 800B 800C 800D 800E 800F
CODE IN HEX
0
12479-042
0
31340
30k
0
0
16
6807
539
502 14
0
0
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
CODE IN HEX
Figure 14. Histogram of a DC Input at the Code Center, VREF = 5.0 V
Figure 17. Histogram of a DC Input at the Code Center, VREF = 2.5 V
Rev. B | Page 9 of 26
12479-059
COUNTS
120k
AD7981
Data Sheet
0
0
VDD = 2.5V
VIO = 3.3V
fIN = 9972.3Hz
fSMPLE = 588.51ksps
SNR = 90.05dB
SINAD = 89.82dB
THD = –102.7dB
–40
–60
–80
–100
–120
–140
–40
–60
–80
–100
–120
–140
–160
250
300
FREQUENCY (kHz)
–180
0
50
92
90
88
SINAD
86
84
82
80
2.00
2.50
3.00
3.50
4.00
4.50
5.00
SFDR
14.0
90
13.5
SINAD
88
13.0
86
12.5
84
12.0
82
11.5
2.5
3.0
3.5
4.0
4.5
5.0
Figure 22. SINAD and ENOB vs. Reference Voltage (VREF), FLATPACK
–120
–116
120
–55°C
+25°C
+210°C
115
SFDR
110
–114
THD (dB)
95
THD
SFDR (dB)
–110
–108
–104
–110
–108
100
THD
95
–106
90
–104
90
–106
105
–112
100
–112
85
–102
85
–100
80
–98
–102
2.5
3.0
3.5
4.0
4.5
5.0
80
5.5
VREF (V)
75
–96
12479-117
–100
2.0
11.0
5.5
VREF (V)
105
–114
THD (dB)
14.5
92
–118
–116
15.0
94
80
2.0
110
–55°C
+25°C
+175°C
15.5
ENOB
VREF (V)
–118
300
16.0
96
Figure 19. SINAD and ENOB vs. Reference Voltage (VREF), MSOP
–120
250
–55°C
+25°C
+210°C
98
SINAD (dB)
SINAD (dB)
94
100
ENOB (dB)
ENOB
16.00
15.75
15.50
15.25
15.00
14.75
14.50
14.25
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
5.50
12479-114
96
200
Figure 21. 10 kHz FFT, VREF = 2.5 V
–55°C
+25°C
+175°C
98
150
FREQUENCY (kHz)
Figure 18. 10 kHz FFT, VREF = 5.0 V
100
100
ENOB (dB)
200
12479-209
150
2.00
2.50
3.00
3.50
4.00
4.50
5.00
70
5.50
VREF (V)
Figure 23. THD and SFDR vs. Reference Voltage (VREF), FLATPACK
Figure 20. THD and SFDR vs. Reference Voltage (VREF), MSOP
Rev. B | Page 10 of 26
SFDR (dB)
100
12479-205
50
12479-038
0
12479-058
–160
–180
VDD = 2.5V
VIO = 3.3V
fIN = 9972.3Hz
fSMPLE = 588.51ksps
SNR = 85.22dB
SINAD = 85.19dB
THD = –107.6dB
–20
AMPLITUDE (dB OF FULL SCALE)
AMPLITUDE (dB OF FULL SCALE)
–20
Data Sheet
100
AD7981
95
–55°C
+25°C
+175°C
–55°C
+25°C
+210°C
93
95
91
90
87
SINAD (dB)
SINAD (dB)
89
85
85
83
81
80
79
1M
INPUT FREQUENCY (Hz)
75
1
80 100 120 140 160 180 200 220
Figure 27. SINAD vs. Input Frequency, FLATPACK
92
SNR AT VREF = 5V
SNR AT VREF = 2.5V
98
1000
100
INPUT FREQUENCY (kHz)
Figure 24. SINAD vs. Input Frequency, MSOP
100
10
12479-205
100k
12479-118
10k
12479-207
77
75
1k
VREF = 5V
VREF = 2.5V
91
96
90
89
92
SNR (dB)
SNR (dB)
94
90
88
88
87
86
86
84
85
82
0
20
40
60
80 100 120 140 160 180 200
TEMPERATURE (°C)
84
–60 –40 –20
12479-119
80
–60 –40 –20
40
60
Figure 28. SNR vs. Temperature, FLATPACK
–110
–55°C
+25°C
+175°C
–105
20
TEMPERATURE (°C)
Figure 25. SNR vs. Temperature, MSOP
–110
0
–55°C
+25°C
+210°C
–105
THD (dB)
–95
–100
–95
–90
–80
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
–85
1
10
100
INPUT FREQUENCY (kHz)
Figure 29. THD vs. Input Frequency, FLATPACK
Figure 26. THD vs. Frequency, MSOP
Rev. B | Page 11 of 26
1000
12479-206
–90
–85
12479-121
THD (dB)
–100
AD7981
Data Sheet
–100
–109
–101
–108
VREF = 5V
VREF = 2.5V
–102
–107
–103
THD (dB)
THD (dB)
–106
–105
–104
–104
–105
–106
–107
–103
–108
–109
THD AT VREF = 5V
THD AT VREF = 2.5V
–10
40
90
140
190
TEMPERATURE (°C)
–110
–60 –40 –20
12479-122
–101
–60
1.2
60
80 100 120 140 160 180 200 220
IVDD
IVIO
IREF
1.0
0.8
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
40
Figure 33. THD vs. Temperature, FLATPACK
IVDD
IVIO
IREF
0.9
20
TEMPERATURE (°C)
Figure 30. THD vs. Temperature, MSOP
1.0
0
12479-208
–102
0.7
0.6
0.5
0.4
0.3
0.2
0.8
0.6
0.4
0.2
–5
20
45
70
95
120
145
170
TEMPERATURE (°C)
0
–55
TYPICAL POWER-DOWN CURRENT (µA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
2.425
2.475
2.525
2.575
2.625
VDD (V)
12479-120
OPERATING CURRENT (mA)
200
0.8
0
2.375
25
85
125
175
210
Figure 34. Operating Current vs. Temperature, FLATPACK
IVDD
IVIO
IREF
0.9
0
TEMPERATURE (°C)
Figure 31. Operating Current vs. Temperature, MSOP
1.0
–40
Figure 32. Operating Current vs. Supply Voltage (VDD)
180
IVDD
IVIO
IVDD + IVIO
160
140
120
100
80
60
40
20
0
–60 –40 –20
0
20
40
60
80 100 120 140 160 180 200 220
TEMPERATURE (°C)
Figure 35. Typical Power-Down Current vs. Temperature
Rev. B | Page 12 of 26
12479-124
–30
12479-123
0
–55
12479-203
0.1
Data Sheet
AD7981
TERMINOLOGY
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 37).
Differential Nonlinearity (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
The first transition occurs at a level ½ LSB above analog ground
(38.1 µV for the 0 V to 5 V range). The offset error is the
deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) occurs for an
analog voltage 1½ LSB below the nominal full scale (4.999886 V
for the 0 V to 5 V range). The gain error is the deviation of the
actual level of the last transition from the ideal level after the
offset is adjusted out.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Resolution
Effective resolution is calculated as follows and is expressed in
bits:
Effective Resolution = log2(2N/RMS Input Noise)
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together. It
is measured with a signal at −60 dBFS to include all noise sources
and DNL artifacts. The value for dynamic range is expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula and is
expressed in bits:
ENOB = (SINADdB − 1.76)/6.02
Noise Free Code Resolution
Noise free code resolution is the number of bits beyond which it
is impossible to distinctly resolve individual codes. It is
calculated as follows and is expressed in bits:
Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.
Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise)
Rev. B | Page 13 of 26
AD7981
Data Sheet
THEORY OF OPERATION
IN+
MSB
LSB
32,768C
16,384C
4C
2C
C
SWITCHES CONTROL
SW+
C
BUSY
REF
COMP
GND
32,768C
16,384C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
LSB
SW–
CNV
12479-011
MSB
IN–
Figure 36. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7981 is a fast, low power, single-supply, precise 16-bit
ADC that uses a successive approximation architecture.
The AD7981 is capable of converting 600,000 samples per
second (600 kSPS) and powers down between conversions.
When operating at 10 kSPS, for example, it consumes 75 μW
typically, ideal for battery-powered applications.
The AD7981 provides the user with on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7981 can be interfaced to any 1.8 V to 5 V digital logic
family. It is housed in a 10-lead MSOP and 10-lead FLATPACK.
These packages, which combine space savings and allow flexible
configurations, are designed for robustness at extreme temperatures.
CONVERTER OPERATION
The AD7981 is a successive approximation ADC based on
a charge redistribution digital-to-analog converter (DAC).
Figure 36 shows the simplified schematic of the ADC. The
capacitive DAC consists of two identical arrays of 16 binary
weighted capacitors, which are connected to the two comparator
inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via the SW+
and SW− switches. All independent switches are connected to
the analog inputs. Therefore, the capacitor arrays are used as
sampling capacitors and acquire the analog signal on the IN+
and IN− inputs. When the acquisition phase is complete and
the CNV input goes high, a conversion phase is initiated. When
the conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs, IN+ and IN−, captured at the end of the
acquisition phase, is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4 … VREF/65,536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the device returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7981 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. B | Page 14 of 26
Data Sheet
AD7981
Transfer Functions
Table 6. Output Codes and Ideal Input Voltages
The ideal transfer characteristic for the AD7981 is shown in
Figure 37 and Table 6.
Description
FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
111 ... 101
1
2
Analog Input
Digital Output Code
0xFFFF1
0x8001
0x8000
0x7FFF
0x0001
0x00002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
000 ... 010
Figure 38 shows an example of the recommended connection
diagram for the AD7981 when multiple supplies are available.
000 ... 001
–FSR –FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 37. ADC Ideal Transfer Function
V+
V+
REF1
100nF
REFERENCE
BUFFER
100nF
10µF2
2.5V
V–
100nF
V+
1.8V TO 5V
100nF
49.9Ω
DRIVER
AMPLIFIER3
0V TO VREF
REF
2.7nF
V–
VDD
VIO
IN+
SDI
SCK
AD7981
4
IN–
GND
3- OR 4-WIRE INTERFACE5
SDO
CNV
1SEE
THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3SEE THE DRIVER AMPLIFIER CHOICE SECTION.
4OPTIONAL FILTER. SEE THE ANALOG INPUT SECTION.
5SEE THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.
2C
REF
Figure 38. Typical Application Diagram with Multiple Supplies
Rev. B | Page 15 of 26
12479-013
000 ... 000
12479-012
ADC CODE (STRAIGHT BINARY)
111 ... 111
111 ... 110
VREF = 5 V
4.999924 V
2.500076 V
2.5 V
2.499924 V
76.3 μV
0V
AD7981
Data Sheet
ANALOG INPUT
DRIVER AMPLIFIER CHOICE
Figure 39 shows an equivalent circuit of the input structure of
the AD7981.
Although the AD7981 is easy to drive, the driver amplifier must
meet the following requirements:
The two diodes, D1 and D2, provide ESD protection for the analog
inputs, IN+ and IN−. Ensure that the analog input signal never
exceeds the supply rails by more than 0.3 V, because this causes
these diodes to become forward-biased and to start conducting
current. A transient with a very short duration of 10 ms applied
on the analog inputs, IN+ and IN−, during latch-up testing
shows that these diodes can then handle a forward-biased
current of 130 mA maximum. For instance, these conditions
may eventually occur when the supplies of the input buffer (U1)
are different from VDD. In such a case (for example, an input
buffer with a short circuit), use the current limitation to protect
the device.
•
SNRLOSS
REF
CPIN
RIN
CIN
D2
GND
12479-014
D1
IN+
OR IN–
Figure 39. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, model the impedance of the
analog inputs (IN+ and IN−) as a parallel combination of the
capacitor, CPIN, and the network formed by the series connection of
RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of some serial
resistors and the on resistance of the switches. CIN is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to CPIN. RIN and CIN combine to make a onepole, low-pass filter that reduces undesirable aliasing effects and
limits the noise.
Keep the noise generated by the driver amplifier as low as
possible to preserve the SNR and transition noise performance of the AD7981. The noise coming from the driver is
filtered by the one-pole, low-pass filter of the AD7981 analog
input circuit made by RIN and CIN, or by the external filter, if
one is used. Because the typical noise of the AD7981 is
47.3 µV rms, the SNR degradation due to the amplifier is
•
•


47.3
= 20 log 

π
 47.32 + f −3dB (Ne N )2
2







where:
f–3dB is the input bandwidth in MHz of the AD7981
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
For ac applications, the driver must have THD
performance commensurate with the AD7981.
For multichannel multiplexed applications, the driver
amplifier and the AD7981 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In an amplifier data sheet, settling
times at 0.1% to 0.01% are more commonly specified, and
may differ significantly from the settling time at a 16-bit
level and, therefore, must be verified prior to driver
selection.
The AD8634 is a rail-to-rail output, precision, low power, high
temperature qualified, dual amplifier recommended for driving
the input of the AD7981.
When the source impedance of the driving circuit is low, drive
the AD7981 directly. Large source impedances significantly
affect the ac performance, especially THD. The dc performances
are less sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD degrades as a function of the source impedance and
the maximum input frequency.
Rev. B | Page 16 of 26
Data Sheet
AD7981
1
OPERATING CURRENTS (mA)
The AD7981 voltage reference input, REF, has a dynamic input
impedance and must therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Printed Circuit Board (PCB) Layout
section.
When REF is driven by a very low impedance source, a ceramic
chip capacitor is appropriate for optimum performance. The
high temperature qualified low temperature drift ADR225 2.5 V
reference and the low power AD8634 reference buffer are
recommended for the AD7981.
VDD = 2.5V
VREF = 5V
VIO = 3V
IVDD
0.1
IREF
IVIO
0.01
0.001
10000
The REF pin must be decoupled with a ceramic chip capacitor of
at least 10 μF (X5R, 1206 size) for optimum performance.
100000
THROUGHPUT RATE (SPS)
600000
12479-055
VOLTAGE REFERENCE INPUT
Figure 41. Operating Currents vs. Throughput Rate
There is no need for an additional lower value ceramic decoupling
capacitor (for example, 100 nF) between the REF and GND pins.
DIGITAL INTERFACE
POWER SUPPLY
Although the AD7981 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7981 uses two power supply pins: a core supply, VDD, and
a digital input/output interface supply, VIO. VIO allows direct
interfacing with any logic between 1.8 V and 5 V. To reduce the
number of supplies needed, tie VIO and VDD together. The
AD7981 is independent of power supply sequencing between
VIO and VDD. Additionally, it is insensitive to power supply
variations over a wide frequency range, as shown in Figure 40.
80
PSRR (dB)
75
The AD7981, when in chain mode, provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line, similar to a shift register.
70
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. CS mode is selected if
SDI is high, and chain mode is selected if SDI is low. The SDI
hold time is such that, when SDI and CNV are connected
together, chain mode is selected.
65
1
10
100
FREQUENCY (kHz)
1000
12479-062
60
55
The AD7981, when in CS mode, is compatible with SPI, QSPI™,
MICROWIRE™, and digital hosts. The AD7981 interface can
use either a 3-wire or 4-wire interface. A 3-wire interface using
the CNV, SCK, and SDO signals minimizes wiring connections
and is useful, for instance, in isolated applications. A 4-wire
interface using the SDI, CNV, SCK, and SDO signals allows
CNV, which initiates the conversions, to be independent of the
readback timing (SDI). The 4-wire interface is useful in low jitter
sampling or simultaneous sampling applications.
Figure 40. PSRR vs. Frequency
The AD7981 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, which makes the device ideal for low sampling
rate (even of a few Hz) and low battery-powered applications.
In either mode, the AD7981 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be used as
a busy signal indicator to interrupt the digital host and to trigger
the data reading. Otherwise, without a busy indicator, the user
must time out the maximum conversion time prior to readback.
The busy indicator feature is enabled in the following modes:


Rev. B | Page 17 of 26
In CS mode if CNV or SDI is low when the ADC conversion
ends (see Figure 45 and Figure 49, respectively).
In chain mode if SCK is high during the CNV rising edge
(see Figure 53).
AD7981
Data Sheet
CS MODE, 3-WIRE WITHOUT A BUSY INDICATOR
time elapses and then held high for the maximum conversion
time to avoid the generation of the busy signal indicator. When
the conversion is complete, the AD7981 enters the acquisition
phase and powers down.
The 3-wire CS mode without a busy indicator is typically used
when a single AD7981 is connected to an SPI-compatible digital
host. The connection diagram is shown in Figure 42, and the
corresponding timing is given in Figure 43.
When CNV goes low, the MSB is output onto SDO. The remaining
data bits are then clocked by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the 16th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. When
a conversion is initiated, it continues until completion, irrespective
of the state of CNV, which can be useful, for instance, for bringing
CNV low to select other SPI devices, such as analog multiplexers.
However, CNV must return high before the minimum conversion
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7981
SDO
DATA INPUT
12479-015
SCK
CLK
Figure 42. 3-Wire CS Mode Without Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
2
3
14
tHSDO
16
tSCKH
tEN
SDO
15
tDSDO
D15
D14
D13
tDIS
D1
D0
Figure 43. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. B | Page 18 of 26
12479-016
1
SCK
Data Sheet
AD7981
When the conversion is complete, SDO goes from high impedance
to low. With a pull-up resistor on the SDO line, use this transition
as an interrupt signal to initiate the data reading controlled by
the digital host. The AD7981 then enters the acquisition phase
and powers down. The data bits are clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge captures the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge
or when CNV goes high, whichever is earlier, SDO returns to
high impedance.
CS MODE, 3-WIRE WITH A BUSY INDICATOR
The 3-wire CS mode with a busy indicator is typically used
when a single AD7981 is connected to an SPI-compatible digital
host having an interrupt input. The connection diagram is
shown in Figure 44, and the corresponding timing is given in
Figure 45.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. SDO is
maintained in high impedance until the completion of the
conversion, irrespective of the state of CNV. Prior to the minimum
conversion time, CNV can be used to select other SPI devices,
such as analog multiplexers, but CNV must be returned low
before the minimum conversion time elapses and then held low
for the maximum conversion time to guarantee the generation
of the busy signal indicator.
If multiple AD7981 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Keep this contention as short as possible to
limit extra power dissipation.
CONVERT
VIO
CNV
VIO
AD7981
SDO
DATA INPUT
SCK
IRQ
12479-017
SDI
DIGITAL HOST
47kΩ
CLK
Figure 44. 3-Wire CS Mode with Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
SDO
D15
D14
D1
D0
Figure 45. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
Rev. B | Page 19 of 26
12479-018
SCK
AD7981
Data Sheet
CS MODE, 4-WIRE WITHOUT A BUSY INDICATOR
time elapses and then held high for the maximum conversion
time to avoid the generation of the busy signal indicator.
The 4-wire CS mode without a busy indicator is typically used
when multiple AD7981 devices are connected to an SPI-compatible
digital host. A connection diagram example using two AD7981
devices is shown in Figure 46, and the corresponding timing is
given in Figure 47.
When the conversion is complete, the AD7981 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge captures the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
it has an acceptable hold time. After the 16th SCK falling edge or
when SDI goes high, whichever is earlier, SDO returns to high
impedance, and another AD7981 can be read.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
CNV
AD7981
SDO
SDI
AD7981
SCK
SDO
SCK
12479-019
SDI
DIGITAL HOST
CNV
DATA INPUT
CLK
Figure 46. 4-Wire CS Mode Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
SCK
2
3
14
tHSDO
SDO
15
16
17
18
30
31
32
tSCKH
tEN
tDIS
tDSDO
D15
D14
D13
D1
D0
D15
D14
Figure 47. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing
Rev. B | Page 20 of 26
D1
D0
12479-020
1
Data Sheet
AD7981
select other SPI devices, such as analog multiplexers, but SDI
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
CS MODE, 4-WIRE WITH A BUSY INDICATOR
The 4-wire CS mode with a busy indicator is typically used
when a single AD7981 is connected to an SPI-compatible digital
host that has an interrupt input, and it is desired to keep CNV,
which is used to sample the analog input, independent of the
signal used to select the data reading. This requirement is
particularly important in applications where low jitter on CNV
is desired.
With a pull-up resistor on the SDO line, use this transition as an
interrupt signal to initiate the data readback controlled by the
digital host. The AD7981 then enters the acquisition phase and
powers down. The data bits are clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge captures the data, a digital host
using the SCK falling edge allows a faster reading rate provided
it has an acceptable hold time. After the optional 17th SCK
falling edge or SDI going high, whichever is earlier, the SDO
returns to high impedance.
The connection diagram is shown in Figure 48, and the
corresponding timing is given in Figure 49.
With SDI high, a rising edge on CNV initiates a conversion, selects
CS mode, and forces SDO to high impedance. In this mode, CNV
must be held high during the conversion phase and the subsequent
data readback (if SDI and CNV are low, SDO is driven low).
Prior to the minimum conversion time, SDI can be used to
CS1
CONVERT
VIO
CNV
AD7981
SDO
DATA INPUT
SCK
IRQ
12479-021
SDI
DIGITAL HOST
47kΩ
CLK
Figure 48. 4-Wire CS Mode with Busy Indicator Connection Diagram
tCYC
CNV
tCONV
ACQUISITION
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
tEN
SDO
D15
D14
D1
Figure 49. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
Rev. B | Page 21 of 26
D0
12479-022
1
SCK
AD7981
Data Sheet
during the conversion phase and the subsequent data readback.
When the conversion is complete, the MSB is output onto SDO,
and the AD7981 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 16 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. Although the rising edge
captures the data, a digital host using the SCK falling edge
allows a faster reading rate and, consequently, more AD7981
devices in the chain, provided the digital host has an acceptable
hold time. The total readback time allows a reduction in the
maximum conversation rate.
CHAIN MODE WITHOUT A BUSY INDICATOR
Use chain mode without a busy indicator to daisy-chain multiple
AD7981 devices on a 3-wire serial interface. This feature is useful
for reducing component count and wiring connections, for
example, in isolated multiconverter applications or for systems
with a limited interfacing capacity. Data readback is analogous
to clocking a shift register.
A connection diagram example using two AD7981 devices is
shown in Figure 50, and the corresponding timing is given in
Figure 51.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects chain mode,
and disables the busy indicator. In this mode, CNV is held high
CONVERT
CNV
AD7981
SDO
SDI
AD7981
A
SCK
SDO
DATA INPUT
B
SCK
12479-023
SDI
DIGITAL HOST
CNV
CLK
Figure 50. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
tHSCKCNV
2
3
14
tSSDISCK
16
17
18
30
31
32
DA1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDIB
15
DA15
DA14
DA13
DA1
DA0
DB1
DB0
tHSDO
SDOB
DB15
DB14
DB13
DA15
DA14
Figure 51. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. B | Page 22 of 26
12479-024
tDSDO
Data Sheet
AD7981
data readback. When all ADCs in the chain have completed
their conversions, the SDO pin of the ADC closest to the digital
host (see the AD7981 ADC labeled C in Figure 52) is driven
high. This transition on SDO can be used as a busy indicator to
trigger the data readback controlled by the digital host. The
AD7981 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are clocked out,
MSB first, by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 16 × N + 1 clocks are required to read back the N ADCs.
Although the rising edge captures the data, a digital host using
the SCK falling edge allows a faster reading rate and, consequently,
more AD7981 devices in the chain, provided the digital host has
an acceptable hold time.
CHAIN MODE WITH A BUSY INDICATOR
Chain mode with a busy indicator can also be used to daisy-chain
multiple AD7981 devices on a 3-wire serial interface while
providing a busy indicator. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using three AD7981 devices is
shown in Figure 52, and the corresponding timing is given in
Figure 53.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects chain
mode, and enables the busy indicator feature. In this mode,
CNV is held high during the conversion phase and the subsequent
CONVERT
SDI
CNV
AD7981
SDO
SDI
CNV
AD7981
SDO
AD7981
SDI
A
B
C
SCK
SCK
SCK
DIGITAL HOST
SDO
DATA INPUT
IRQ
12479-025
CNV
CLK
Figure 52. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDIA
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
1
tHSCKCNV
2
3
4
15
16
tSSDISCK
DA15
SDOA = SDIB
DA14
DA13
18
19
31
32
33
34
35
tSCKL
tHSDISCK
tEN
17
DA1
DB15
DB14
DB13
tDSDOSDI
DB1
DB0
DA15
DA14
DA1
DA0
tDSDOSDI
SDOC
49
DA0
tDSDO
SDOB = SDIC
48
tDSDOSDI
tHSDO
tDSDOSDI
47
tDSDOSDI
DC15
DC14
DC13
DC1
DC 0
DB15
DB14
DB 1
DB0
Figure 53. Chain Mode with Busy Indicator Serial Interface Timing
Rev. B | Page 23 of 26
DA15
DA14
DA1
DA0
12479-026
SCK
tSCKH
AD7981
Data Sheet
APPLICATIONS INFORMATION
A growing number of industries demand low power electronics
that can operate reliably at temperatures of 175°C and higher.
The AD7981 enables precision analog signal processing from
the sensor to the processor at high temperatures for these types
of applications.
Figure 54 shows the simplified signal chain of the data acquisition
instrument.
In downhole drilling, avionics, and other extreme temperature
environment applications, signals from various sensors are sampled
to collect information about the surrounding geologic formations.
These sensors take the form of electrodes, coils, piezoelectric, or
other transducers. Accelerometers and gyroscopes provide
information about the inclination, vibration, and rotation rate.
Some of these sensors are very low bandwidth, whereas others have
information in the audio frequency range and higher. The
AD7981 is ideal for sampling data from sensors with varying
bandwidth requirements while maintaining power efficiency
and accuracy. The small footprint of the AD7981 makes it easy
to include multiple channels even in space constrained layouts,
such as the very narrow board widths prevalent in downhole
tools. In addition, the flexible digital interface allows simultaneous
sampling in more demanding applications, while also allowing
simple daisy-chained readback for low pin count systems.
For a complete selection of available high temperature products,
see the high temperature product list and qualification data
available at www.analog.com/hightemp.
ADR225
REFERENCE
POWER
MANAGEMENT
COMMUNICATION
TO SURFACE
SENSOR SIGNALS
ACOUSTIC, TEMPERATURE,
RESISTIVITY, PRESSURE
AD8634
AMP
SENSORS
AD8229
INST
AMP
AD7981
ADC
AD8634
AMP
AD7981
ADC
PROCESSOR
INERTIAL SENSORS
INCLINATION, VIBRATION,
ROTATION RATE
ADXL206
ACCELEROMETER
COMMUNICATIONS
INTERFACE
AD8634
AMP
AD7981
ADC
AD8634
GYROSCOPE
AMP
AD7981
ADC
Figure 54. Simplified Data Acquisition System Signal Chain
Rev. B | Page 24 of 26
MEMORY
12479-142
ADXRS645
Data Sheet
AD7981
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Design the PCB that houses the AD7981 so that the analog and
digital sections are separated and confined to certain areas of
the board. The pinout of the AD7981, with all of its analog
signals on the left side and all of its digital signals on the right
side, eases this task.
AD7981
Use at least one ground plane. It can be common or split between
the digital and analog section. If the ground plane is split, join
the planes underneath the AD7981.
12479-028
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7981 is
used as a shield. Fast switching signals, such as CNV or clocks,
must never run near analog signal paths. Avoid crossover of
digital and analog signals.
Figure 55. Example PCB Layout of the AD7981 (Top Layer)
The AD7981 voltage reference input, REF, has a dynamic input
impedance and must be decoupled with minimal parasitic
inductances. The reference decoupling ceramic capacitor must
be placed close to, ideally right up against, the REF and GND
pins and connecting them with wide, low impedance traces.
Decouple the AD7981 power supplies, VDD and VIO, with
ceramic capacitors, typically 100 nF, placed close to the AD7981
and connected using short and wide traces to provide low
impedance paths and to reduce the effect of glitches on the
power supply lines.
12479-027
An example of a layout following these rules is shown in
Figure 55 and Figure 56.
Figure 56. Example PCB Layout of the AD7981 (Bottom Layer)
Rev. B | Page 25 of 26
AD7981
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
5.15
4.90
4.65
6
1
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 57. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
1.00
0.260
0.255 SQ
0.250
0.191
0.185 SQ
0.179
1
0.205
0.200
0.195
10
5
R 0.012
BSC
0.185 SQ
0.019
0.017
0.015
6
TOP VIEW
INDEX
MARK
0.0946
0.0860
0.0774
END VIEW
0.007
0.005
0.004
0.039
0.035
0.031
PKG-004181
0.035
BSC
BOTTOM VIEW
0.026 MIN
SIDE VIEW
05-12-2015-A
0.055
0.050
0.045
Figure 58. 10-Lead Ceramic Flat Package [FLATPACK]
(F-10-2)
Dimensions shown in inches
ORDERING GUIDE
Model 1
AD7981HRMZ
AD7981HFZ
1
Integral
Nonlinearity (INL)
±2.0 LSB
±2.5 LSB
Temperature
Range
−55°C to +175°C
−55°C to +210°C
Package Description
10-Lead Mini Small Outline Package [MSOP]
10-Lead Ceramic Flat Package [FLATPACK]
Z = RoHS Compliant Part.
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12479-0-7/17(B)
Rev. B | Page 26 of 26
Package
Option
RM-10
F-10-2
Branding
C7C
Ordering
Quantity
50