DATA SHEET MOS INTEGRATED CIRCUIT MC-4532DA726 32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE EO Description The MC-4532DA726 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of 128M SDRAM: µPD45128441 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. L Features • 33,554,432 words by 72 bits organization (ECC type) • Clock frequency and access time from CLK Part number MC-4532DA726EFB-A10 (MAX.) CL = 3 125 MHz 6 ns PC100 Registered DIMM CL = 2 100 MHz 6 ns Rev. 1.2 Compliant CL = 3 100 MHz 6 ns CL = 2 77 MHz 7 ns CL = 3 CL = 3 CL = 2 MC-4532DA726XFB-A80 CL = 3 CL = 2 125 MHz 6 ns 100 MHz 6 ns 100 MHz 6 ns 77 MHz 7 ns 125 MHz 6 ns 100 MHz 6 ns CL = 3 100 MHz CL = 2 77 MHz t uc MC-4532DA726XFB-A10 Module type (MAX.) CL = 2 MC-4532DA726PFB-A10 Access time from CLK od MC-4532DA726PFB-A80 Clock frequency Pr MC-4532DA726EFB-A80 /CAS latency 6 ns 7 ns • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by BA0 and BA1 (Bank Select) • Programmable burst-length (1, 2, 4, 8 and Full Page) • Programmable wrap sequence (Sequential / Interleave) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0072N10 (1st edition) (Previous No. M13633EJ8V0DS00) Date Published January 2001 CP(K) Printed in Japan This product became EOL in March, 2004. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. MC-4532DA726 • Programmable /CAS latency (2, 3) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • All DQs have 10 Ω ± 10 % of series resistor • Single 3.3 V ± 0.3 V power supply • LVTTL compatible • 4,096 refresh cycles / 64 ms • Burst termination by Burst Stop command and Precharge command EO • 168-pin dual in-line memory module (Pin pitch = 1.27 mm) • Registered type • Serial PD Ordering Information Part number MC-4532DA726EFB-A80 Clock frequency Package Mounted devices (MAX.) 125 MHz 168-pin Dual In-line Memory Module 18 pieces of µPD45128441G5 (Rev. E) L 100 MHz (Socket Type) (10.16 mm (400) TSOP (II)) MC-4532DA726PFB-A80 125 MHz Edge connector: Gold plated 18 pieces of µPD45128441G5 (Rev. P) MC-4532DA726PFB-A10 100 MHz 43.18 mm height (10.16 mm (400) TSOP (II)) MC-4532DA726XFB-A80 125 MHz 18 pieces of µPD45128441G5 (Rev. X) MC-4532DA726XFB-A10 100 MHz (10.16 mm (400) TSOP (II)) od Pr MC-4532DA726EFB-A10 t uc 2 Data Sheet E0072N10 MC-4532DA726 Pin Configuration 168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal. EO 85 86 87 88 89 90 91 92 93 94 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 VSS NC NC Vcc /CAS DQMB4 DQMB5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 CLK1 NC VSS CKE0 NC DQMB6 DQMB7 NC Vcc NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc 1 2 3 4 5 6 7 8 9 10 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 BA1(A12) Vcc 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 L 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 Pr A0 - A11 : Address Inputs [Row: A0 - A11, Column: A0 - A9, A11] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs : Clock Input CKE0 : Clock Enable Input WP : Write Protect /CS0, /CS2 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQMB0 - DQMB7 : DQ Mask Enable od CLK0 - CLK3 SDA SCL VCC VSS REGE NC Data Sheet E0072N10 t uc SA0 - SA2 : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : Register / Buffer Enable : No Connection 3 MC-4532DA726 Block Diagram /RCS0 RDQMB4 RDQMB0 DQ 3 DQ 2 DQ 1 DQ 0 DQ 0 DQM DQ 1 D0 DQ 2 DQ 7 DQ 6 DQ 5 DQ 4 /CS DQ 32 DQ 33 DQ 34 DQ 35 DQ 0 DQM /CS DQ 1 D9 DQ 2 DQ 3 DQ 0 DQM DQ 1 D1 DQ 2 DQ 3 /CS DQ 36 DQ 37 DQ 38 DQ 39 DQ 0 DQM /CS DQ 1 D10 DQ 2 DQ 3 DQ 11 DQ 10 DQ 9 DQ 8 DQ 0 DQM DQ 1 D2 DQ 2 DQ 3 /CS DQ 15 DQ 14 DQ 12 DQ 13 DQ 0 DQM DQ 1 D3 DQ 2 DQ 3 /CS CB 2 CB 3 CB 0 CB 1 DQ 0 DQM DQ 1 D4 DQ 2 DQ 3 /CS DQ 3 EO RDQMB1 RDQMB5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 0DQM /CS DQ 1 D11 DQ 2 DQ 3 DQ 45 DQ 44 DQ 46 DQ 47 DQ 0 DQM /CS DQ 1 D12 DQ 2 DQ 3 CB 5 CB 4 CB 7 CB 6 DQ 0 DQM /CS DQ 1 D13 DQ 2 DQ 3 D1 - D17 Register1, Register2, PLL VCC C D1 - D17 Register1, Register2, PLL VSS SERIAL PD SDA SCL A0 L SA0 SA1 SA2 RDQMB2 /CS DQ 0 DQM DQ 1 D6 DQ 2 /CS DQ 3 RDQMB3 DQ 48 DQ 49 DQ 50 DQ 51 DQ 0 DQM /CS DQ 1 D14 DQ 2 DQ 52 DQ 53 DQ 54 DQ 55 DQ 0 DQM /CS DQ 1 D15 DQ 2 DQ 3 DQ 31 DQ 30 DQ 29 DQ 28 DQ 0 DQM DQ 1 D8 DQ 2 DQ 3 DQ 3 /CS /CS DQ 56 DQ 57 DQ 58 DQ 59 DQ 0 DQM /CS DQ 1 D16 DQ 2 DQ 3 DQ 60 DQ 61 DQ 62 DQ 63 DQ 0 DQM /CS DQ 1 D17 DQ 2 DQ 3 RA0 - RA6 A0 - A6 : D0 - D17 /RAS /RRAS /RAS : D0 - D17 /CAS /RCAS /CAS : D0 - D17 /RWE /WE : D0 - D17 Register1 12 pF A7 - A11, BA0, BA1 CKE0 DQMB2, DQMB3, DQMB6, DQMB7 /CS2 Register2 PLL LE LE VCC 10 kΩ Remarks 1. The value of all resistors of DQs is 10 Ω. 2. D0 - D17: µPD45128441 (8M words × 4 bits × 4 banks) 3. REGE ≤ VIL: Buffer mode REGE ≥ VIH: Register mode 4. Register: HD74ALVC16835 PLL: HD74CDC2509B Data Sheet E0072N10 CLK : D0, D1, D9 CLK : D2, D10, D11 CLK : D3, D4, D12 CLK : D5, D13, D14 CLK : D6, D7, D15 CLK : D8, D16, D17 CLK : Register1, Register2 RA7 - RA11, RBA0, RBA1 A7 - A11, BA0, BA1 : D0 - D17 RCKE0 CKE : D0 - D17 RDQMB 2, RDQMB 3, RDQMB 6, RDQMB 7 /RCS2 /RCS0 /CS0 10 Ω CLK0 t uc RDQMB0, RDQMB1, RDQMB4, RDQMB5 DQMB0, DQMB1, DQMB4, DQMB5 4 CLK1 - CLK3 od DQ 0 DQM DQ 1 D7 DQ 2 /WE 10 Ω DQ 3 RDQMB7 DQ 27 DQ 26 DQ 25 DQ 24 A0 - A6 REGE RDQMB6 Pr DQ 23 DQ 22 DQ 21 DQ 20 DQ 0 DQM DQ 1 D5 DQ 2 DQ 3 WP A2 47 kΩ /RCS2 DQ 18 DQ 19 DQ 17 DQ 16 A1 MC-4532DA726 Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit VCC –0.5 to +4.6 V Voltage on input pin relative to GND VT –0.5 to +4.6 V EO Voltage on power supply pin relative to GND Short circuit output current IO 50 mA Power dissipation PD 21 W Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits L described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Supply voltage High level input voltage Low level input voltage Operating ambient temperature Pr Parameter Symbol Parameter Input capacitance TYP. MAX. Unit VCC 3.0 3.3 3.6 V VIH 2.0 VCC + 0.3 V VIL –0.3 +0.8 V TA 0 70 °C MAX. Unit pF Test condition MIN. TYP. CI1 A0 – A11, BA0 (A13), BA1 (A12), /RAS, /CAS, /WE 4 10 CI2 CLK0 15 25 CI3 CKE0 7 20 CI4 /CS0, /CS2 CI5 DQMB0 - DQMB7 CI/O DQ0 - DQ63, CB0 - CB7 Data Sheet E0072N10 t uc Data input/output capacitance Symbol MIN. od Capacitance (TA = 25 °C, f = 1 MHz) Condition 4 10 3 10 5 13 pF 5 MC-4532DA726 DC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Operating current Symbol ICC1 Test condition Burst length = 1 Grade /CAS latency = 2 tRC ≥ tRC (MIN.), IO = 0 mA /CAS latency = 3 Precharge standby current in EO power down mode Precharge standby current in ICC2P ICC2PS ICC2N non power down mode Active standby current in power down mode MAX. Unit Notes -A80 2,100 mA -A10 2,100 -A80 2,100 -A10 2,100 CKE ≤ VIL (MAX.), tCK = 15 ns 268 CKE ≤ VIL (MAX.), tCK = ∞ 98 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 610 1 mA mA Input signals are changed one time during 30 ns. ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ , 224 Input signals are stable. ICC3P ICC3PS ICC3N CKE ≤ VIL (MAX.), tCK = 15 ns 340 CKE ≤ VIL (MAX.), tCK = ∞ 152 CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.), 790 L Active standby current in MIN. non power down mode mA mA Input signals are changed one time during 30 ns. ICC3NS CKE ≥ VIH (MIN.), tCK = ∞ , 440 Input signals are stable. (Burst mode) ICC4 tCK ≥ tCK (MIN.), IO = 0 mA /CAS latency = 2 Pr Operating current /CAS latency = 3 CBR (Auto) Refresh current ICC5 tRC ≥ tRC (MIN.) /CAS latency = 2 2,190 -A10 1,830 -A80 2,640 -A10 2,280 -A80 4,440 -A10 4,440 od /CAS latency = 3 Self refresh current ICC6 CKE ≤ 0.2 V Input leakage current II (L) VI = 0 to 3.6 V, All other pins not under test = 0 V Input leakage current (CKE0) -A80 IO (L) DOUT is disabled, VO = 0 to 3.6 V High level output voltage VOH IO = –4.0 mA Low level output voltage VOL IO = +4.0 mA 4,440 -A10 4,440 2 mA 3 286 mA –10 +10 µA –20 +20 –1.5 +1.5 µA t uc Output leakage current -A80 mA 2.4 V 0.4 V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.). 6 Data Sheet E0072N10 MC-4532DA726 AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) EO Output timing measurement reference level Value Unit 2.4 / 0.4 V 1.4 V 1 ns 1.4 V tCK tCH CLK tCL 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V L Input 0.4 V tAC tOH od Pr Output t uc Data Sheet E0072N10 7 MC-4532DA726 Synchronous Characteristics Parameter Symbol Clock cycle time Access time from CLK -A80 -A10 Unit MIN. MAX. MIN. MAX. /CAS latency = 3 tCK3 8 (125 MHz) 10 (100 MHz) ns /CAS latency = 2 tCK2 10 (100 MHz) 13 (77 MHz) ns /CAS latency = 3 tAC3 6 6 ns 1 /CAS latency = 2 tAC2 6 7 ns 1 50 125 50 100 MHz Input CLK duty cycle 40 60 40 60 % EO Input clock frequency Data-out hold time Note /CAS latency = 3 tOH3 3 3 ns 1 /CAS latency = 2 tOH2 3 3 ns 1 tLZ 0 /CAS latency = 3 tHZ3 3 6 3 6 ns /CAS latency = 2 tHZ2 3 6 3 7 ns Data-in setup time tDS 2 2 ns Data-in hold time tDH 1 1 ns Address setup time tAS 2 2 ns Address hold time tAH 1 1 ns CKE setup time tCKS 2 2 ns Data-out low-impedance time Data-out high- impedance time 0 L Pr CKE hold time ns tCKH 1 1 ns CKE setup time (Power down exit) tCKSP 2 2 ns Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 - tCMS 2 2 ns tCMH 1 1 ns DQMB7) setup time Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 - Note 1. Output load od DQMB7) hold time Z = 50 Ω Output 50 pF 8 Data Sheet E0072N10 t uc Remark These specifications are applied to the monolithic device. MC-4532DA726 Asynchronous Characteristics Parameter Symbol -A80 MIN. -A10 MAX. MIN. Unit MAX. tRC 70 70 ns REF to REF/ACT command period (Refresh) tRC1 70 78 ns ACT to PRE command period tRAS 48 PRE to ACT command period tRP 20 20 ns Delay time ACT to READ/WRITE command tRCD 20 20 ns ACT(one) to ACT(another) command period tRRD 16 20 ns Data-in to PRE command period tDPL −1CLK+8 −1CLK+10 ns /CAS latency = 3 tDAL3 20 20 ns /CAS latency = 2 tDAL2 20 20 ns tRSC 2 2 CLK tT 0.5 EO ACT to REF/ACT command period (Operation) Data-in to ACT(REF) command period (Auto precharge) Mode register set cycle time Transition time L Refresh time (4,096 refresh cycles) 120,000 tREF 30 50 Note 120,000 1 64 ns 30 ns 64 ms od Pr t uc Data Sheet E0072N10 9 MC-4532DA726 Serial PD (1/2) Byte No. 0 Function Described Defines the number of bytes written into serial PD memory Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 1 0 0 0 0 0 0 0 Notes 128 bytes Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes 2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM 3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows 4 Number of columns 0BH 0 0 0 0 1 0 1 1 11 columns 5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank EO 1 6 Data width 48H 0 1 0 0 1 0 0 0 72 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL 9 CL = 3 Cycle time -A80 80H 1 0 0 0 0 0 0 0 8 ns -A10 A0H 1 0 1 0 0 0 0 0 10 ns 10 CL = 3 Access time -A80 60H 0 1 1 0 0 0 0 0 6 ns 11 DIMM configuration type -A10 L 60H 0 1 1 0 0 0 0 0 6 ns 02H 0 0 0 0 0 0 1 0 ECC Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal 13 SDRAM width 04H 0 0 0 0 0 1 0 0 x4 14 Error checking SDRAM width 04H 0 0 0 0 0 1 0 0 x4 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F 17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks 18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3 19 /CS latency supported 20 /WE latency supported Pr 12 01H 0 0 0 0 0 0 0 1 0 01H 0 0 0 0 0 0 0 1 0 Registered SDRAM module attributes 1FH 0 0 0 1 1 1 1 1 22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0 23 CL = 2 Cycle time -A80 A0H 1 0 1 0 0 0 0 0 10 ns -A10 D0H 1 1 0 1 0 0 0 0 13 ns -A80 60H 0 1 1 0 0 0 0 0 6 ns -A10 70H 0 1 1 1 0 0 0 0 7 ns 00H 0 0 0 0 0 0 0 0 14H 0 0 0 1 0 1 0 0 CL = 2 Access time 25-26 od 21 24 tRP(MIN.) -A80 -A10 14H 0 0 0 1 0 1 0 0 20 ns 28 tRRD(MIN.) -A80 10H 0 0 0 1 0 0 0 0 16 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns 29 tRCD(MIN.) -A80 14H 0 0 0 1 0 1 0 0 20 ns -A10 14H 0 0 0 1 0 1 0 0 20 ns -A80 30H 0 0 1 1 0 0 0 0 48 ns -A10 32H 0 0 1 1 0 0 1 0 50 ns 40H 0 1 0 0 0 0 0 0 256M bytes 31 tRAS(MIN.) Module bank density Data Sheet E0072N10 20 ns t uc 27 30 10 Hex MC-4532DA726 (2/2) Byte No. Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 32 Command and address signal input setup time Function Described 20H 0 0 1 0 0 0 0 0 2 ns Notes 33 Command and address signal input hold time 10H 0 0 0 1 0 0 0 0 1 ns 34 Data signal input setup time 20H 0 0 1 0 0 0 0 0 2 ns 35 Data signal input hold time 10H 0 0 0 1 0 0 0 0 1 ns 36-61 EO 62 SPD revision 63 Checksum for bytes 0 - 62 64-71 72 73-90 91 00H 0 0 0 0 0 0 0 0 12H 0 0 0 1 0 0 1 0 -A80 3AH 0 0 1 1 1 0 1 0 -A10 A0H 1 0 1 0 0 0 0 0 1.2 A Manufacture’s JEDEC ID code Manufacturing location Manufacture’s P/N Revision Code Manufacturing date 95-98 Assembly serial number 99-125 Mfg specific L 93-94 126 Intel specification frequency 64H 0 1 1 0 0 1 0 0 127 Intel specification /CAS -A80 87H 1 0 0 0 0 1 1 1 latency support -A10 85H 1 0 0 0 0 1 0 1 Pr Timing Chart 100 MHz Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N). od t uc Data Sheet E0072N10 11 MC-4532DA726 Package Drawing 168-PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) Y M1 (AREA B) Z N EO R Q M L A M2 (AREA A) J S G T (OPTIONAL HOLES) K C B I B H U E D L A1 (AREA A) ITEM Pr detail of B part detail of A part D2 W od V P X D1 MILLIMETERS A 133.35 A1 133.35±0.13 B 11.43 C 36.83 D 6.35 D1 2.0 D2 3.125 E G 54.61 6.35 H 1.27 (T.P.) I J 8.89 24.495 K L 42.18 17.78 M 43.18±0.13 23.40 M2 19.78 N 4.0 MAX. P 1.0 Q R R2.0 4.0±0.10 S φ 3.0 T U 1.27±0.1 4.0 MIN. V W 0.2±0.15 1.0±0.05 X Y 2.54±0.10 3.0 MIN. t uc M1 Z 3.0 MIN. M168S-50A107 12 Data Sheet E0072N10 MC-4532DA726 [MEMO] L EO od Pr t uc Data Sheet E0072N10 13 MC-4532DA726 [MEMO] L EO od Pr t uc 14 Data Sheet E0072N10 MC-4532DA726 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using EO insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided L to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and 3 Pr related specifications governing the devices. STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does od not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. t uc Data Sheet E0072N10 15 MC-4532DA726 CAUTION FOR HANDLING MEMORY MODULES EO When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. L • The information in this document is current as of September, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. • Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above). od Pr t uc M8E 00. 4