INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40097B buffers 3-state hex non-inverting buffer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF40097B buffers 3-state hex non-inverting buffer DESCRIPTION The HEF40097B is a hex non-inverting buffer with 3-state outputs. The 3-state outputs are controlled by two enable inputs (EO4 and EO2). A HIGH on EO4 causes four of the six buffer elements to assume a high impedance or OFF-state, regardless of the other input conditions and a HIGH on EO2 causes the outputs of the remaining two buffer elements to assume a high impedance or OFF-state, regardless of the other input conditions. Fig.2 Pinning diagram. HEF40097BP(N): 16-lead DIL; plastic (SOT38-1) HEF40097BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF40097BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING I1 to I6 buffer inputs EO4, EO2 enable inputs (active LOW) O1 to O6 buffer outputs (active HIGH) FAMILY DATA, IDD LIMITS category BUFFERS Fig.1 Functional diagram. See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF40097B buffers 3-state hex non-inverting buffer Fig.3 Logic diagram. DC CHARACTERISTICS VSS = 0 V Tamb (°C) HEF VDD V VOH V VOL V −40 SYMBOL +25 MIN. MAX. MIN. MAX. Output current HIGH HIGH Output current LOW 5 4,6 10 9,5 15 13,5 5 2,5 −IOH −IOH 4,75 0,4 10 0,5 15 1,5 IOL +85 MIN. MAX. 1,2 1,0 0,8 mA 3,8 3,2 2,5 mA 12,0 10,0 8,0 mA 3,8 3,2 2,5 mA 3,5 2,9 2,3 mA 12,0 10,0 8,0 mA 24,0 20,0 16,0 mA Tamb (°C) HEC VDD V VOH V VOL V −55 SYMBOL +25 MIN. MAX. MIN. MAX. Output current HIGH HIGH Output current LOW January 1995 5 4,6 10 9,5 15 13,5 5 2,5 1,25 −IOH 4,75 0,4 10 0,5 15 1,5 +125 MIN. MAX. 1,0 0,6 mA 4,0 3,2 2,1 mA 12,5 10,0 6,7 mA −IOH 4,0 3,2 2,1 mA 3,6 2,9 1,9 mA IOL 12,5 10,0 6,7 mA 25,0 20,0 13,0 mA 3 Philips Semiconductors Product specification HEF40097B buffers 3-state hex non-inverting buffer AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays In → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 ns 60 ns + (0,20 ns/pF) CL 60 ns 26 ns + (0,08 ns/pF) CL 25 50 ns 22 ns + (0,06 ns/pF) CL 60 120 ns 45 ns + (0,30 ns/pF) CL 25 50 ns 19 ns + (0,13 ns/pF) CL 20 40 ns 16 ns + (0,09 ns/pF) CL 30 60 ns 15 ns + (0,30 ns/pF) CL 30 ns 10 ns + (0,11 ns/pF) CL 10 20 ns 7 ns + (0,07 ns/pF) CL 35 70 ns 10 ns + (0,50 ns/pF) CL 20 40 ns 8 ns + (0,24 ns/pF) CL 15 15 30 ns 6 ns + (0,18 ns/pF) CL 5 45 95 ns 35 70 ns 5 10 tTHL 15 5 LOW to HIGH 140 30 15 Output transition times HIGH to LOW 70 10 tTLH 3-state propagation delays Output disable times EO2, EO4 → On HIGH LOW 10 tPHZ 15 30 60 ns 5 60 120 ns 35 70 ns 15 25 55 ns 5 75 150 ns 10 tPLZ Output enable times EO2, EO4 → On HIGH LOW 10 35 70 ns 30 60 ns 5 95 190 ns 40 80 ns 30 65 ns 10 15 VDD V Dynamic power tPZH 15 5 tPZL TYPICAL FORMULA FOR P (µW) 5 400 fi + ∑ (foCL) × VDD2 dissipation per 10 25 200 fi + ∑ (foCL) × package (P) 15 96 500 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4