TI1 LM1771SMM Low-voltage synchronous buck controller Datasheet

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LM1771
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LM1771 Low-Voltage Synchronous Buck Controller With Precision Enable and No
External Compensation
1 Features
3 Description
•
•
•
•
•
•
•
•
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The LM1771 device is an efficient synchronous buck
switching controller with a precision enable requiring
no external compensation. The constant ON-time
control scheme provides a simple design free of
compensation
components,
allowing
minimal
component count and board space. The precision
enable pin allows flexibility in sequencing multiple
rails and setting UVLO. The LM1771 also
incorporates a unique input feedforward to maintain a
constant frequency independent of the input voltage.
The LM1771 is optimized for a low-voltage input
range of 2.8 V to 5.5 V and can provide an adjustable
output as low as 0.8 V. Driving an external high-side
PFET and low-side NFET, it can provide efficiencies
as high as 95%.
1
Input Voltage Range of 2.8 V to 5.5 V
0.8-V Reference Voltage
Precision Enable
No Compensation Required
Constant Frequency Across Input Range
Low Quiescent Current of 400 µA
Internal Soft-Start
Short Circuit Protection
6-Pin WSON Package and 8-Pin VSSOP Package
2 Applications
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Simple-to-Design, High-Efficiency, Step-Down
Switching Regulators
FPGAs, DSPs, and ASIC Power Supplies
Set-Top Boxes
Cable Modems
Printers
Digital Video Recorders
Servers
Graphic Cards
Three versions of the LM1771 are available
depending on the switching frequency desired for the
application. Nominal switching frequencies are in the
range of 100 kHz to 1000 kHz.
Device Information(1)
PART NUMBER
LM1771
PACKAGE
BODY SIZE (NOM)
WSON (6)
3.00 mm × 3.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
VIN
VIN
EN
HG
EN
LM1771
VOUT
LG
FB
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM1771
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 21
10.3 Thermal Considerations ........................................ 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision B (April 2013) to Revision C
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 22
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5 Pin Configuration and Functions
NGG Package
6-Pin WSON
Top View
FB
1
GND
2
HG
3
DAP
6
EN
5
VIN
4
LG
DGK Package
8-Pin VSSOP
Top View
1
2
FB
EN
GND
VIN
GND
VIN
3
4
HG
8
LG
7
6
5
Pin Functions
PIN
NAME
TYPE (1)
DESCRIPTION
WSON
VSSOP
DAP
—
—
GND
EN
6
8
I
Enable Pin
FB
1
1
A
Feedback Pin
GND
2
2, 3
GND
HG
3
4
AO
PFET Gate Drive
LG
4
5
AO
NFET Gate Drive
VIN
5
6, 7
PWR
(1)
Die Attach Pad is internally connected to GND, but it cannot be used as the
primary GND connection
Ground
Input Supply
I = Input, A = Analog, GND = Ground, AO = Analog output, PWR = Power
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See
MIN
MAX
UNIT
VIN
–0.3
6
V
EN, FB, HG, LG
–0.3
Junction temperature
Lead temperature
Soldering, 10 sec
Storage temperature, Tstg
(1)
(2)
–65
VIN
V
150
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
V(ESD)
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Electrostatic discharge
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VIN to GND
Junction temperature, TJ
MAX
UNIT
2.8
5.5
V
−40
125
°C
6.4 Thermal Information
LM1771
THERMAL METRIC (1)
NGG (WSON)
DGK (VSSOP)
6 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
52.8
169.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.4
59.7
°C/W
RθJB
Junction-to-board thermal resistance
27.2
89.3
°C/W
ψJT
Junction-to-top characterization parameter
0.7
7.0
°C/W
ψJB
Junction-to-board characterization parameter
27.3
87.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.4
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Specifications are for TJ = 25°C. All maximum and minimum limits apply over the full junction temperature range (−40°C to
+125°C), unless otherwise specified. Minimum and maximum limits are ensured through test, design or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. Unless
otherwise specified, VIN = 3.3 V.
PARAMETER
VFB
Feedback pin voltage
IQ
Quiescent current
TON
TEST CONDITIONS
0.782
VFB = 0.9 V
Switch ON-time
TOFF_MIN
MIN
Minimum OFF-time
TYP
MAX
0.8
0.818
V
400
700
µA
LM1771S - (500 ns)
0.4
0.5
0.6
LM1771T - (1000 ns)
0.8
1
1.2
LM1771U - (2000 ns)
1.6
2
2.4
LM1771S - (500 ns)
150
250
LM1771T - (1000 ns)
135
225
LM1771U - (2000 ns)
120
220
TD
Gate drive dead-time
VIH_EN
EN pin rising threshold
VEN_HYS
EN pin hysteresis
IFB
Feedback pin bias current
VFB = 0.9 V
VUVLO
Undervoltage lockout
VIN Rising Edge
VUVLO_HYS
Undervoltage lockout hysteresis
VSC_TH
Feedback pin short circuit latch
threshold
UNIT
70
1.15
ns
ns
1.2
1.25
V
50
200
mV
50
2.65
nA
2.8
50
0.42
µs
0.55
V
mV
0.65
V
RDS(ON)
1
HG FET driver pullup ON-resistance
IHG = 20 mA
4
Ω
RDS(ON)
2
HG FET driver pulldown ON-resistance
IHG = 20 mA
6
Ω
3
LG FET driver pullup ON-resistance
ILG = 20 mA
4
Ω
4
LG FET driver pulldown ON-resistance
ILG = 20 mA
6
Ω
RDS(ON)
RDS(ON)
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6.6 Typical Characteristics
All curves taken at VIN = 3.3 V with configuration in typical application circuit shown in Typical Applications. TJ = 25°C, unless
otherwise specified.
6
Figure 1. TON vs VIN (LM1771S)
Figure 2. TON vs VIN (LM1771T)
Figure 3. TON vs VIN (LM1771U)
Figure 4. TON vs Temperature (LM1771S)
Figure 5. TON vs Temperature (LM1771T)
Figure 6. TON vs Temperature (LM1771U)
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Typical Characteristics (continued)
All curves taken at VIN = 3.3 V with configuration in typical application circuit shown in Typical Applications. TJ = 25°C, unless
otherwise specified.
Figure 7. TOFF vs Temperature (LM1771S)
Figure 8. TOFF vs Temperature (LM1771T)
Figure 9. TOFF vs Temperature (LM1771U)
Figure 10. Feedback Voltage vs Temperature
Figure 11. VEN Threshold vs Temperature
Figure 12. Short-Circuit Threshold vs Temperature
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Typical Characteristics (continued)
All curves taken at VIN = 3.3 V with configuration in typical application circuit shown in Typical Applications. TJ = 25°C, unless
otherwise specified.
Figure 13. Quiescent Current vs Temperature
VIN = 5 V
VOUT = 1.8 V
FSW = 545 kHz
Figure 14. Dead-Time vs Temperature
VIN = 5 V
Figure 15. Efficiency vs IOUT (LM1771T)
VIN = 5 V
VOUT = 3.3 V
FSW = 500 kHz
FSW = 379 kHz
Figure 16. Efficiency vs IOUT (LM1771U)
VIN = 5 V
Figure 17. Efficiency vs IOUT (LM1771U)
8
VOUT = 2.5 V
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VOUT = 1.2 V
FSW = 727 kHz
Figure 18. Efficiency vs IOUT (LM1771S)
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7 Detailed Description
7.1 Overview
The LM1771 synchronous buck controller has a control scheme that is referred to as adaptive ON-time control.
This topology relies on a fixed switch ON-time to regulate the output voltage. This ON-time is internally set by
EEPROM and is available with three different set-points to allow for different frequency options. The LM1771
automatically adjusts the ON-time during operation inversely with the input voltage (VIN) to maintain a constant
frequency. Therefore the switching frequency during continuous conduction mode is independent of the inductor
and capacitor size unlike hysteretic switchers.
At the beginning of the cycle, the LM1771 turns on the high-side PFET for a fixed duration. This ON-time is
predetermined (internally set by EEPROM and adjusted by VIN) and the switch does not turn off until the timer
has completed its period. The PFET then turns off for a minimum predetermined time period. This minimum TOFF
of 150 ns is internally set and cannot be adjusted. This is to prevent false triggering from occurring on the
comparator due to noise from the SW node transition. After the minimum TOFF period has expired, the PFET
remains off until the comparator trip-point has been reached. Upon passing this trip-point (set at 0.8 V at the
feedback pin), the PFET turns back on and the process repeats, thus regulating the output.
The NFET control is complementary to the PFET control with the exception of a short dead-time to prevent
shoot-through from occurring.
7.2 Functional Block Diagram
LM1771
VIN
ON TIMER
Vin
Q
UVLO
OFF TIMER
SD
Q
0.8V
Level Shift
and
Shoot
Through
Protection
R Q
S
FB
Q
REGULATION
COMPARATOR
0.55 V
High-Side
Driver
Low-Side
Driver
HG
LG
SD
UVLO
SHORT
CIRCUIT
PROTECTION
R Q
S
/Soft-Start
Q
EN
1.2 V
ENABLE
COMPARATOR
GND
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7.3 Feature Description
7.3.1 Timing Opinion
Three versions of the LM1771 are available each with a predetermined TON set internally by EEPROM. This TON
setting determines the switching frequency for the application. Derivation and calculation of the dependence of
the switching frequency on VIN and TON is shown in Equation 1 through Equation 6.
In a PWM buck switcher, Equation 1, Equation 2, and Equation 3 can be manipulated to obtain the switching
frequency. Equation 1 shows the standard duty-cycle equation given by the volts-seconds balance on the
inductor with Equation 2 and Equation 3 defining standard relationships:
D=
VOUT
VIN
TON = D x TP
(1)
(2)
1
fSW
(3)
TP =
Using these equations and solving for duty-cycle for Equation 4:
D = fSW x TON
(4)
Frequency can now be expressed in Equation 5:
F=
VOUT
VIN x TON
(5)
Or simply written as Equation 6:
fSW =
VOUT
D
where
•
α = VIN x TON
(6)
To maintain a set frequency in an application, α is always held constant by varying TON inversely with VIN. The
three versions of the LM1771 are identified by the ON-times at a VIN of 3.3 V for consistency. For clarification,
see Table 1.
Table 1. Timing for All Variants
Product ID
TON at 3.3 V
α (V µs)
LM1771S
0.5 µs
1.65
LM1771T
1.0 µs
3.3
LM1771U
2.0 µs
6.6
The variation of TON versus VIN can also be expressed graphically. These graphs can be found in the Typical
Characteristics of the data sheet.
With α being a constant regardless of the version of the LM1771 used, Equation 6 shows that the only
dependent variable remaining is VOUT. Because VOUT is a constant in any application, the frequency also remains
constant. The switching frequency at which the application runs depends upon the VOUT desired and the LM1771
version chosen. For any VOUT, three frequency options (LM1771 versions) can be selected. This can be seen
Table 2. The recommended frequency range of operation is 100 kHz to 1000 kHz.
10
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Table 2. Frequency vs VOUT for Variants
VOUT
(1)
TIMING OPTIONS
(1)
500 ns
1000 ns
2000 ns
0.8
485
242
121
1
606
303
152
1.2
727
364
182
1.5
909
455
227
1.8
1091
545
273
2.5
1515
758
379
3.3
2000
1000
500
Switching Frequency (kHz) of LM1771 based on output voltage and
timing option.
7.3.2 Short-Circuit Protection
The LM1771 has an internal short-circuit comparator that constantly monitors the feedback node (except during
soft-start). If the feedback voltage drops below 0.55 V (equivalent to the output voltage dropping below 68% of
nominal), the comparator trips causing the part to latch off. The LM1771 does not resume switching until the
input voltage is taken below the UVLO threshold and then brought back into its normal operating range, or the
part is disabled then re-enabled through the enable pin. The purpose of this function is to prevent a severe short
circuit from causing damage to the application. Due to the fast transient response of the LM1771 a severe short
on the output causing the feedback to drop would only occur if the load applied had an effective resistance that
approaches the PMOS RDS(ON).
7.3.3 Precision Enable
The LM1771 features a precision enable circuit. If the voltage on the EN pin is 1.2 V or greater, the part is
enabled and switching occurs. If the enable voltage falls below 1.2 V, the part is placed into a shutdown state
and the drivers is tri-stated. This allows the LM1771 to be easily sequenced using a resistive divider from the
output of another regulator, or the working input voltage range of the LM1771 to be set using a resistive divider
on VIN. There is no internal pullup connected to the EN pin, so an external signal is required to initiate switching.
NOTE
When power is first applied to the LM1771, there is a slight delay before the enable
comparator is functional. During this delay, typically on the order of 400 µs, the part is
disabled regardless of the voltage on the EN pin. The falling enable threshold features 50
mV of hysteresis
7.3.4 Soft-Start
To limit in-rush current and allow for a controlled start-up the LM1771 incorporates an internal soft-start scheme.
Every time the enable voltage rises above 1.2 V while VIN is greater than the UVLO threshold, the LM1771 goes
through an adaptive soft-start that limits the ON-time and expands the minimum OFF-time. In addition the part
only activates the PMOS allowing a discontinuous mode of operation enabling a prebiased start-up. The time
spent in soft-start depends on the load applied to the output, but is usually close to a set time that is dependent
on the timing option. The approximate soft-start time can be seen in Table 3 for each timing option.
Table 3. Soft-Start Timing for All Variants
PRODUCT ID
TIMING
TSS
LM1771S
0.5 µs
1 ms
LM1771T
1.0 µs
1.2 ms
LM1771U
2.0 µs
1.8 ms
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Therefore, if the input supply is extremely slow rising such that at the end of soft-start the input voltage is still
near the UVLO threshold, a timing option must be chosen to ensure that maximum duty-cycle permits the output
to meet the minimum condition. TI recommends using the 2000-ns option (LM1771U) in conditions where the
output voltage is 2.5 V or greater to avoid false latch-offs when there is concern regarding the input supply slew
rate.
NOTE
As soon as soft-start terminates the short-circuit protection is enabled. This means that if
the output voltage does not reach at least 68% of its final value the part latches off.
In some situations, the internal soft-start routine can create a slight overshoot on the output voltage. If this must
be avoided, the use of a feedforward capacitor as detailed in the Feedforward Capacitor section.
7.3.5 Jitter
The LM1771 uses an adaptive ON-time control scheme that relies on the output voltage ripple to provide a
consistent switching frequency. Under certain conditions, excessive noise can couple onto the feedback pin
causing the switch node to appear to have a slight amount of jitter. This is not indicative of an unstable design.
The output voltage still regulates to the exact same value. Careful component selection and layout must minimize
any external influence.
In addition to any external noise that can add to the jitter seen on the switch node, the LM1771 always has a
slight amount of switch jitter. This is because the LM1771 makes a small alteration in the reference voltage every
128 cycles to improve its accuracy and long-term performance. This has the effect of causing a change in the
switching frequency at that instant. When viewed on an oscilloscope this can be seen as a jitter in the switch
node. The change in feedback voltage or output voltage, however, is almost indistinguishable.
7.4 Device Functional Modes
The LM1771 has essentially one normal operational mode: in normal operation, the part operates in full
synchronous mode to regulate the FB input to 0.8 V (typical) after soft-start period is over. The EN pin allows the
user to shut down the part. When the part is enabled, the IC enters soft-start for 1 ms to 1.8 ms depending on
the variant of the IC. See Soft-Start for more detail on the soft-start pattern.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Design Guide details the design procedure to follow for the typical application. Because of the nature of constant
ON-time controller, a certain degree of iteration might be necessary on the sizing of some key components to
achieve optimal response, such as the inductor L1.
8.2 Typical Applications
8.2.1 LM1771 Typical Application
VIN
CIN
VIN
EN
HG
EN
Q1
L1
LM1771
VOUT
LG
Q2
RSNS
CFF
RFB1
COUT
FB
RFB2
GND
Figure 19. Example Circuit Schematic
8.2.1.1 Design Requirements
The main parameters needed to successfully design an application based on the LM1171 are typical of buck
DC–DC converters. The input and output voltage must be known as well as the worst-case input voltage
operating conditions. The maximum output current helps the designer size the inductor appropriately. In addition,
the designer needs to be aware of the requirement on the output capacitor to achieve stable operation. See
Output Capacitor for details on the output capacitor requirements.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Design Guide
As with any DC–DC converter, numerous trade-offs are possible to optimize the design for efficiency, size, or
performance. These are taken into account and highlighted throughout this discussion.
Equation 7 calculates for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs
and parasitic resistances it can be approximated by:
D=
VOUT
VIN
(7)
A more accurate calculation for duty-cycle can be used that takes into account the voltage drops across the
FETs. Equation 8 determines the slight load dependency on switch frequency if needed. Otherwise the simplified
equation works well for component calculation.
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Typical Applications (continued)
D=
VOUT + VDS_NMOS
VIN + VDS_NMOS + VDS_PMOS
(8)
8.2.1.2.1.1 Frequency Selection
The LM1771 is available with three preset timing options that select the ON-time and hence determine the
switching frequency of the application. Increasing the switching frequency has the effect of reducing the inductor
size needed for the application while requiring a slight trade-off in efficiency. Table 4 shows the same frequency
table as shown earlier (Table 2) with the exception that the recommended timing option for each VOUT is
highlighted. TI does not recommend using a high switching frequency with VOUT equal to or greater than 2.5 V
due to the maximum duty-cycle limitations of the device coupled with the internal start-up.
Table 4. Recommended Switching Frequency vs VOUT
VOUT
(1)
TIMING OPTIONS
(1)
500 ns
1000 ns
2000 ns
0.8
485
242
-
1
606
303
-
1.2
727
364
-
1.5
909
455
2237
1.8
-
545
273
2.5
-
-
379
3.3
-
-
500
Recommended switching frequency (kHz) based on output voltage
and timing option.
8.2.1.2.1.2 Inductor Selection
The inductor selection is an iterative process likely requiring several passes before settling on a final value. The
reason for this is because it influences the amount of ripple seen at the output, a critical component to ensure
general stability of an adaptive ON-time circuit. For the first pass at inductor selection the value can be obtained
by targeting a maximum peak-to-peak ripple current equal to 30% of the maximum load current. The inductor
current ripple (ΔIL) can be calculated by Equation 9:
'IL =
(VIN ± VOUT) x D
L x fSW
(9)
Therefore, L can be initially set by applying the 30% rule in Equation 10:
L=
(VIN ± VOUT) x D
0.3 x fSW x IOUT
(10)
The other features of the inductor that can be selected besides inductance value are saturation current and core
material. Because the LM1771 does not have a current limit, TI recommends having a saturation current higher
than the maximum output current to handle any ripple or momentary overcurrent events. The core material also
influences the saturation characteristics as ferrite materials have a hard saturation curve and take care that they
never saturate during normal use. A shielded inductor or low-profile unshielded inductor is recommended to
reduce EMI. This also helps prevent any spurious noise from picking up on the feedback node resulting in
unexpected tripping of the feedback comparator.
8.2.1.2.1.3 Output Capacitor
One of the most important components to select with the LM1771 is the output capacitor. This is because its size
and ESR have a direct effect on the stability of the loop. A constant ON-time control scheme works by sensing
the output voltage ripple and switching the FETs appropriately. The output voltage ripple on a buck converter can
be approximated by stating that the AC inductor ripple flows entirely into the output capacitor and is created by
the ESR of the capacitor. This can be expressed in Equation 11:
ΔVOUT = ΔIL x RESR
14
(11)
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To ensure stability, two constraints need to be met. The first is that there is sufficient ESR to create enough
voltage ripple at the feedback pin. TI recommends having at least 10 mV of ripple seen at the feedback pin. This
can be calculated by multiplying the output voltage ripple by the gain seen through the feedback resistors. This
gain, H, can be calculated in Equation 12:
H=
VFB
VOUT
=
0.8V
VOUT
(12)
If the output voltage is fairly high, causing significant attenuation through the feedback resistors, a feedforward
capacitor can be used. This is actually recommended for most circuits as it improves performance. See the
Feedforward Capacitor section for more details.
The second criteria is to ensure that there is sufficient ripple at the output that is in-phase with the switch. The
problem exists that there is actually ripple caused by the capacitor charging and discharging, not only the ESR
ripple. Because these are effectively out of phase, problems can exist. To avoid this issue, TI recommends that
the ratio of the two ripples (β) is always greater than 5. To calculate the minimum ESR value needed,
Equation 13 can be used:
§
¨
©
'IL2
ICIN_RMS = IOUT D §¨1 - D +
©
12 x IOUT2
(13)
In general, the best capacitors to use are chemistries that have a known and consistent ESR across the entire
operating temperature range. Tantalum capacitors or similar chemistries such as Niobium Oxide perform well
along with certain families of Aluminum Electrolytics. Small value POSCAPs and SP CAPs also work as they
have sufficient ESR. When used in conjunction with a low-value inductor it is possible to have an extremely
stable design. The only capacitors that require modification to the circuit are ceramic capacitors. Ceramic
capacitors cause problems meeting both criteria because they have low ESR and low capacitance. Therefore, if
they are to be used, an external ESR resistor (RSNS) must be added. This can be seen in Figure 20.
VIN
CIN
VIN
EN
HG
EN
Q1
L1
LM1771
RSNS
VOUT
COUT
LG
Q2
CFF
RFB1
FB
RFB2
GND
Figure 20. LM1771 With an External ESR Resistor (RSNS)
This circuit uses an additional resistor in series with the inductor to add ripple at the output. It is placed in this
location and used in combination with the feedforward capacitor (CFF) to provide ripple to the feedback pin,
without adding ripple or a DC offset to the output. The benefit of using a ceramic capacitor is still obtained with
this technique. Because the addition of the resistor results in power loss, this circuit implementation is only
recommended for low currents (2 A and below). The power loss and rating of the resistor must be taken into
account when selecting this component.
This circuit implementation using the feedforward capacitor begins to experience limitations when the output
voltage is small. Previously the circuit relied on the CFF for all the ripple at the feedback node by assuming that
the resistor divider was negligible. As VOUT decreases this can not be assumed. The resistor divider contributes a
larger amount of ripple which is problematic as it is also out of phase. Therefore the resistor location must be
changed to be in series with the output capacitor. This can be viewed as adding an effective ESR to the output
capacitor. This can be seen in Figure 21.
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VIN
CIN
VIN
EN
HG
EN
Q1
L1
LM1771
VOUT
LG
Q2
RSNS
RFB1
COUT
FB
RFB2
GND
Figure 21. LM1771 With ESR Resistor (RSNS) in Series With Output Capacitor
8.2.1.2.1.4 Feedforward Capacitor
The feedforward capacitor is used across the top feedback resistor to provide a lower impedance path for the
high-frequency ripple without degrading the DC accuracy. Typically the value for this capacitor must be small
enough to prevent load transient errors because of the discharging time, but large enough to prevent attenuation
of the ripple voltage. In general a small ceramic capacitor in the range of 1 nF to 10 nF is sufficient.
If CFF is used then it can be assumed that the ripple voltage seen at the feedback pin is the same as the ripple
voltage at the output. The attenuation factor H no longer needs to be used. However, in these conditions, TI
recommends having a minimum of 20-mV ripple at the feedback pin. The use of a CFF capacitor is recommended
as it improves the regulation and stability of the design. However, its benefit is diminished as VOUT starts
approaching VREF , therefore it is not needed in this situation.
8.2.1.2.1.5 Input Capacitor
The dominating factor that usually sets the size of an input capacitor is the current handling ability. This is usually
determined by the package size and ESR of the capacitor. If these two criteria are met then there usually must
be enough capacitance to prevent impedance interactions with the source. In general, TI recommends using a
ceramic capacitor for the input as they provide a low impedance and small footprint.
NOTE
Use a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better
over temperature performance and also minimize the DC voltage derating that occurs on
Y5V capacitors.
To calculate the input capacitor RMS current, Equation 14 can be used:
§
¨
©
'IL2
ICIN_RMS = IOUT D §¨1 - D +
©
12 x IOUT2
(14)
which can be approximated by, Equation 15
ICIN_RMS = IOUT x
D(1 - D)
(15)
8.2.1.2.2 MOSFET Selection
The two FETs used in the LM1771 requires attention to selection of parameters to ensure optimal performance of
the power supply. The high-side FET must be a PFET and the low-side an NFET. These can be integrated in
one package or as two separate packages.
16
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8.2.1.2.2.1 VDS Voltage Rating
The first selection criteria is to select FETs that have sufficient VDS voltage ratings to handle the maximum
voltage seen at the input plus any transient spikes that can occur from parasitic ringing. In general most FETs
available for this application have ratings from 8 V to 20 V. If a larger voltage rating is used then the performance
is most likely be degraded because of higher gate capacitance.
8.2.1.2.2.2 RDSON
The RDS(ON) specification is important as it determines several attributes of the FET and the overall power supply.
The first is that it sets the maximum current of the FET for a given package. A lower RDS(ON) permits a higher
allowable current and reduce conduction losses, however, it increases the gate capacitance and the switching
losses.
8.2.1.2.2.3 Gate Drive
The next step is to ensure that the FETs are capable of switching at the low Vin supplies used by the LM1771.
The FET must have the Rdson specified at either 1.8 V or 2.5 V to ensure that it can switch effectively as soon
as the LM1771 starts up.
8.2.1.2.2.4 Gate Charge
Because the LM1771 uses a fixed dead-time scheme to prevent cross conduction, the FET transitions must
occur in this time. The rise and fall time of the FETs gate can be influenced by several factors including the gate
capacitance. Therefore the total gate charge of both FETs must be limited to less than 20 nC at 4.5 V VGS. The
lower the number the faster the FETs must switch and the better the efficiency.
8.2.1.2.2.5 Rise and Fall Times
A better indication of the actual switching times of the FETs can be found in their Electrical Characteristics table.
The rise and fall time must be specified and selected to be at a minimum. This helps improve efficiency and
ensuring that shoot-through does not occur.
8.2.1.2.2.6 Gate Charge Ratio
Another consideration in selecting the FETs is to pay attention to the Qgd / Qgs ratio. The reason for this is that
proper selection can prevent spurious turnon. If we look at the NFET for example, when the FET is turning off,
the gate signal pulls to ground. Conversely the PFET is turning on, causing the SW node to rise towards VIN. The
gate-to-drain capacitance of the NFET couples the SW node to the gate and causes it to rise. If this voltage is
excessive, then it could weakly turn on the low-side FET causing an efficiency loss. However, this coupling is
mitigated by having a large gate to source capacitance of the FET, which helps to hold the gate voltage down.
Ideally, a very low Qgd / Qgs would be ideal, but in practice it is common to find the number around 1. As a
general rule, the lower the ratio, the better.
If the above selection criteria have been met it is useful to generate a figure of merit to allow comparison
between the FETs. One such method is to multiply the RDS(ON) of the FET by the total gate charge. This allows
an easy comparison of the different FETs available. Once again, the lower the product, the better.
8.2.1.2.2.7 Feedback Resistors
The feedback resistors are used to scale the output voltage to the internal reference value such that the loop can
be regulated. The feedback resistors must not be made arbitrarily large as this creates a high impedance node at
the feedback pin that is more susceptible to noise. A combined value of 50 kΩ for the two resistors is adequate.
To calculate the resistor values use Equation 16. Typically, the low-side resistor is initially set to a predetermined
value such as 10 kΩ.
§
¨
©
RFB1 = RFB2
§ VOUT
-1
¨
© VFB
where
•
VFB is the internal reference voltage that can be found in the Electrical Characteristics table or approximated
by 0.8 V
(16)
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The output voltage value can be set in a precise manner by taking into account the fact that the reference
voltage is regulating the bottom of the output ripple as opposed to the average value. This relationship is shown
in Figure 22.
VOUT
'VOUT
VOUT_ACTUAL
VOUT_SET
Figure 22. Output Voltage Waveform
The average output voltage (VOUT_ACTUAL) is higher than the output voltage (VOUT_SET) that was calculated by the
earlier equation by exactly half the output voltage ripple. The output voltage that is targeted for regulation may
then be appended according to the voltage ripple. This can be seen in Equation 17:
VOUT_ACTUAL= VOUT_SET + ½ΔVOUT = VOUT_SET + ½ΔIL x RESR
(17)
8.2.1.2.3 Efficiency Calculations
One of the most important parameters to calculate during the design stage is the expected efficiency of the
system. This can help determine optimal FET selection and can be used to calculate expected temperature rise
of the individual components.
8.2.1.2.3.1 Quiescent Current
The quiescent current consumed by the LM1771 is one of the major sources of loss within the controller.
However, from a system standpoint this is usually less than 0.5% of the overall efficiency. Therefore, it could
easily be omitted but is shown for completeness:
PIQ = VIN x IQ
(18)
8.2.1.2.3.2 Conduction Loss
There are three losses associated with the external FETs. From the DC standpoint there is the I-squared R loss,
caused by the ON-resistance of the FET. This can be modeled for the PMOS by:
PP_COND = D x RDSON_PMOS x IOUT2
(19)
and the NMOS by:
PN_COND = (1 - D) x RDSON_NMOS x IOUT2
(20)
8.2.1.2.3.3 Switching Loss
The next loss is the switching loss that is caused by the need to charge and discharge the gate capacitance of
the FETs every cycle. This can be approximated by:
PP_SWITCH = VIN x Qg_PMOS x fSW
(21)
for the PMOS, and the same approach can be adapted for the NMOS:
PN_SWITCH = VIN x Qg_NMOS x fSW
(22)
8.2.1.2.3.4 Transitional Loss
The last FET power loss is the transitional loss. This is caused by switching the PMOS while it is conducting
current. This approach only models the PMOS transition, the NMOS loss is considered negligible because it has
minimal drain to source voltage when it switches due to the conduction of the body diode. Therefore the
transitional loss of the PMOS can be modeled by:
PP_TRANSITIONAL = 0.5 x VIN x IOUT x fSW x (tr + tf)
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tr and tf are the rise and fall times of the FET and can be found in their corresponding datasheet. Typically these
numbers are simulated using a 6-Ω drive, which corresponds well to the LM1771. Given this, no adjustment is
needed.
8.2.1.2.3.5 DCR Loss
The last source of power loss in the system that needs to be calculated is the loss associated with the inductor
resistance (DCR) which can be calculated by Equation 24:
PDCR = RDCR x IOUT2
(24)
8.2.1.2.3.6 Efficiency
The efficiency, η, can then be calculated by summing all the power losses and then using Equation 25:
K=
POUT
POUT + PLOSSES
(25)
8.2.1.3 Application Curve
Figure 23. Typical Efficiency 5 VIN to 2.5 VOUT
8.2.2 Example Application 5 VIN to 1.8 VOUT
Figure 24 and Table 5 show an application with conversion from 5-V input to 1.8-V output with a switching
frequency of 1.1 MHz and a 2-A maximum output current.
VIN
CIN
VIN
EN
HG
EN
Q1
L1
LM1771
VOUT
LG
Q2
RSNS
CFF
RFB1
COUT
FB
RFB2
GND
Figure 24. Example Circuit Schematic, 5 VIN to 1.8 VOUT
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Table 5. Bill of Materials (5-V to 1.8-V Conversion, fSW = 1090 kHz, IOUT = 2 A)
DESIGNATOR
DESCRIPTION
PART NUMBER
QUANTITY
VENDOR
U1
LM1771, 500 ns
LM1771S
1
Texas Instruments
Q1
PMOS
Si3867DV
1
Siliconix
Q2
NMOS
Si3460DV
1
Siliconix
CIN
22-μF Capacitor, 0805
GRM21BR60J226ME39
1
Murata
COUT
100-μF Capacitor, 6.3 V, 100 mΩ
TPSY107M006R0100
1
AVX
RFB1
12.4-kΩ Resistor, 0603
CRCW06031242F
1
Vishay
RFB2
10-kΩ Resistor, 0603
CRCW06031002F
1
Vishay
CFF
1-nF Capacitor, 0603
VJ0603102KXXA
1
Vishay
3.3-μH Inductor
MSS7341-332NLB
1
Coilcraft
L
8.2.3 Example Application 5 VIN to 3.3 VOUT
Figure 25 and Table 6 show an application with conversion from 5-V input to 3.3-V output with a switching
frequency of 500 kHz and a 5-A maximum output current.
VIN
CIN
VIN
EN
Q1
HG
EN
L1
LM1771
VOUT
Q2
LG
RSNS
CFF
RFB1
COUT
FB
RFB2
GND
Figure 25. Example Circuit Schematic, 5 VIN to 3.3 VOUT
Table 6. Bill of Materials (5-V to 3.3-V Conversion, fSW = 500 kHz, IOUT = 5 A)
DESIGNATOR
DESCRIPTION
PART NUMBER
QUANTITY
VENDOR
U1
LM1771, 200 ns
LM1771U
1
Texas Instruments
Q1
PMOS
Si9433BDY
1
Siliconix
Q2
NMOS
Si4894DY
1
Siliconix
CIN
100-μF Capacitor, 1812
GRM43SR60J107ME20B
1
Murata
COUT
150-μF Capacitor, 6.3 V, 70 mΩ
NOSD157M006R0070
1
AVX
RFB1
29.4-kΩ Resistor, 0805
CRCW08052942F
1
Vishay
RFB2
10-kΩ Resistor, 0805
CRCW08051002F
1
Vishay
CFF
1-nF Capacitor, 0805
VJ0805102KXXA
1
Vishay
2.2-μH Inductor
DO3316P-222
1
Coilcraft
L
9 Power Supply Recommendations
The power line feeding the LM1771 must have low impedance. The input capacitor of the system must be placed
as close to VIN as possible. If the power supply is very noisy, an additional bulk capacitor might be necessary in
the system to ensure that clean power is delivered to the IC.
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10 Layout
10.1 Layout Guidelines
The LM1771, like all switching regulators, requires careful attention to layout to ensure optimal performance. The
following steps must be taken to aid in the layout. For more information refer to Application Note AN-1299
(SNVA074).
1. Ensure that the ground connections of the input capacitor, output capacitor and NMOS are as close as
possible. Ideally these must all be grounded together in close proximity on the component side of the board.
2. Keep the switch node small to minimize EMI without degrading thermal cooling of the FETs.
3. Locate the feedback resistors close to the IC and keep the feedback trace as short as possible. Do not run
any feedback traces near the switch node.
4. Keep the gate traces short and keep them away from the switch node as much as possible.
5. If a small bypass capacitor is used on VIN (0.1 µF) place it as close to the pin, with the ground connection as
close to the chip ground, as possible.
10.2 Layout Examples
CIN and COUT GND are close together
Keep path of FET’s gate short
Feedback components are
close to the FB pin
Limit surface of switch node
to reduce capacitance
Figure 26. LM1771 Layout Example (Top)
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Layout Examples (continued)
Figure 27. LM1771 Layout Example (Bottom)
10.3 Thermal Considerations
By breaking down the individual power loss in each component it makes it easy to determine the temperature
rise of each component. Generally the expected temperature rise of the LM1771 is extremely low as it is not in
the power path. Therefore the only two items of concern are the PMOS and the NMOS. The power loss in the
PMOS is the sum of the conduction loss and transitional loss, while the NMOS only has conduction loss. It is
assumed that any loss associated with the body diode conduction during the dead-time is negligible.
For completeness of design it is important to watch out for the temperature rise of the inductor. Assuming the
inductor is kept out of saturation the predominant loss is the DC copper resistance. At higher frequencies,
depending on the core material, the core loss could approach or exceed the DCR losses. Consult with the
inductor manufacturer for appropriate temp curves based on current.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
User's Guide, AN-1299 LM5041 Evaluation Board, SNVA074
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
LM1771SMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM1771SSD/NOPB
ACTIVE
WSON
NGG
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM1771TMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM1771TSD/NOPB
ACTIVE
WSON
NGG
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM1771UMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM1771USD/NOPB
ACTIVE
WSON
NGG
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
SNRB
-40 to 125
1771S
SNSB
-40 to 125
1771T
SNTB
-40 to 125
1771U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM1771SMM/NOPB
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM1771SSD/NOPB
WSON
NGG
6
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LM1771TMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM1771TSD/NOPB
WSON
NGG
6
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LM1771UMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM1771USD/NOPB
WSON
NGG
6
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM1771SMM/NOPB
LM1771SSD/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
WSON
NGG
6
1000
210.0
185.0
35.0
LM1771TMM/NOPB
LM1771TSD/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
WSON
NGG
6
1000
210.0
185.0
35.0
LM1771UMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM1771USD/NOPB
WSON
NGG
6
1000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NGG0006A
SDE06A (Rev A)
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