IDT IDT73720A 16-bit tri-port bus exchanger Datasheet

16-BIT TRI-PORT
BUS EXCHANGER
IDT73720/A
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed 16-bit bus exchange for interbus communication in the following environments:
— Multi-way interleaving memory
— Multiplexed address and data busses
• Direct interface to R3051 family RISChipSet
— R3051 family of integrated RISController CPUs
— R3721 DRAM controller
• Data path for read and write operations
• Low noise 12mA TTL level outputs
• Bidirectional 3-bus architecture: X, Y, Z
— One CPU bus: X
— Two (interleaved or banked) memory busses:Y & Z
— Each bus can be independently latched
• Byte control on all three busses
• Source terminated outputs for low noise and undershoot
control
• 68-pin PLCC and 80-pin PQFP package
• High-performance CMOS technology.
The IDT73720/A Bus Exchanger is a high speed 16-bit bus
exchange device intended for inter-bus communication in
interleaved memory systems and high performance multiplexed address and data busses.
The Bus Exchanger is responsible for interfacing between
the CPU A/D bus (CPU address/data bus) and multiple
memory data busses.
The 73720/A uses a three bus architecture (X, Y, Z), with
control signals suitable for simple transfer between the CPU
bus (X) and either memory bus (Y or Z). The Bus Exchanger
features independent read and write latches for each memory
bus, thus supporting a variety of memory strategies. All three
ports support byte enable to independently enable upper and
lower bytes.
FUNCTIONAL BLOCK DIAGRAM
OEYL
8
LEXY
Y-WRITE
LATCH
Y0:7
16
Y8:15
8
8
LEYX
8
8
OEYU
Y-READ
LATCH
16
(Even Path)
8
16
OEXL
OEXU
OEXL
OEYU
OEYL
OEZU
OEZL
8
X0:7
X8:15
M
U
16 X
8
8
OEXU
8
PATH
T/R
BUS CONTROL
OEU
OEL
16
Z-READ
LATCH
LEZX
16
OEZL
8
8
16
LEXZ
Z-WRITE
LATCH
8
Z0:7
16
Z8:15
8
OEZU
(Odd Path)
2527 drw 01
Figure 1. 73720 Block Diagram
NOTE:
1. Logic equations for bus control:
OEXU = T/R* . OEU*; OEXL = T/R* . OEL*; OEYU = T/R . PATH . OEU*
OEYL = T/R . PATH . OEL*; OEZU = T/R . PATH* . OEU*; OEZL = T/R . PATH* .
OEL*
RISChipSet, RISController, R305x, R3051, R3052 are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1995 Integrated Device Technology, Inc.
AUGUST 1995
11.5
DSC-2046/6
1
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
X7
X6
X5
X4
X3
X2
X1
X0
GND
VCC
Z15
Z14
Z13
Z12
Z11
Z10
GND
PIN CONFIGURATIONS
9
8
7
6
10
11
5
4
3
2
1 68 67 66 65 64 63 62 61
60
Pin 1
Designator
12
59
58
13
57
14
56
15
55
16
54
17
53
J68-1
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
GND
VCC
LEXZ
OEL
LEXY
T/R
GND
GND
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
VCC
Y9
Y10
Y11
Y12
Y13
Y14
Y15
GND
X8
X9
X10
X11
X12
X13
X14
X15
GND
VCC
PATH
OEU
LEYX
LEZX
Y0
Y1
2527 drw 02
1
2
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
3
59
Pin 1
Designator
58
4
57
5
6
56
55
7
54
8
9
53
10
11
52
PQ80-1
51
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
GND
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
GND
VCC
LEXZ
OEL
LEXY
T/R
NC
NC
GND
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
VCC
Y9
Y10
Y11
Y12
Y13
Y14
Y15
NC
GND
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
NC
GND
NC
NC
X8
X9
X10
X11
X12
X13
X14
X15
GND
VCC
PATH
OEU
LEYX
LEZX
Y0
Y1
GND
NC
NC
GND
GND
X7
X6
X5
X4
X3
X2
X1
X0
GND
VCC
Z15
Z14
Z13
Z12
Z11
Z10
PLCC
TOP VIEW
PQFP
TOP VIEW
11.5
2527 drw 03
2
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal
X(0:15)
Y(0:15)
Z(0:15)
LEXY
I/O
I/O
I/O
I/O
I
Description
Bidirectional Data Port X. Usually connected to the CPU's A/D (Address/Data) bus.
Bidirectional Data port Y. Connected to the even path or even bank of memory.
Bidirectional Data port Z. Connected to the odd path or odd bank of memory.
Latch Enable input for Y-Write Latch. The Y-Write Latch is open when LEXY is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXY
LEXZ
I
Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXZ.
LEYX
I
Latch Enable input for the Y-Read Latch. The Y-Read Latch is open when LEYX is HIGH. Data from the even
path Y is latched on the HIGH-to-LOW transition of LEYX.
LEZX
I
Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is HIGH. Data from the odd
path Z is latched on the HIGH-to-LOW transition of LEZX
PATH
I
Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the Y-port (even
path). When LOW, PATH enables data transfer between the X-Port and the Z-Port (odd path).
T/R
I
Transmit/Receive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When LOW,
Port X is an output Port while Ports Y & Z are input Ports
OEU
I
Output Enable for Upper byte. When LOW, the Upper byte of data is transfered to the port specified by PATH in
the direction specified by T/R .
OEL
I
Output Enable for Lower byte. When LOW, the Lower byte of data is transfered to the port specified by PATH in
the direction specified by T/R .
2527 tbl 02
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, F = 1.0MHZ)
Symbol
Rating
Com’l.
Mil.
VTERM
Terminal Voltage
with Respect
to GND
Operating
Temperature
–0.5 to +7.0
–0.5 to +7.0
V
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
Power
Dissipation
–55 to +125
–65 to +125
°C
1.0
1.0
W
50
50
mA
TA
PT
IOUT
DC Output
Current
Unit
Symbol
CIN
COUT
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
8
12
Unit
pF
pF
NOTE:
2527 tbl 04
1. This parameter is guaranteed by device characterization, but is not production tested.
TRUTH TABLE
NOTE:
2527 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Path
L
T/R
L
OEU
OEL
L
L
Functionality
Z→X (16-bits)–Read Z(1)
L
H
L
L
X→Z (16 bits)–Write Z(1)
H
L
L
L
Y→X (16-bits)–Read Y(2)
H
H
L
L
X→Y (16 bits)–Write Y(2)
X
X
H
H
X
X
H
L
All output buffers are
disabled
Transfer of lower 8 bits
(0:7) as per PATH & T/R
X
X
L
H
Transfer of upper 8 bits
(8:15) as per PATH & T/R
NOTES:
2527 tbl 01
1. For Z→X and X→Z transfers, Y-port output buffers are tristated.
2. For Y→X and X→Y transfers, Z-port output buffers are tristated.
11.5
3
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
ARCHITECTURE OVERVIEW
The Bus Exchanger is used to service both read and write
operations between the CPU and the dual memory busses. It
includes independent data path elements for reads from and
writes to each of the memory banks (Y and Z). Data flow
control is managed by a simple set of control signals, analogous to a simple transceiver. In short, the Bus Exchanger
allows bidirectional communication between ports X and Y
and ports X and Z as illustrated in figure 1.
The data path elements for each port include:
Read Latch: Each of the memory ports Y and Z contains a
transparent latch to capture the contents of the memory bus.
Each latch features an independent latch enable.
Write Latch: Each memory port Y and Z contains an independent latch to capture data from the CPU bus during writes.
Each memory port write latch features an independent latch
enable, allowing write data to be directed to a specific memory
port without disrupting the other memory port.
Data Flow Control Signals
T/R (Transmit/Receive). This signal controls the direction
of data transfer. A transmit is used for CPU writes, and a
receive is used for read operations.
OEU, OEL are the output enable control signals to select
upper or lower bytes of all three ports.
Path: The path control signal is used to select between the
even memory path Y and the odd memory path Z during read
or write operations. Path selects the memory port to be
connected to the CPU bus (X-port), and is independent of the
latch enable signals. Thus, it is possible to transfer data from
one memory port to the CPU bus (X) while capturing data from
the other memory port.
MEMORY READ OPERATIONS
Latch Mode
In this mode the read operation consists of two stages.
During the first stage, the data present at the memory port is
captured by the read latch for that memory port. During a
subsequent stage, data is brought from a selected memory
port to the CPU A/D port X by using output enable control.
The read operation is selected by driving T/R LOW. The
read is managed using the Path input to select the memory
port (Y or Z); the LEYX/LEZX enable the data capture into the
corresponding Read Latch.
In this way, memory interleaving can be performed. While
data from one bank is output onto the CPU bus, data on the
other bank is captured in the other memory port. In the next
cycle, the Path input is changed, enabling the next data
element onto the CPU bus, while the first bank is presented
with a new data element.
Transparent Mode
The Bus Exchanger may be used as a data transceiver by
leaving all latches open or transparent.
Memory Write Operations
Memory write operations also consist of two distinct stages.
During one stage, the write data is captured into the selected
memory port write latch. During a later stage, the memory is
presented on the memory port bus
The write operation is selected by driving T/R HIGH. Writes
are thus performed using the Path input to select the memory
port (Y or Z). The LEXY/LEXZ capture data in the corresponding Write Latch.
Note that it is possible to utilize the bus exchanger’s write
resources as an additional write buffer, if desired; the CPU
A/D bus can be freed up once the data has been captured by
the Bus Exchanger.
APPLICATIONS
Use as Part of the R3051 Family ChipSet
Figure 2 shows the use of the Bus Exchanger in a typical
R3051 based system.
In write transactions, the R3051 drives data on the CPU
bus. The latch enables are held open through the entire write;
thus, the bus exchanger is used like a transceiver. The
appropriate LEXY/LEXZ signal is derived from ALE (Logic
LOW- indicating that the processor is driving data) and the low
order address bit. The rising edge of Wr from the CPU, ends
the write operation.
During read transactions, the memory system is responsible for generating the input control signals to cause data to
be captured at the memory ports. The memory controller is
also responsible for acknowledging back to the CPU that the
data is available, and causing the appropriate path to be
selected.
The R3721 DRAM controller for the R3051 family uses the
transparent latches of the read ports. The R3721 directly
controls the inputs of the bus exchanger, during both reads
and writes. Consult the R3721 data sheet for more information on these control signals.
Use in a general 32-bit System
Figures 3 and 4 illustrate the use of the Bus Exchanger in
a 32-bit microprocessor based system. Note the reduced pin
count achieved with the Bus Exchanger.
11.5
4
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
Clk2xIn
IDT R3051 FAMILY
RISController
ADDRESS/DATA
CONTROL
R305x
LOCAL BUS
IDT79R3721
DRAM
CONTROLLER
DRAM
DRAM
IDT73720
BUS EXCHANGER
(2)
Figure 2. Bus Exchanger Used in R3051 Family System
2527 drw 04
CPU
CPU
32
32
2 x (73720)
4 x (74FCT373)
DRAM 1
DRAM 2
DRAM 1
Address
DRAM 2
Address
Data Bus Chip Count = 2 Pin Count = 136
CPU
Data Bus Chip Count = 2 Pin Count = 136
CPU
32
4 x (74FCT373)
2 x (73720)
4 x (74FCT373)
4 x (74FCT245)
4 x (74FCT245)
DRAM 1
DRAM 2
32
4 x (74FCT373)
Address
4 x (74FCT543)
4 x (74FCT543)
DRAM 1
DRAM 2
Address
Data Bus Chip Count = 8 Pin Count = 160
Data Bus Chip Count = 8 Pin Count = 192
2527 drw 05
2527 drw 06
Figure 3. CPU System with Transparent Data Path
(2-way Interleaving)
Figure 4. CPU System with Latched Data Path
(2-way Interleaving)
11.5
5
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, TA = 0°C to +70°C)
Test Conditions(1)
Min.
2.0
—
—
—
—
—
Typ.(2)
—
—
—
—
—
—
Max.
—
0.8
5.0
5.0
–5.0
–5.0
Unit
V
V
µA
—
–60
2.4
—
–0.7
—
3.3
0.3
–1.2
–200
—
0.5
V
mA
V
V
VCC = 5V
—
200
—
mV
Quiescent Power
Supply Current
VCC = Max.
VIN = GND or VCC
—
0.2
1.5
mA
∆ICC
Quiescent Power
Supply Current
VCC = Max.
VIN =3.4 V(4)
—
0.5
2.0
mA/
Input
ICCD
Dynamic Power
Supply Current(5)
VCC = Max.
VIN = VCC or GND
Outputs Disabled
OE = VCC
One Input Toggling
50 % Duty Cycle
—
0.25
0.5
mA/
MHz
IC
Total Power Supply
Current(6)
VCC = Max.
VIN = VCC or GND
Outputs Disabled
50 % Duty Cycle
OE = VCC
fi = 10MHz
One Bit Toggling
—
2.7
6.5
mA
Symbol
VIH
VIL
IIH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
VCC = Max., VIH = 2.7V
IIL
Input LOW Current
VCC = Max., VIL = 0.5V
VIK
IOS(3)
VOH
VOL
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND
VCC = Min., VIN = VIH or VIL, IOH = –12mA
VCC = Min., VIN = VIH or VIL, IOL = 12mA
VH
Input Hysteresis
All inputs
ICC
Inputs only
I/O pins
Inputs only
I/O pins
NOTES:
1. For conditions shown as max. or min., use appropriate VCC value.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
4. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
5. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megaherz.
µA
2527 tbl 05
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
See Figure 5
2527 tbl 06
11.5
6
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, TA = 0° to +70°C)
73720A
Symbol
Test Conditions(1)
Parameter
tPLH
tPHL
X to Y & X to Z Latches enabled
tPLH
tPHL
Y to X & Z to X Latches enabled
tPLH
tPHL
Latch Enable to Y & Z Port
tPLH
tPHL
Latch Enable to X
tPLH
tPHL
Max.
73720
Min.(2)
Max.
Units
2.0
6.0
2.0
7.5
ns
2.0
6.0
2.0
7.5
ns
LEXY to Y
LEXZ to Z
2.0
7.0
2.0
8.5
ns
LEYX to X
LEZX to X
2.0
7.0
2.0
8.5
ns
Path to X Port Propagation Delay
2.0
7.0
2.0
8.5
ns
tHZ
tLZ
Y & Z Port Disable Time (T/R, PATH, OEU, OEL)(3)
2.0
8.5
2.0
9.5
ns
tZH
tZL
Y & Z Port Enable Time (T/R, PATH, OEU, OEL)(3)
2.0
9.5
2.0
10.5
ns
tHZ
tLZ
X-Port DisableTime (T/R, OEU, OEL)(3)
2.0
8.5
2.0
9.5
ns
tZH
tZL
tSU
X-Port Enable Time (T/R, OEU, OEL)(3)
2.0
9.5
2.0
10.5
ns
Port to LE Set-up time
2.0
—
2.0
—
ns
tH
Port to LE Hold time
1.5
—
1.5
—
ns
3
—
4
—
tW
LE Pulse Width, HIGH or LOW
CL = 50pF
RL = 500 Ohms
Min.(2)
(2)
NOTES:
1. All timings are referenced to 1.5 V.
2. Minimum Delay Times, Enable Times, Disable Times and Pulse Width are guaranteed by design, but not tested.
3. Bus turnaround times are guaranteed by design, but not tested. (T/R enable/disable times).
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
VCC
7.0V
V OUT
VIN
Switch
Disable LOW
Closed
All Other Tests
D.U.T.
50pF
RT
Test
Enable LOW
500Ω
Pulse
Generator
CL
ns
2527 tbl 07
500Ω
Open
DEFINITIONS:
2527 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2527 drw 07
Figure 5. Test Circuit for all outputs
11.5
7
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
tH
tREM
tSU
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
2527 drw 09
2527 drw 08
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPLH
OUTPUT
tPLH
tPLH
3V
1.5V
0V
3V
1.5V
0V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY SWITCH
LOW CLOSED
tPZH
VOH
1.5V
VOL
3V
1.5V
0V
OPPOSITE PHASE
INPUT TRANSITION
DISABLE
OUTPUT SWITCH
NORMALLY OPEN
HIGH
2527 drw 10
tPLZ
3.5V
3.5V
1.5V
0.3V
VOL
tPHZ
VOH
0.3V
1.5V
0V
0V
2527 drw 11
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR
≤ 2.5ns.
ORDERING INFORMATION
IDT
XXXXX
X
X
X
Device
Type
Speed
Package
Process/
Temperature
Range
Blank
Commercial Temperature Range
J
PQF
68-Pin PLCC
80-Pin PQFP
Blank
A
73720
Standard Speed
High Speed
Bus Exchanger
2527 drw 12
11.5
8