DATASHEET EL5825 FN7005 Rev 4.00 June 24, 2005 8-Channel TFT-LCD Reference Voltage Generator The EL5825 is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the serial interface. A serial out pin enables daisy chaining of multiple devices. Features A number of the EL5825 can be stacked for applications requiring more than 8 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. • Rail-to-rail capability The EL5825 has 8 outputs and is available in both the 24-pin TSSOP and the 24-pin QFN packages. It is specified for operation over the full -40°C to +85°C temperature range. • Reference voltage generators • Supply voltage of 4.5V to 16.5V • Digital supply 3.3V to 5V • Low supply current of 8mA • Pb-Free plus anneal available (RoHS compliant) Applications • TFT-LCD drive circuits Pinouts MDP0046 EL5825IL-T13 24-Pin QFN 13” MDP0046 EL5825ILZ (See Note) 24-Pin QFN (Pb-free) - MDP0046 EL5825ILZ-T7 (See Note) 24-Pin QFN (Pb-free) 7” MDP0046 EL5825ILZ-T13 (See Note) 24-Pin QFN (Pb-free) 13” MDP0046 EL5825IR 24-Pin TSSOP - MDP0044 EL5825IR-T7 24-Pin TSSOP 7” MDP0044 EL5825IR-T13 24-Pin TSSOP 13” MDP0044 EL5825IRZ (See Note) 24-Pin TSSOP (Pb-free) - MDP0044 EL5825IRZ-T7 (See Note) 24-Pin TSSOP (Pb-free) 7” MDP0044 EL5825IRZ-T13 24-Pin TSSOP (See Note) (Pb-free) 13” MDP0044 2 SDO ENA 23 3 OSC OUTA 22 4 VSD OUTB 21 5 NC OUTC 20 6 VS OUTD 19 7 REFH GND 18 8 REFL OUTE 17 9 GND OUTF 16 10 NC OUTG 15 11 CAP OUTH 14 12 NC 20 OUTA 7” OSC 1 19 OUTB VSD 2 18 OUTC NC 3 17 OUTD THERMAL PAD VS 4 Thermal Pad 16 GND REFH 5 15 OUTE REFL 6 14 OUTF GND 7 13 OUTG OUTH 12 24-Pin QFN SDI 24 21 ENA EL5825IL-T7 1 SCLK NC 11 MDP0046 22 SDI - NC 10 24-Pin QFN NC 9 EL5825IL 24 SDO TAPE & REEL PKG. DWG. # 23 SCLK EL5825 (24-PIN QFN) TOP VIEW CAP 8 PACKAGE • Accuracy of ±0.1% EL5825 (24-PIN TSSOP) TOP VIEW Ordering Information PART NUMBER • 8-channel reference outputs NC 13 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN7005 Rev 4.00 June 24, 2005 Page 1 of 12 EL5825 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . .+18V Supply Voltage between VSD and GND . . . . . . . VS and +7V (max) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 7.6 9 mA 0.17 0.35 mA 50 150 mV SUPPLY IS Supply Current ISD Digital Supply Current No load ANALOG VOL Output Swing Low Sinking 5mA (VREFH = 15V, VREFL = 0) VOH Output Swing High Sourcing 5mA (VREFH = 15V, VREFL = 0) ISC Short Circuit Current PSRR Power Supply Rejection Ratio tD 14.85 14.95 V RL = 10 100 140 mA VS+ is moved from 14V to 16V 45 60 dB Program to Out Delay 4 ms VAC Accuracy 20 mV VDROOP Droop Voltage 1 RINH Input Resistance @ VREFH, VREFL 34 REG Load Regulation BG Band Gap IOUT = 5mA step 1.1 2 mV/ms k 0.5 1.5 mV/mA 1.3 1.6 V DIGITAL VIH Logic 1 Input Voltage VIL Logic 0 Input Voltage FCLK Clock Frequency tS Setup Time 20 ns tH Hold Time 20 ns tLC Load to Clock Time 20 ns tCE Clock to Load Line 20 ns tDCO Clock to Out Delay Time 10 ns RSDIN SDIN Input Resistance 1 G FN7005 Rev 4.00 June 24, 2005 VSD20% Negative edge of SCLK V 20%* VSD V 5 MHz Page 2 of 12 EL5825 Pin Descriptions 24-PIN QFN 24-PIN TSSOP PIN NAME PIN TYPE 1 3 OSC IP/OP Oscillator pin for synchronizing multiple chips 2 4 VSD Power Positive power supply for digital circuits (3.3V - 5V) 3 5 NC 4 6 VS Power 5 7 REFH Analog Input High reference voltage 6 8 REFL Analog Input Low reference voltage 7 9 GND Power Ground 8 11 CAP Analog Decoupling capacitor for internal reference generator, 0.1µF 9 10 NC Not connected 10 12 NC Not connected 11 13 NC Not connected 12 14 OUTH Analog Output Channel H programmable output voltage 13 15 OUTG Analog Output Channel G programmable output voltage 14 16 OUTF Analog Output Channel F programmable output voltage 15 17 OUTE Analog Output Channel E programmable output voltage 16 18 GND Power 17 19 OUTD Analog Output Channel D programmable output voltage 18 20 OUTC Analog Output Channel C programmable output voltage 19 21 OUTB Analog Output Channel B programmable output voltage 20 22 OUTA Analog Output Channel A programmable output voltage 21 23 ENA Logic Input Chip select, low enables data input to logic 22 24 SDI Logic Input Serial data input 23 1 SCLK Logic Input Serial data clock 24 2 SDO Logic Output Serial data output FN7005 Rev 4.00 June 24, 2005 PIN DESCRIPTION Not connected Positive supply voltage for analog circuits Ground Page 3 of 12 EL5825 INPUT CODE 0.3 VSD (V) 180 160 0.2 140 120 0.1 ISD (nA) DIFFERENTIAL NONLINEARITY (LSB) Typical Performance Curves 0 100 80 60 -0.1 VS=15V VSD=5V VREFH=13V VREFL=2V -0.2 -0.3 10 210 410 610 810 40 20 0 3 1010 FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE 5 0mA 6.8 5.5 5mA/DIV 5mA 6.6 IS (mA) 4.5 VS=VREFH=15V M=400ns/DIV VOUT=0V 7 4 FIGURE 2. DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY VOLTAGE VS (V) 7.2 3.5 CL=4.7nF RS=20 6.4 6.2 5V CL=1nF RS=20 6 5.8 200mV/DIV CL=180pF 5.6 4 6 8 10 12 14 16 18 FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING) VS=VREFH=15V M=400ns/DIV M=200µs/DIV 5mA SCLK 0mA CL=1nF RS=20 SDA ENA CL=4.7nF RS=20 CL=180pF FIGURE 5. TRANSIENT LOAD REGULATION (SINKING) FN7005 Rev 4.00 June 24, 2005 OUTA FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V) Page 4 of 12 EL5825 Typical Performance Curves (Continued) M=200µs/div SCLK SDA ENA OUTA FIGURE 7. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 100mV) 0.9 0.8 1.176W 1.2 1 JA 0.8 0.6 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD TS S OP 24 =8 5° C/ W 0.4 0.2 781mW 0.7 0.6 JA 0.5 0.4 0.3 0.2 0.1 0 0 0 25 50 75 85 100 0 125 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.8 3 2.703W 1.5 FN 24 37 °C /W 1 0.5 0.5 A JA = 714mW 24 /W FN °C 40 =1 2 Q 0.6 Q POWER DISSIPATION (W) 0.7 2.5 J POWER DISSIPATION (W) TS SO P2 =1 4 28 °C /W 0.4 0.3 0.2 0.1 0 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7005 Rev 4.00 June 24, 2005 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Page 5 of 12 EL5825 Product Description The EL5825 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5825, this curve can be changed to optimize its characteristics according to the required application of the display product. Each of the reference voltage outputs can be set with a 10-bit resolution. These outputs are available to within 100mV of the power rails of the EL5825. allocated to the following functions (also refer to the Control Bits Logic Table) • Bit 15 is always set to a zero • Bit 14 controls the source of the clock, see the next section for details • Bits 13 through 10 select the channel to be written to, these are binary coded with channel A = 0, and channel H=7 • The 10-bit data is on bits 9 through 0. Some examples of data words are shown in the table of Serial Programming Examples TABLE 1. CONTROL BITS LOGIC TABLE BIT NAME DESCRIPTION B15 Test As all of the output buffers are identical, it is also possible to use the EL5825 for applications other than LCDs where 8 voltage references are required that can be set to a 10-bit accuracy. B14 Oscillator B13 A3 Channel Address (don’t care) B12 A2 Channel Address Serial Interface B11 A1 Channel Address The EL5825 is programmed through a three-wire serial interface. The start and stop conditions are defined by the ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The MSB (bit 15) is loaded first and the LSB (bit 0) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. B10 A0 Channel Address B9 D9 Data B8 D8 Data B7 D7 Data B6 D6 Data B5 D5 Data B4 D4 Data To facilitate the system designs that use multiple EL5825 chips, a buffered serial output of the shift register (SDO pin) is available. Data appears on the SDO pin at the 16th falling SCLK edge after being applied to the SDI pin. B3 D3 Data B2 D2 Data B1 D1 Data To control the multiple EL5825 chips from a single three-wire serial port, just connect the ENA pins and the SCLK pins together, connect the SDO pin to the SDI pin on the next chip. While the ENA is held low, the 16m-bit data is loaded to the SDI input of the first chip. The first 16-bit data will go to the last chip and the last 16-bit data will go to the first chip. While the ENA is held high, all addressed outputs will be updated simultaneously. B0 D0 Data Always 0 0 = Internal, 1 = External The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals. The serial data has a minimum length of 16 bits, the MSB (most significant bit) is the first bit in the signal. The bits are FN7005 Rev 4.00 June 24, 2005 Page 6 of 12 EL5825 Serial Timing Diagram ENA tHE tSE T tr tf tHE tSE SCLK tSD SDI tHD B15 tw B14 B13 B12-B2 B1 B0 t MSB LSB Load MSB first, LSB last TABLE 2. SERIAL TIMING PARAMETERS PARAMETER EXAMPLE DESCRIPTION T 200ns Clock Period tr/tf 0.05 * T Clock Rise/Fall Time tHE 10ns ENA Hold Time tSE 10ns ENA Setup Time tHD 10ns Data Hold Time tSD 10ns Data Setup Time tW 0.50 * T Clock Pulse Width TABLE 3. SERIAL PROGRAMMING EXAMPLES CONTROL CHANNEL ADDRESS C1 C0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 Internal Oscillator, Channel A, Value = 0 0 0 X 0 0 0 1 1 1 1 1 1 1 1 1 1 Internal Oscillator, Channel A, Value = 1023 0 0 X 0 0 0 1 0 0 0 0 0 0 0 0 0 Internal Oscillator, Channel A, Value = 512 0 0 X 0 1 1 1 0 0 0 0 0 0 0 0 1 Internal Oscillator, Channel C, Value = 513 0 0 X 1 1 1 0 0 0 0 0 1 1 1 1 1 Internal Oscillator, Channel H, Value = 31 0 1 X 1 1 1 0 0 0 0 0 1 1 1 1 1 External Oscillator, Channel H, Value = 31 FN7005 Rev 4.00 June 24, 2005 DATA CONDITION Page 7 of 12 EL5825 Internal Refresh Clock Oscillator The EL5825 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn’t be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 25kHz and can be output to the OSC pin. In a multiple chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. Subsequent chips may have the OSC pin connected to this clock source. In these chips, the program will set them to external OSC Mode by setting bit 14 to 1. See the control bits logic table and serial programming example for details. For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing on page 10 shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. After programming the oscillator with bit 14, the pin will be set to the appropriate mode. Transfer Function The transfer function is: data V OUT IDEAL = V REFL + ------------- V REFH - V REFL 1024 where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5825 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5825. GND < VREFH VS and GND VREFL VREFH. In some LCD applications that require more than 8 channels, the system can be designed such that one EL5825 will provide the Gamma correction voltages that are more positive than the VCOM potential. The second EL5825 can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing on page 10 shows a system connected in this way. Block Diagram REFERENCE HIGH OUTA OUTB OUTC OUTD EIGHT CHANNEL REGISTERS VOLTAGE SOURCES OUTE OUTF OUTG OUTH REFERENCE LOW CAP SERIAL DATA OUTPUT SERIAL DATA INPUT SERIAL CLOCK CONTROL IF ENABLE OSCILLATOR INPUT/OUTPUT3 FN7005 Rev 4.00 June 24, 2005 Page 8 of 12 EL5825 Channel Outputs Where: Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 100mV of the power rails, (see Electrical Characteristics for details). • i = 1 to total 8 When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 40µs. In the worst-case scenario this will be 320µs, when the data has just missed the cycle. When a large change in output voltage is required, the change will occur in 2 volt steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16 volts can take between 2.56 milliseconds and 3 milliseconds depending on the absolute timing relative to the update cycle. Power Dissipation With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125°C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to: T JMAX - T AMAX P DMAX = -------------------------------------------- JA • VS = Supply voltage • IS = Quiescent current • VOUTi = Output voltage of the i channel • ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, We can solve for the RLOAD's to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. Power Supply Bypassing and Printed Circuit Board Layout Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5825. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5825 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1µF ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7µF local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins. Application Using the EL5825 In the application drawing, the schematic shows the interconnect of a pair of EL5825 chips connected to give 8 gamma corrected voltages above the VCOM voltage, and 8 gamma corrected voltages below the VCOM voltage. By using the serial data out pin, it is possible to daisy chain (cascade) the two chips. In this mode the micro-controller will send a 32-bit word that will update both the upper and lower references voltages in one operation. See Application Drawing 1 for details. where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads. P DMAX = V S I S + V S - V OUT i I LOAD i when sourcing, and: P DMAX = V S I S + V OUT i I LOAD i when sinking. FN7005 Rev 4.00 June 24, 2005 Page 9 of 12 EL5825 Application Drawing HIGH REFERENCE VOLTAGE EL5825 +10V REFH OUTA VS OUTB VSD OUTC 0.1µF +12V COLUMN (SOURCE) DRIVER 0.1µF MICROCONTROLLER +5V LCD PANEL 0.1µF SERIAL DATA SDI SERIAL DATA CLOCK SCLK OUTE ENABLE ENA SERIAL DATA LCD TIMING CONTROLLER OUTD SDO OUTF OSC HORIZONTAL RATE CAP OUT 0.1µF REFL GND OUTH MIDDLE REFERENCE VOLTAGE +5.5V REFH OUTA OSC +12V VS OUTB 0.1µF +5V VSD OUTC 0.1µF SERIAL DATA SDI SERIAL DATA CLOCK SCLK OUTE ENABLE ENA CAP LOW REFERENCE VOLTAGE OUTD OUTF 0.1µF REFL +1V OUT 0.1µF GND OUTH Serial Timing Diagram (32 bit) FN7005 Rev 4.00 June 24, 2005 Page 10 of 12 EL5825 QFN Package Outline Drawing FN7005 Rev 4.00 June 24, 2005 Page 11 of 12 EL5825 TSSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> © Copyright Intersil Americas LLC 2004-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7005 Rev 4.00 June 24, 2005 Page 12 of 12