Catalyst CAT93HC46JATE13 1-kb high speed microwire serial eeprom Datasheet

H
EE
GEN FR
ALO
CAT93HC46
1-kb High Speed Microwire Serial EEPROM
LE
A D F R E ETM
FEATURES
■ High speed operation: 4 MHz @ 5.0 V
■ Low power CMOS technology
■ 1.8 to 5.5 volt operation
■ 1,000,000 program/erase cycles
■ Selectable x8 or x16 word organization
■ 100 year data retention
■ Sequential Read
■ Industrial and extended temperature ranges
■ Software write protection
■ 8-Lead PDIP, SOIC, MSOP and TSSOP
packages
■ Power-up inadvertent write protection
DESCRIPTION
The CAT93HC46 is a 1-kb Serial EEPROM memory
device which is configured as registers of either 16 bits
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
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PIN CONFIGURATION
DIP Package (P, L)
1
2
3
4
CS
SK
DI
DO
8
7
6
5
VCC
NC
ORG
GND
SOIC Package (J, W)
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
is
o
c
d
e
1
2
3
4
8
7
6
5
D
VCC
NC
ORG
GND
CS
SK
DI
DO
1
2
3
4
8
7
6
5
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FUNCTIONAL SYMBOL
DO
1
2
3
4
8
7
6
5
DO
DI
CAT93HC46
SK
CS
VCC
VSS
NC
ORG
GND
PIN FUNCTIONS
Pin Name
VCC
NC
ORG
GND
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
VCC
ORG
TSSOP Package (U, Y)
CS
SK
DI
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technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, SOIC,
MSOP or TSSOP packages.
SOIC Package (S, V) MSOP Package (R, Z)
CS
SK
DI
DO
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1
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
1.8 to 5.5 V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
Doc. No. 1008,Rev. H
CAT93HC46
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Storage Temperature ........................ -65°C to +150°C
Pin with Respect to Ground(1) .... -2.0 V to VCC + 2.0 V
VCC with Respect to Ground ................ -2.0 V to 7.0 V
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
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RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
NEND(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
TDR(3)
Data Retention
MIL-STD-883, Test Method 1008
100
VZAP(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
ILTH(3)(4)
Latch-Up
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
Industrial Temperature Range (-40°C to 85°C)
Symbol
Parameter
ICC1
Power Supply Current (Write)
ICC2
Power Supply Current (Read)
ISB1
Standby Supply Current (x8)
ISB2(5)
Standby Supply Current (x16)
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
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Min
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0
Max
a
P
Max
Units
Cycles/Byte
Years
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100
u
n
Limits
Typ
Typ
Volts
mA
Units
Test Conditions
mA
fSK = 4 MHz, VCC = 5.0 V
200
µA
fSK = 4 MHz, VCC = 5.0 V
10
µA
CS = GND, ORG=GND
10
µA
CS = GND, ORG = Float or VCC
1
µA
VIN = 0 V to VCC, CS = GND
1
µA
VOUT = 0 V to VCC, CS = GND
2
-0.1
0.8
4.5 V ≤ VCC < 5.5 V
2
VCC + 1
4.5 V ≤ VCC < 5.5 V
Input Low Voltage
0
VCC x 0.2
1.8 V ≤ VCC < 4.5 V
Input High Voltage
VCC x 0.7
VCC + 1
1.8V ≤ VCC < 4.5 V
0.4
4.5 V ≤ VCC < 5.5 V, IOL = 2.1 mA
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Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
2.4
V
Output Low Voltage
Output High Voltage
0.2
4.5 V ≤ VCC < 5.5 V, IOH = -400 µA
1.8 V ≤ VCC < 4.5 V, IOL = 1 mA
1.8 V ≤ VCC < 4.5 V, IOH = -100 µA
VCC - 0.2
Note:
(1) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1 V to VCC + 1 V.
(5) Standby Current (ISB2) = 0 µA (<900 nA).
Doc. No. 1008, Rev. H
2
CAT93HC46
POWER-UP TIMING (1)(2)
Symbol
Parameter
tPUR
tPUW
Min
Typ
Max
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
t
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A.C. CHARACTERISTICS
Industrial Temperature Range (-40°C to 85°C)
1.8 V - 5.5 V
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2.5 V - 5.5 V
4.5 V - 5.5 V
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
SKMAX
Maximum Clock Frequency
DC
1
DC
2
DC
4
MHz
tCSS
CS Setup Time
240
120
60
tCSH
CS Hold Time
0
0
0
tDIS
DI Setup Time
240
120
tDIH
DI Hold Time
240
120
tPD1
Output Delay to 1
480
240
120
ns
tPD0
Output Delay to 0
480
240
120
ns
tHZ(1)
Output Delay to High-Z
240
120
60
ns
tCSMIN
Minimum CS Low Time
tSKHI
Minimum SK High Time
tSKLOW
Minimum SK Low Time
tSV
Output Delay to Status Valid
480
240
120
ns
tEW
Program/Erase Pulse Width
5
5
5
ms
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n
240
480
240
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c
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e
240
ns
60
120
Conditions
ns
60
u
n
120
ns
Test
ns
60
ns
120
ns
60
ns
CL = 100 pF
(3)
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
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A.C. TEST CONDITIONS
Input Rise and Fall Times
≤ 10 ns
Input Pulse Voltages
0.4 V to 2.4 V
4.5 V ≤ VCC ≤ 5.5 V
Timing Reference Voltages
0.8 V, 2.0 V
4.5 V ≤ VCC ≤ 5.5 V
Input Pulse Voltages
VCC x 0.2 to VCC x 0.8
1.8 V ≤ VCC ≤ 4.5 V
Timing Reference Voltages
VCC x 0.5
1.8 V ≤ VCC ≤ 4.5 V
3
Doc. No. 1008, Rev. H
CAT93HC46
DEVICE OPERATION
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state by shifting a dummy “1” into the DI pin. The DO pin
will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin
and the DO pin are to be tied together to form a common
DI/O pin.
The CAT93HC46 is a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93HC46 can be organized as registers of either
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the operation of the device.
The CAT93HC46 operates on a single power supply and
will generate on chip the high voltage required during
write operation.
Instructions, addresses, and data are clocked into the DI
pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state, except when reading
data from the device, or when checking the ready/busy
status after a write operation.
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INSTRUCTION SET
Instruction
Start
Bit Opcode
Address
x8
x16
READ
1
10
A6-A0
ERASE
1
11
A6-A0
WRITE
1
01
A6-A0
EWEN
1
00
11XXXXX
EWDS
1
00
00XXXXX
ERAL
1
00
10XXXXX
WRAL
1
00
01XXXXX
s
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D
x8
it
n
A5-A0
o
c
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Data
A5-A0
A5-A0
D7-D0
11XXXX
00XXXX
x16
a
P
D7-D0
Comments
Read Address AN–A0
Clear Address AN–A0
D15-D0 Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
10XXXX
01XXXX
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r
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/
word address (an additional bit when organized X8) and
for write operations a 16-bit data field (8-bit for X8
organization).
D15-D0 Write All Addresses
Figure 1. Sychronous Data Timing
SK
DI
tSKHI
tSKLOW
tCSH
tDIS
tDIH
VALID
VALID
tCSS
CS
tDIS
tPD0,tPD1
DO
Doc. No. 1008, Rev. H
DATA VALID
4
tCSMIN
CAT93HC46
Read
Write
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state; after an initial
dummy zero bit, data will be shifted out, MSB first. The
output will toggle on the rising edge of the SK clock and
will be stable after the specified time delay (tPD0 or tPD1)
After receiving a WRITE command, address and data,
the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self-timed clear and data store cycle into the specified
memory location. The clocking of the SK pin is not
necessary after the device has entered the self-timed
mode. (Note 1.) The ready/busy status of the CAT93HC46
can be determined by selecting the device and polling
the DO pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
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Figure 2a. Read Instruction Timing
SK
CS
o
c
AN
DI
DO
1
1
AN—1
0
s
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D
HIGH-Z
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r
a
P
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self-timed
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self-timed mode. (Note 1.) The ready/busy
status of the CAT93HC46 can be determined by selecting
the device and polling the DO pin. Once cleared, the
content of a cleared location returns to a logical “1” state.
d
e
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n
tCS MIN
STANDBY
A0
tPD0
tHZ
HIGH-Z
0
DN
DN—1
D1
D0
Figure 2b. Sequential Read Instruction Timing
SK
1
1
1
1
1
AN
AN–1
1
1
1
1
1
1
1
1
1
1
CS
DI
DO
1
Don't Care
1
A0
0
HIGH-Z
Dummy 0
D15 . . . D0
or
D7 . . . D0
5
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Doc. No. 1008, Rev. H
CAT93HC46
Erase/Write Enable and Disable
Write All
The CAT93HC46 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once write is enabled, it will
remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can
be used to disable all CAT93HC46 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self-timed
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self-timed mode. The ready/busy status
of the CAT93HC46 can be determined by selecting the
device and polling the DO pin. It is not necessary for all
memory locations to be cleared before the WRAL
command is executed. Once written, the contents of all
memory locations will return to a logical “0” state.
Erase All
Figure 3. Write Instruction Timing
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n
SK
CS
AN
DI
1
o
c
0
DO
AN-1
1
s
i
D
A0
t
r
a
P
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if the CS is
brought low before or after this specific frame window,
the addressed location will not be programmed or erased.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self-timed clear cycle of
all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self-timed mode. (Note 1.) The ready/busy status of the
CAT93HC46 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory locations will return to a logical “1” state.
d
e
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n
DN
tCS MIN
STANDBY
STATUS
VERIFY
D0
tSV
tHZ
BUSY
HIGH-Z
READY
HIGH-Z
tEW
Figure 4. Erase Instruction Timing
SK
CS
STATUS VERIFY
AN
DI
1
1
tCS MIN
A0
AN-1
STANDBY
1
tHZ
tSV
HIGH-Z
DO
BUSY
READY
HIGH-Z
tEW
Doc. No. 1008, Rev. H
6
CAT93HC46
Figure 5. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
a
P
* ENABLE=11
DISABLE=00
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e
Figure 6. ERAL Instruction Timing
SK
CS
DI
1
0
1
0
o
c
s
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Figure 7. WRAL Instruction Timing
SK
CS
DI
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n
0
HIGH-Z
DO
1
0
0
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r
*
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STATUS VERIFY
STANDBY
tCS MIN
tSV
tHZ
BUSY
READY
HIGH-Z
tEW
STATUS VERIFY
STANDBY
tCS MIN
0
DN
1
D0
tSV
tHZ
DO
BUSY
READY
HIGH-Z
tEW
7
Doc. No. 1008, Rev. H
CAT93HC46
ORDERING INFORMATION
Prefix
Device #
Suffix
93HC46
CAT
Optional
Company ID
-1.8
I
S
Temperature Range
Blank = Commercial (0¡C to +70¡C)
I = Industrial (-40¡C to +85¡C)
A = Automotive (-40¡C to +105¡C)
E = Extended (-40ßC to +125ßC)
Product
Number
93HC46: 1K
Package
P = PDIP
S = SOIC (JEDEC)
J = SOIC (JEDEC)
U = TSSOP
* available upon request
Rev H(2)
TE13
Tape & Reel
a
P
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
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Notes:
(1) The device used in the above example is a 93HC46SI-TE13 (SOIC, Industrial Temperature,Tape & Reel).
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWH.) For additional
information, please contact your Catalyst sales office.
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Doc. No. 1008, Rev. H
8
t
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Die Revision
REVISION HISTORY
Date
Rev.
Reason
11/11/2003
E
Updated Features
Eliminated Commercial temperature range
Updated DC Operating Characteristics
Updated AC Characteristics
t
r
Updated Ordering Information
11/14/2003
F
Updated DC Operating Characteristics
7/27/2004
G
Add die revision to Ordering Information
03/11/2005
H
Updated Ordering Information
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Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
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a
P
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
it
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
o
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #:
Revison:
Issue date:
Type:
1008
H
03/11/05
Final
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