ON MC33304P Rail-to-rail sleep-mode operational amplifier Datasheet

Order this document by MC33304/D
v
t
The MC33304 is a monolithic bipolar operational amplifier. This low
voltage rail–to–rail amplifier has both a rail–to–rail input and output stage,
with high output current capability. This amplifier also employs Sleep–Mode
technology. In sleepmode, the micropower amplifier is active and waiting for
an input signal. When a signal is applied, causing the amplifier to source or
sink ≥200 µA (typically) to the load, it will automatically switch to the
awakemode (supplying up to 70 mA to the load). When the output current
drops below 90 µA, the amplifier automatically returns to the sleepmode.
Excellent performance can be achieved as an audio amplifier. This is due
to the amplifier’s low noise and low distortion. A delay circuit is incorporated
to prevent crossover distortion.
• Ideal for Battery Applications
•
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•
•
•
•
•
•
•
•
•
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•
•
Full Output Signal (No Distortion) for Battery Applications Down
to ±0.9 VDC.
Single Supply Operation (+1.8 to +12 V)
RAIL–TO–RAIL SLEEP–MODE
OPERATIONAL AMPLIFIER
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 646
14
1
Rail–To–Rail Performance on Both the Input and Output
Output Voltages Swings Typically within 100 mV of Both Rails
(RL = 1.0 mΩ)
Two States: “Sleepmode” (Micropower, ID = 110 µA/Amp) and
“Awakemode” (High Performance, ID = 1200 µA/Amp)
Automatic Return to Sleepmode when Output Current Drops Below
Threshold, Allowing a Fully Functional Micropower Amplifier
Independent Sleepmode Function for Each Amplifier
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
14
1
No Phase Reversal on the Output for Overdriven Input Signals
High Output Current (70 mA typically)
PIN CONNECTIONS
600 Ω Drive Capability
Standard Pinouts; No Additional Pins or Components Required
Drop–In Replacement for Many Other Quad Operational Amplifiers
Output 1 1
Similar to MC33201, MC33202 and MC33204 Family
2
The MC33304 Amplifier is Offered in the Plastic DIP or SOIC Package
(P and D Suffixes)
Inputs 1
14 Output 4
1
4
13
Inputs 4
3
12
VCC 4
11
VEE
Sleep–Mode is a trademark of Motorola, Inc.
5
Inputs 2
TYPICAL DC ELECTRICAL CHARACTERISTICS (TA = 25°C)
Characteristic
VCC = 2.0 V
VCC = 3.3 V
VCC = 5.0 V
Input Offset Voltage
VIO(max)
MC33304
±10
±10
±10
Output Voltage Swing
VOH (RL = 600 Ω)
VOL (RL = 600 Ω)
1.85
0.15
3.10
0.15
4.75
0.15
Power Supply Current
per Amplifier (ID)
Awakemode
Sleepmode
6
Output 2 7
1.625
140
Specifications are for reference only and not necessarily guaranteed. VEE = Gnd.
Vmin
Vmax
8
Output 3
ORDERING INFORMATION
mA
µA
Operating
Temperature Range
Package
TA = – 40° to +105°C
Plastic DIP
MC33304D
MC33304P
SO–14
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
Inputs 3
9
(Quad, Top View)
Device
1.625
140
3
Unit
mV
1.625
140
10
2
Rev 0
1
MC33304
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+16
V
Supply Voltage (VCC to VEE)
ESD Protection Voltage at Any Pin
Human Body Model
VESD
V
Voltage at Any Device Pin (Note 2)
VDP
VS ± 0.5
Input Differential Voltage Range
2000
V
VIDR
(Notes 1 & 2)
V
Output Short Circuit Duration
ts
Indefinite
(Note 3)
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature Range
Tstg
–65 to +150
°C
Maximum Power Dissipation
PD
(Note 5)
mW
RECOMMENDED OPERATING CONDITIONS
Characteristic
Supply Voltage
Single Supply
Split Supplies
Symbol
Min
Typ
Max
Unit
1.8
±0.9
–
–
12
±6.0
VICR
VEE
–
VCC
V
TA
–40
–
+105
°C
VS
Input Voltage Range, Sleepmode and Awakemode
Ambient Operating Temperature Range
V
DC ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Characteristic
Input Offset Voltage (VCM = 0 V, VO = 0 V) (Note 4)
Sleepmode and Awakemode
TA = 25°C
TA = –40° to +105°C
Average Temperature Coefficient of Input Offset Voltage
(RS = 50 Ω, VCM = 0 V, VO = 0 V)
TA = –40° to +105°C, Sleepmode and Awakemode
Symbol
Max
0.7
–
+10
+13
∆VIO/∆T
µV/°C
–
Input Offset Current (VCM = 0 V, VO = 0 V) (Note 4)
Awakemode
TA = 25°C
TA = –40° to +105°C
|IIO|
Power Supply Rejection Ratio, Awakemode
PSRR
Output Short Circuit Current (Awakemode)
(VID = ±0.2 V)
Source
Sink
ISC
–
90
–
+200
+500
nA
–
–
AVOL
2.0
nA
–
–
Large Signal Voltage Gain (VCC = +5.0 V, VEE = –5.0 V)
Awakemode, RL = 600 Ω
TA = 25°C
TA = –40° to +105°C
Unit
mV
–10
–13
 IIB|
2
Typ
VIO
Input Bias Current (VCM = 0 V, VO = 0 V) (Note 4)
Awakemode
TA = 25°C
TA = –40° to +105°C
Output Transition Current, Source/Sink
Sleepmode to Awakemode, VCC = +1.0 V, VEE = –1.0 V
Awakemode to Sleepmode, VCC = +5.0 V, VEE –5.0 V
Min
3.1
–
+50
+100
dB
90
85
116
–
–
–
65
90
–
dB
mA
–200
+50
–89
+89
–50
+200
–
90
–
–
200
–
µA
|ITH1|
|ITH2|
MOTOROLA ANALOG IC DEVICE DATA
MC33304
DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)
Characteristic
Output Voltage Swing (VID = ±0.2 V)
Sleepmode
VCC = +5.0 V, VEE = 0 V, RL = 1.0 MΩ
VCC = 0 V, VEE = –5.0 V, RL = 1.0 MΩ
VCC = +2.0 V, VEE = 0 V, RL = 1.0 MΩ
VCC = 0 V, VEE = –2.0 V, RL = 1.0 MΩ
Awakemode
VCC = +5.0 V, VEE = 0 V, RL = 600 Ω
VCC = 0 V, VEE = –5.0 V, RL = 600 Ω
VCC = +2.0 V, VEE = 0 V, RL = 600 Ω
VCC = 0 V, VEE = –2.0 V, RL = 600 Ω
VCC = +2.5 V, VEE = –2.5 V, RL = 600 Ω
VCC = +2.5 V, VEE = –2.5 V, RL = 600 Ω
Common Mode Rejection Ratio
Power Supply Current (per Amplifier)
Sleepmode
VCC = +2.0 V, VEE = 0 V
TA = +25°C
VCC = +2.5 V, VEE = –2.5 V TA = +25°C
TA = –40° to +105°C
VCC = +12 V, VEE = 0 V
TA = +25°C
Awakemode
VCC = +2.5 V, VEE = –2.5 V TA = +25°C
TA = –40° to +105°C
Symbol
Min
Typ
Max
V
VOH
VOL
VOH
VOL
4.90
–
1.90
–
4.97
–4.96
1.98
–1.97
–
–4.90
–
–1.90
VOH
VOL
VOH
VOL
VOH
VOL
4.75
–
1.85
–
–
–
4.86
–4.85
1.91
–1.90
2.41
–2.40
–
–4.75
–
–1.85
–
–
CMRR
60
90
–
dB
µA
ID
–
–
–
–
85
110
–
125
–
140
150
–
–
–
1200
–
1625
1750
–
–
145
75
–
–
θJA
Thermal Resistance
SOIC
Plastic DIP
Unit
°C/W
AC ELECTRICAL CHARACTERISTICS (VCC = +6.0 V, VEE = –6.0 V, RL = 600 Ω, TA = 25°C, unless otherwise noted.)
Characteristic
Slew Rate (VCC = +2.5 V, VEE = –2.5 V, AV = +1.0) (Note 6)
Awakemode
Gain Bandwidth Product (f = 100 kHz)
Awakemode
Symbol
Min
Typ
Max
0.5
0.89
–
–
2.2
–
–
–
6.0
9.0
–
–
–
–
40
60
–
–
–
–
4.0
12
–
–
–
1.5
–
–
100
–
SR
V/µs
GBW
Gain Margin (CL = 0 pF)
Awakemode
Sleepmode (RL = 1.0 kΩ)
Am
Phase Margin (RL = 1.0 kΩ, VO = 0 V, CL = 0 pF)
Awakemode
Sleepmode
φm
Sleepmode to Awakemode Transition Time
RL = 600 Ω
RL = 10 k
ttr1
Awakemode to Sleepmode Transition Time
ttr2
Channel Separation (f = 1.0 kHz)
Awakemode
CS
Unit
MHz
dB
Deg
µsec
sec
dB
NOTES: 1. The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to
each other. For more differential input voltage range, use current limiting resistors in series with the input pins.
2. The common–mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the
voltage on either input must not exceed supply rail by more than ±500 mV.
3. Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual
failure of the device.
4. Rail–to–rail performance is achieved at the input of the amplifier by using parallel NPN–PNP differential stages. When the inputs are near the
negative rail (VEE < VCM < 800 mV), the PNP stage is on. When the inputs are above 800 mV (i.e. 800 mV < VCM < VCC), the NPN stage is on.
This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN
and PNP pairs. Cross–coupling techniques have been used to keep this change to a minimum.
5. Power dissipation must be considered to ensure maximum junction (TJ) is not exceeded. (See Figure 2)
6. When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the
inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1.0 kΩ and
10 kΩ. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary.
(The output could be tied directly to the negative input.)
MOTOROLA ANALOG IC DEVICE DATA
3
MC33304
AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +6.0 V, VEE = –6.0 V, RL = 600 Ω, TA = 25°C, unless otherwise noted.)
Characteristic
Symbol
Power Bandwidth (VO = 4.0 Vpp, RL = 2.0 kΩ, THD ≤ 1.0%)
Awakemode
BWp
Distortion (VO = 2.0 Vpp, AV = +1.0)
Awakemode (f = 10 kHz)
Sleepmode (f = 1.0 kHz, RL = Infinite)
THD
Open Loop Output Impedance
(VO = 0 V, f = 2.0 MHz, AV = +10, IQ = 10 µA)
Awakemode
Sleepmode
|ZO|
Differential Input Impedance (VCM = 0 V)
Awakemode
Sleepmode
RIN
Differential Input Capacitance (VCM = 0 V)
Awakemode
Sleepmode
CIN
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz)
Awakemode
Sleepmode
en
Equivalent Input Noise Current (f = 1.0 kHz)
Awakemode
Sleepmode
in
Min
Typ
Max
–
28
–
–
–
0.009
0.007
–
–
Unit
kHz
%
Ω
–
–
100
1000
–
–
–
–
200
1300
–
–
–
–
8.0
0.4
–
–
–
–
15
60
–
–
–
–
0.22
0.20
–
–
kΩ
pF
nVńǸHz
pAńǸHz
NOTES: 1. The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to
each other. For more differential input voltage range, use current limiting resistors in series with the input pins.
2. The common–mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the
voltage on either input must not exceed supply rail by more than ±500 mV.
3. Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual
failure of the device.
4. Rail–to–rail performance is achieved at the input of the amplifier by using parallel NPN–PNP differential stages. When the inputs are near the
negative rail (VEE < VCM < 800 mV), the PNP stage is on. When the inputs are above 800 mV (i.e. 800 mV < VCM < VCC), the NPN stage is on.
This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN
and PNP pairs. Cross–coupling techniques have been used to keep this change to a minimum.
5. Power dissipation must be considered to ensure maximum junction (TJ) is not exceeded. (See Figure 2)
6. When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the
inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1.0 kΩ and
10 kΩ. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary.
(The output could be tied directly to the negative input.)
4
MOTOROLA ANALOG IC DEVICE DATA
MC33304
Figure 1. Equivalent Circuit Block Diagram (Each Amplifier)
Fractional
Load Current
Detector
Awake to
Sleepmode
Delay Circuit
Current
Threshold
Detector
% of IL
IHysteresis
IEnable
Buffer
Buffer
Iref
CStorage
Bias
Boost
Bias
IL
Vin
Input
Stage
Interface
Stage
Output
Stage
Vout
RL
Overdrive
Correction
IBias
Enable
Sleepmode
Current
Regulator
ISleep
Awakemode
Current
Regulator
IAwake
There are 515 active components for the entire quad device.
MOTOROLA ANALOG IC DEVICE DATA
5
MC33304
DEVICE DESCRIPTION
The MC33304 will begin to function at power supply
voltages as low as VS = ±0.8 V. The device has the ability to
swing rail–to–rail on both the input and the output. Since the
common mode input voltage range extends from VCC to VEE,
it can be operated with either single or split voltage supplies.
The MC33304 is guaranteed not to latch up or phase reverse
over the entire common mode range. However, the output
could go into phase reversal state if input voltage is set higher
than +VCC or –VEE.
When power is initially applied, the part may start to
operate in the awakemode. This occurs because of bias
currents being generated from the charging of the internal
capacitors. When this occurs, the user will have to wait
approximately 1.5 seconds before the device will switch back
to the sleepmode.
The amplifier is designed to switch from sleepmode to
awakemode whenever the output current exceeds a preset
current threshold (ITH) of approximately 200 µA. As a result,
the output switching threshold voltage (VST) is controlled by
the output loading resistance (RL). Large valued load
resistors require a large output voltage to switch, but reduce
unwanted transitions to the awakemode.
Most of the transition time is consumed slewing in the
sleepmode until VST is reached, therefore, small values of RL
allow rapid transition to the awakemode. The output
switching threshold voltage (VST) is higher for the larger
values of RL, requiring the amplifier to slew longer in the
slower sleepmode state before switching to the awakemode.
Although typically 200 µA, ITH varies with supply voltage,
temperature and the load resistance. Generally, any current
loading on the ouput which causes a current greater than ITH
6
to flow will switch the amplifier into the awakemode. This
includes transition currents like those generated by charging
load capacitances. In fact, the maximum capacitance that
can be driven while attempting to remain in the sleepmode is
approximately 300 pF.
The awakemode to sleepmode transition time is controlled
by an internal delay circuit, which is necessary to prevent the
amplifier from going to sleep during every zero crossing of
the output waveform. This delay circuit also eliminates the
crossover distortion commonly found in micropower
amplifiers.
The MC33304 rail–to–rail sleepmode operational amplifier
is unique in its ability to swing rail–to–rail on both the input
and output using a bipolar design. This offers a low noise and
wide common mode input voltage range. Since the common
mode input voltage range extends from VCC to VEE, it can be
operated with either single or split voltage supplies.
Rail–to–rail performance is achieved at the input of the
amplifiers by using parallel NPN–PNP differential input
stages. When the inputs are within 800 mV of the negative
rail, the PNP stage is on. When the inputs are more than
800 mV above VEE, the NPN stage is on. This switching of
input pairs will cause a reversal of input bias currents. Also,
slight differences in offset voltage may be noted between the
NPN and PNP pairs. Cross–coupling techniques have been
used to keep this change to a minimum.
In addition to the rail–to–rail performance, the output stage
is current boosted to provide enough output current to drive
600 Ω loads. Because of this high current capability, care
should be taken not to exceed the 150°C maximum junction
temperature specification.
MOTOROLA ANALOG IC DEVICE DATA
Figure 2. Maximum Power Dissipation
versus Temperature
Figure 3. Input Bias Current versus Temperature
150
2.5 k
IIB , INPUT BIAS CURRENT (nA)
PD(max) , MAXIMUM POWER DISSIPATION (mW)
MC33304
2.0 k
MC33304P
1.5 k
MC33304P
1.0 k
0.5 k
0
–55 –40 –25
0
25
50
85
TA = 25°C
VCC = +5.0 V
VEE = Gnd
Sleepmode
–50
Awakemode
–100
50
85
–4.0
–2.0
0
2.0
4.0
110
100
90
25
50
85
125
Figure 7. Output Voltage versus Frequency
12
VO, OUTPUT VOLTAGE SWING (Vpp )
8.0
6.0
4.0
2.0
MOTOROLA ANALOG IC DEVICE DATA
0
TA, AMBIENT TEMPERATURE (°C)
RL = 600 Ω – 1.0 MΩ
TA = 25°C
Awakemode/
Sleepmode
± 2.0
± 3.0
± 4.0
± 5.0
VCC,VEE SUPPLY VOLTAGE (V)
VCC = +5.0 V
VEE = Gnd
RL = 600 Ω
∆VO = 0.5 to 4.5 V
Awakemode
80
–55 –40 –25
6.0
125
120
Figure 6. Output Voltage Swing
versus Supply Voltage
VO, OUTPUT VOLTAGE (Vpp )
25
130
VCM, COMMON MODE INPUT VOLTAGE (V)
0
±1.0
0
Figure 5. Open Loop Voltage Gain
versus Temperature
0
10
–40 –25
Figure 4. Input Bias Current versus
Common Mode Input Voltage
50
12
Awakemode
90
TA, AMBIENT TEMPERATURE (°C)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
IIB, INPUT BIAS CURRENT (nA)
105
TA, AMBIENT TEMPERATURE (°C)
100
–150
–6.0
120
75
–55
125
VCC = +5.0 V
VEE = Gnd
VCM = 0 V
135
± 6.0
10
8.0
Sleepmode
(RL = 1.0 MΩ)
Awakemode
(RL = 600 Ω)
6.0
4.0
2.0
0
0.1
VCC = +6.0 V
VEE = –6.0 V
AV = +1.0
TA = 25°C
1.0
10
100
1.0 k
f, FREQUENCY (kHz)
7
MC33304
Figure 9. Common Mode Rejection
versus Frequency
Figure 8. Maximum Peak–to–Peak Output
Voltage Swing versus Load Resistance
CMR, COMMOM MODE REJECTION (dB)
VO, OUTPUT VOLTAGE SWING (Vpp )
100
10
1.0
VCC = +6.0 V
VEE = –6.0 V
f = 1.0 kHz
TA = 25°C
0.1
10
100
1.0 k
10 k
100 k
ITH1, CURRENT THRESHOLD ( µ A)
20
0
10
VCC = +6.0 V
VEE = –6.0 V
TA = 25°C
100
1.0 k
10 k
100 k
1.0 m
10 m
I TH2, CURRENT THRESHOLD ( µ A)
240
±PSR
Awakemode
±PSR
Sleepmode
VCC = +6.0 V
VEE = –6.0 V
TA = 25°C
100
1.0 k
10 k
100 k
1.0 M
Source Current
200
TA = 125°C
160
TA = 25°C
80
0
10 M
TA = –55°C
120
1.0
2.0
3.0
4.0
5.0
f, FREQUENCY (Hz)
VCC, VEE, SUPPLY VOLTAGE (V)
Figure 12. Sleepmode to Awakemode
Current Threshold versus Supply Voltage
Figure 13. Output Short Circuit Current
versus Output Voltage
Source Current
240
220
TA = 25°C
200
TA = –55°C
180
TA = 125°C
1.0
2.0
3.0
4.0
5.0
VCC, VEE, SUPPLY VOLTAGE (V)
8
40
Figure 11. Awakemode to Sleepmode
Current Threshold versus Supply Voltage
260
160
0
Sleepmode
Figure 10. Power Supply Rejection
versus Frequency
6.0
7.0
I SC, OUTPUT SHORT CIRCUIT CURRENT (mA)
PSR, POWER SUPPLY REJECTION (dB)
0
10
Awakemode
60
f, FREQUENCY (Hz)
40
20
80
RL, LOAD RESISTANCE TO GROUND (Ω)
80
60
100
6.0
80
70
Source
60
Sink
VCC = +6.0 V
VEE = –6.0 V
VID = ±1.0 V
Awakemode
50
40
0
2.0
4.0
6.0
IVOI, OUTPUT VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
Figure 14. Output Short Circuit Current
versus Temperature
Figure 15. Supply Current versus
Supply Voltage with Load
120
VCC = +5.0 V
VEE = Gnd
VID = ±0.2 V
RL = 1.0 MΩ
Awakemode
Source
100
4.0 k
I D, SUPPLY CURRENT ( µ A)
I SC, OUTPUT SHORT CIRCUIT CURRENT (mA)
MC33304
3.0 k
Sink
80
2.0 k
60
1.0 k
40
–55 –40 –25
0
25
50
85
Single Supply
RL = 600 Ω
0
0
125
3.5
TA, AMBIENT TEMPERATURE (°C)
SR, SLEW RATE (V/µ s)
400
Sleepmode (µA)
300
200
100
1.5
VCC = +2.5 V
VEE = –2.5 V
VO = ±2.0 V
RL= 600 Ω
+ Slew Rate
1.0
– Slew Rate
0.5
Single Supply
No Load
2.0
4.0
6.0
8.0
10
12
0
–55 –40 –25
14
0
25
70
85
V CC , SUPPLY VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
Figure 18. Gain Bandwidth Product
versus Temperature
Figure 19. Gain Margin versus
Differential Source Resistance
12
3.0
2.0
1.0
0
25
70
TA, AMBIENT TEMPERATURE (°C)
MOTOROLA ANALOG IC DEVICE DATA
85
105
125
Sleepmode
10
8.0
Awakemode
6.0
4.0
2.0
0
–55 –40 –25
105 125
14
VCC = + 2.5 V
VEE = – 2.5 V
f = 100 kHz
A m , GAIN MARGIN (dB)
I D, SUPPLY CURRENT ( µ A)
GBW, GAIN BANDWIDTH PRODUCT (MHz)
14
2.0
500
4.0
10.5
Figure 17. Slew Rate versus Temperature
Figure 16. Supply Current versus Supply Voltage
600
0
0
7.0
VCC, SUPPLY VOLTAGE (V)
0
10
VCC = +6.0 V
VEE = –6.0 V
RT = R1 + R2
VO = 0 V
TA = 25°C
100
1.0 k
10 k
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
9
MC33304
Figure 21. Gain Margin versus
Output Load Capacitance
Figure 20. Phase Margin versus
Differential Source Resistance
9.0
80
Sleepmode
A m , GAIN MARGIN (dB)
φ m , PHASE MARGIN ( ° )
70
60
50
40
Awakemode
30
20
10
10
VCC = +6.0 V
VEE = –6.0 V
RT = R1 + R2
VO = 0 V
TA = 25°C
100
1.0 k
Figure 23. Channel Separation
versus Frequency
140
CS, CHANNEL SEPARATION (dB)
Sleepmode
Awakemode
30
20
0
10
100
120
100
80
60
40
20
VCC = +6.0 V
VEE = –6.0 V
RL = 600 Ω
Awakemode
0
100
1.0 k
1.0 k
10 k
100 k
CL, OUTPUT LOAD CAPACITANCE (pF)
f, FREQUENCY (Hz)
Figure 24. Total Harmonic Distortion
versus Frequency
Figure 25. Input Referred Noise Voltage
versus Frequency
100
VCC = +6.0 V
VEE = –6.0 V
RL = 600 Ω
VO = 2.0 Vpp
TA = 25°C
Awakemode
1.0
AV = 1000
AV = 100
AV = 10
0.01
AV = 1.0
1.0 k
10 k
f, FREQUENCY (Hz)
100 k
en , INPUT REFERRED NOISE VOLTAGE (nV/ √Hz)
PHASE MARGIN ( ° )
1.0 k
Figure 22. Phase Margin versus
Output Load Capacitance
10
THD, TOTAL HARMONIC DISTORTION (%)
100
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
40
10
3.0
1.0
10
10 k
50
0.001
100
Awakemode
CL, OUTPUT LOAD CAPACITANCE (pF)
60
0.1
5.0
VCC = +6.0 V
VEE = –6.0 V
70
10
Sleepmode
7.0
100
80
Sleepmode
VCC = +6.0 V
VEE = –6.0 V
TA = 25°C
60
40
Awakemode
20
10
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
MC33304
Figure 27. Percent Overshoot
versus Load Capacitance
Figure 26. Current Noise versus Frequency
100
VCC = +6.0 V
VEE = –6.0 V
TA = 25°C
(RS = 100 k)
1.2
1.0
Awakemode
OS, PERCENT OVERSHOOT (%)
i n , INPUT NOISE CURRENT (pA/√ Hz)
1.4
0.8
0.6
0.4
0.2
80
VCC = +6.0 V
VEE = –6.0 V
TA = 25°C
60
40
Awakemode
(RL = 600 Ω)
20
Sleepmode
(RL = ∞)
Sleepmode
0
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
100 k
0
10
100
1.0 k
CL, LOAD CAPACITANCE (pF)
11
MC33304
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
14
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
M
F
–T–
M
K
D 14 PL
0.25 (0.010)
M
T B
S
M
R X 45 _
C
SEATING
PLANE
B
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
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12
◊
*MC33304/D*
MOTOROLA ANALOG IC DEVICE
DATA
MC33304/D