TI1 DAC7811IDGSRG4 12-bit, serial input, multiplying digital-to-analog converter Datasheet

 DA
C
781
1
DAC7811
SBAS337C – APRIL 2005 – REVISED JULY 2007
12-Bit, Serial Input, Multiplying
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
2.7V to 5.5V Supply Operation
50MHz Serial Interface
10MHz Multiplying Bandwidth
±15V Reference Input
Low Glitch Energy: 5nV-s
Extended Temperature Range:
–40°C to +125°C
10-Lead MSOP Package
12-Bit Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Daisy-Chain Mode
Readback Function
Industry-Standard Pin Configuration
APPLICATIONS
•
•
•
•
•
•
•
•
Portable Battery-Powered Instruments
Waveform Generators
Analog Processing
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
DESCRIPTION
The DAC7811 is a CMOS, 12-bit, current output
digital-to-analog converter (DAC). This device
operates from a 2.7V to 5.5V power supply, making it
suitable for battery-powered and many other
applications.
This DAC uses a double-buffered 3-wire serial
interface that is compatible with SPI™, QSPI™,
MICROWIRE™, and most DSP interface standards.
In addition, a serial data out pin (SDO) allows for
daisy-chaining when multiple devices are used. Data
readback allows the user to read the contents of the
DAC register via the SDO pin. On power-up, the
internal shift register and latches are filled with
zeroes and the DAC outputs are at zero scale.
The
DAC7811
offers
excellent
4-quadrant
multiplication characteristics, with large signal
multiplying bandwidth of 10MHz. The applied
external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback
resistor (RFB) provides temperature tracking and
full-scale voltage output when combined with an
external current-to-voltage precision amplifier.
The DAC7811 is available in a 10-lead MSOP
package.
VDD
VREF
R
DAC7811
RFB
12-Bit
R-2R DAC
IOUT1
IOUT2
DAC Register
Power-On
Reset
SYNC
SCLK
SDIN
Input Latch
Control Logic and
Input Shift Register
SDO
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
DAC7811
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SBAS337C – APRIL 2005 – REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
DAC7811
UNIT
–0.3 to +7.0
V
Digital input voltage to GND
–0.3 to VDD + 0.3
V
IOUT1, IOUT2 to GND
VDD to GND
–0.3 to VDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
–65 to +150
°C
Junction temperature (TJ max)
+150
°C
ESD Rating, HBM
2000
V
ESD Rating, CDM
1000
V
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = +2.7 V to +5.5 V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = +10 V; TA = full operating temperature. All specifications
–40°C to +125°C, unless otherwise noted.
DAC7811
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
Relative accuracy
±1
LSB
Differential nonlinearity
±1
LSB
Output leakage current
Data = 0000h, TA = +25°C
±5
nA
Output leakage current
Data = 0000h, TA = TMAX
±25
nA
Full-scale gain error
All ones loaded to DAC register
Full-scale tempco (1)
Output capacitance (1)
(1)
2
Bits
Code dependent
Specified by design and characterization; not production tested.
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±5
±10
mV
±5
ppm/°C
5
pF
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SBAS337C – APRIL 2005 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
VDD = +2.7 V to +5.5 V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = +10 V; TA = full operating temperature. All specifications
–40°C to +125°C, unless otherwise noted.
DAC7811
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT
VREF range
–15
15
V
8
10
12
kΩ
8
10
12
kΩ
VIL VDD = +2.7V
0.6
V
VIL VDD = +5V
0.8
V
Input resistance
RFB resistance
LOGIC INPUTS AND OUTPUT
Input low voltage
Input high voltage
Input leakage current
Input capacitance
(2)
VIH VDD = +2.7V
2.1
VIH VDD = +5V
2.4
V
V
IIL
10
µA
CIL
10
pF
50
MHz
INTERFACE TIMING (see Figure 28)
Clock input frequency
Clock period
fCLK
tC
20
ns
Clock pulse width high
tCH
8
ns
Clock pulse width low
tCC
8
ns
SYNC falling edge to SCLK
active edge setup time
tCSS
13
ns
SCLK active edge to SYNC
rising edge hold time
tCST
5
ns
Data setup time
tDS
5
ns
Data hold time
tDH
3
ns
SYNC high time
tSH
30
SYNC inactive edge to SDO
valid
tDDS
ns
VDD = +2.7V
25
35
ns
VDD = +5V
20
30
ns
5.5
V
POWER REQUIREMENTS
VDD
2.7
IDD (normal operation)
Logic inputs = 0V
5
µA
VDD = +4.5 V to +5.5 V
VIH = VDD and VIL = GND
0.8
5
µA
VDD = +2.7 V to +3.6 V
VIH = VDD and VIL = GND
0.4
2.5
µA
Reference multiplying BW
VREF = 7 VPP, Data = FFFh
10
MHz
DAC glitch impulse
VREF = 0 V to 10 V,
Data = 7FFh to 800h to 7FFh
5
nV-s
Feedthrough error VOUT/VREF
Data = 000h, VREF = 100kHz
–60
dB
2
nV-s
AC CHARACTERISTICS (2)
Output voltage settling time
0.2
Digital feedthrough
µs
Total harmonic distortion
–105
dB
Output spot noise voltage
18
nV/√Hz
(2)
Specified by design and characterization; not production tested.
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PIN DESCRIPTION
MSOP PACKAGE
(TOP VIEW)
IOUT1
1
10
IOUT2
2
9
GND
3
8
VDD
SCLK
4
5
7
6
SDO
SDIN
RFB
VREF
SYNC
TERMINAL FUNCTIONS
TERMINAL
NAME
1
IOUT1
DAC Current Output
2
IOUT2
DAC Analog Ground. This pin is normally tied to the analog ground of the system.
3
GND
Ground pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input.
Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift
register on the rising edge of SCLK.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default,
on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to
change the active edge to the rising edge.
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
edge of the following clocks (power-on default is falling clock edge). In stand-alone mode, the serial interface counts
the clocks and data is latched to the shift register on the 16th active clock edge.
6
SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked out on the
alternate edge to loading data to the shift register. Writing the Readback control word to the shift register makes the
DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock
edge.
8
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.7V to 5.5V.
9
VREF
DAC Reference Voltage Input
10
RFB
DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
7
4
DESCRIPTION
NO.
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TYPICAL CHARACTERISTICS: VDD = +5V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
TA = +25°C
0.8
TA = +25°C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 1.
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
0.8
TA = -40°C
0.8
TA = -40°C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
INL (LSB)
0
-0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
0.8
TA = +125°C
0.8
TA = +125°C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
INL (LSB)
0.2
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 5.
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 6.
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TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
0.9
VDD = +5.0V
Attenuation (dB)
0.7
0xFFF
0x800
0x400
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
0.6
0.5
0.4
0.3
0.2
VDD = +3.0V
0.1
0
0
1.0
2.0
3.0
4.0
0x000
10
5.0
100
10k
1k
100k
1M
10M
Logic Input Voltage (V)
Figure 8.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Output Voltage (50mV/div)
Figure 7.
Output Voltage (50mV/div)
100M
Bandwidth (Hz)
Code 2047 to 2048
DAC Update
Code 2048 to 2047
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 9.
Figure 10.
DAC SETTLING TIME
GAIN ERROR
vs TEMPERATURE
0
VREF = +10V
-0.2
Small Signal Settling
Gain Error (mV)
Output Voltage (%)
90
10
-0.4
DAC Update
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
Time (20ns/div)
-2.0
-40
-20
0
20
40
60
Temperature (°C)
Figure 11.
6
Figure 12.
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80
100
120
Digital Code
Supply Current (mA)
0.8
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-56
-60
-66
-72
-78
-84
-90
-96
-102
DAC7811
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SBAS337C – APRIL 2005 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs TEMPERATURE
2.0
1.6
VREF = +10V
1.8
VREF = +10V
1.4
1.6
Output Leakage (nA)
Quiescent Current (mA)
OUTPUT LEAKAGE
vs TEMPERATURE
1.4
1.2
1.0
VDD = +5.0V
0.8
0.6
VDD = +3.0V
0.4
1.2
1.0
0.8
0.6
0.4
0.2
0.2
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
Figure 13.
Figure 14.
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80
100
120
7
DAC7811
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SBAS337C – APRIL 2005 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +2.7V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
0.8
TA = +25°C
0.8
TA = +25°C
0.6
RREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1536 2048 2560
Digital Input Code
3072
3584
Figure 16.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
4096
1.0
0.8
TA = -40°C
0.6
VREF = +10V
0.8
TA = -40°C
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 17.
Figure 18.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
0.8
TA = +125°C
0.6
VREF = +10V
0.8
TA = +125°C
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 19.
8
1024
Figure 15.
1.0
INL (LSB)
0
-0.2
-0.4
-1.0
INL (LSB)
0.2
512
1024
1536 2048 2560
Digital Input Code
Figure 20.
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3072
3584
4096
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TYPICAL CHARACTERISTICS: VDD = +2.7V (continued)
At TA = +25°C, unless otherwise noted.
MIDSCALE DAC GLITCH
Output Voltage (50mV/div)
Output Voltage (50mV/div)
MIDSCALE DAC GLITCH
Code 2048 to 2047
Code 2047 to 2048
DAC Update
DAC Update
0
Time (50ns/div)
Time (50ns/div)
Figure 21.
Figure 22.
GAIN ERROR
vs TEMPERATURE
OUTPUT LEAKAGE
vs TEMPERATURE
1.6
VREF = +10V
-0.2
Output Leakage (nA)
-0.4
Gain Error (mV)
VREF = +10V
1.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
1.2
1.0
0.8
0.6
0.4
0.2
-1.8
0
-2.0
-40
-20
0
20
40
60
80
100
120
-40
Temperature (°C)
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 23.
Figure 24.
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Theory of Operation
The DAC7811 is a single channel, current output, 12-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 25, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to IOUT1 or the IOUT2 terminal. The IOUT1 terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load
impedance to the external reference of 10kΩ ±20%. The external reference voltage can vary over a range of
–15V to +15V, thus providing bipolar IOUT current operation. By using an external I/V converter and the
DAC7811 RFB resistor, output voltage ranges of –VREF to VREF can be generated.
R
R
R
R
VREF
2R
2R
2R
R
2R
RFB
IOUT1
IOUT2
DB11
(MSB)
DB10
DB9
DB0
(LSB)
Figure 25. Equivalent R-2R DAC Circuit
When using an external I/V converter and the DAC7811 RFB resistor, the DAC output voltage is given by
Equation 1:
V OUT + *VREF CODE
4096
(1)
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT1 terminal changes versus code, the external I/V converter noise gain
will also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage
such that the amplifier offset is not modulated by the DAC IOUT1 terminal impedance change. External op amps
with large offset voltages can produce INL errors in the transfer function of the DAC7811 due to offset
modulation versus DAC code.
For best linearity performance of the DAC7811, a low offset voltage op amp (such as the OPA277) is
recommended (see Figure 26). This circuit allows VREF swinging from –10V to +10V.
VDD
15V
VDD
VREF
RFB
DAC7811
GND
IOUT1
IOUT2
V+
OPA277
V-15V
Figure 26. Voltage Output Configuration
10
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Theory of Operation (continued)
Table 1. Control Logic Truth Table (1)
CLK
SYNC
X
H
No effect
Latched
↓–
L
Shift register data advanced one bit
Latched
In daisy-chain mode, the function as determined by
C3-C0 is executed.
In daisy-chain mode, the contents may change as
determined by C3-C0.
↑+
X
(1)
SERIAL SHIFT REGISTER
DAC REGISTER
↓– Negative logic transition, default CLK mode;↑+ Positive logic transition; X = Do not care.
Serial Interface
The DAC7811 has a 3-wire serial interface (SYNC, SCLK, and SDIN), which is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most Digital Signal Processor (DSP) devices. See the Serial Write
Operation timing diagram (Figure 28) for an example of a typical write sequence. The write sequence begins by
bringing the SYNC line low. Data from the DIN line are clocked into the 16-bit shift register on the falling edge of
SCLK. The serial clock frequency can be as high as 50MHz, making the DAC7811 compatible with high-speed
DSPs. The SDIN and SCLK input buffers are gated off while SYNC is high which minimizes the power
dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK
input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low,
but before the first active clock edge, it will be ignored. If the SDO pin is being used then SYNC must remain low
until after the inactive clock edge that follows the 16th active clock edge.
Input Shift Register
The input shift register is 16 bits wide, as shown in Figure 27. The four MSBs are the control bits C3–C0; these
bits determine which function will be executed at the rising edge of SYNC in daisy-chain mode or the 16th active
clock edge in stand-alone mode. The remaining 12 bits are the data bits. On a load and update command
(C3–C0 = 0001) these 12 data bits will be transferred to the DAC register; otherwise, they have no effect.
4 CONTROL BITS
12 DATA BITS
B15
(MSB)
B14
B13
B12
B11
C3
C2
C1
C0
DB11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(LSB)
DB0
Figure 27. Contents of the 16-Bit Input Shift Register
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SYNC Interrupt (Stand-Alone Mode)
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is
updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an
interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs.
Daisy-Chain
The DAC7811 powers up in the daisy-chain mode which must be used when two or more devices are connected
in tandem. The SCLK and SYNC signals are shared across all devices while the SDO output of the first device
connects to the SDIN input of the following device, and so forth. In this configuration 16 SCLK cycles for each
DAC7811 in the chain are required. Please refer to the timing diagram of Figure 28.
For n devices in a daisy-chain configuration, 16n SCLK cycles are required to shift in the entire input data
stream. After 16n active SCLK edges are received following a falling SYNC, the data stream becomes complete,
and SYNC can brought high to update n devices simultaneously.
When SYNC is brought high, each device will execute the function defined by the four DAC control bits C3-C0 in
its input shift register. For example, C3-C0 must be 0001 for each DAC in the chain that is to be updated with
new data, and C3-C0 must be 0000 for each DAC in the chain whose contents are to remain unchanged.
A continuous stream containing the exact number of SCLK cycles may be sent first while the SYNC signal is
held low, and then raise SYNC at a later time. Nothing happens until the rising edge of SYNC, and then each
DAC7811 in the chain will execute the function defined by the four DAC control bits C3-C0 in its input shift
register.
tC
SCLK
tCST
tCC
tCSS
tCH
tSH
SYNC
tDH
tDS
SDIN
DB15
(N)
DB0
(N)
DB15
(N + 1)
DB0
(N + 1)
tDDS
SDO
DB15
(N)
Figure 28. DAC7811 Timing Diagram
12
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(N)
DAC7811
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SBAS337C – APRIL 2005 – REVISED JULY 2007
Control Bits C3 to C0
Control Bits C3 to C0 allow control of various functions of the DAC; see Table 2. Default settings of the DAC on
powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled.
The device powers on with zero-scale loaded into the DAC register and IOUT lines. The DAC control bits allow
the user to adjust certain features as part of an initialization sequence; for example, daisy-chaining may be
disabled if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to
either zero or midscale. The user may also initiate a readback of the DAC register contents for verification
purposes.
Table 2. Serial Input Register Data Format, Data Loaded MSB First
C3
C2
C1
C0
FUNCTION IMPLEMENTED
0
0
0
0
No operation (power-on default)
0
0
0
1
Load and update
0
0
1
0
Initiate readback
0
0
1
1
Reserved
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Reserved
1
0
0
1
Daisy-chain disable
1
0
1
0
Clock data to shift register on rising edge
1
0
1
1
Clear DAC output to zero
1
1
0
0
Clear DAC output to midscale
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 29), the DAC7811 current output (IOUT) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design practices. For each code change, there is a step function. If the gain bandwidth product (GBP) of
the op amp is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible.
Therefore, for circuit stability, a compensation capacitor C1 (1pF to 5pF typ) can be added to the design, as
shown in Figure 29.
VDD
U1
VDD
VREF
RFB
C1
IOUT1
VREF
GND
VOUT
IOUT2
U2
Figure 29. Gain Peaking Prevention Circuit with Compensation Capacitor
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DAC7811
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SBAS337C – APRIL 2005 – REVISED JULY 2007
Amplifier Selection
There are many choices and many differences in selecting the proper operational amplifier for a multiplying DAC
(MDAC). Making the analog signal out of the MDAC is one critical aspect. However, there are also other issues
to take into account such as amplifier noise, input bias current, and offset voltage, as well as MDAC resolution
and glitch energy. Table 3 and Table 4 suggest some suitable operational amplifiers for low power, fast settling,
and high-speed applications. A greater selection of operational amplifiers can be found at www.ti.com/amplifer.
Table 3. Suitable Precision Operational Amplifiers from Texas Instruments
IQ
PER
CHANNEL GBW
(max)
(typ)
(mA)
(MHz)
TOTAL
SUPPLY
VOLTAGE
(V) (min)
TOTAL
SUPPLY
VOLTAGE
(V) (max)
SLEW
RATE
(typ)
(V/μs)
OFFSET
DRIFT
(typ)
(μV/°C)
IIB
(max)
(pA)
CMRR
(min)
(dB)
OPA703
4
12
0.2
1
0.6
4
10
70
SOT5-23,
PDIP-8,
SOIC-8
12V, CMOS, Rail-to-Rail I/O,
Operational Amplifier
OPA735
2.7
12
0.75
1.6
1.5
0.01
200
115
SOT5-23,
SOIC-8
0.05μV/°C (max),
Single-Supply CMOS
Zero-Drift Series Operational
Amplifier
OPA344
2.7
5.5
0.25
1
1
2.5
10
80
SOT5-23,
PDIP-8,
SOIC-8
Low Power, Single-Supply,
Rail-To-Rail Operational
Amplifiers MicroAmplifier
Series
OPA348
2.1
5.5
0.065
1
0.5
2
10
70
SC5-70,
SOT5-23,
SOIC-8
1MHz, 45μA, Rail-to-Rail I/O,
Single Op Amp
OPA277
4
36
0.825
1
0.8
0.1
1000
130
PDIP-8,
SOIC-8,
SON-8
High Precision Operational
Amplifiers
OPA350
2.7
5.5
7.5
38
22
4
10
76
MSOP-8,
PDIP-8,
SOIC-8
High-Speed, Single-Supply,
Rail-to-Rail Operational
Amplifiers MicroAmplifier
Series
OPA727
4
12
6.5
20
30
0.6
500
86
MSOP-8,
SON-8
e-trim 20MHz, High
Precision CMOS Operational
Amplifier
OPA227
5
36
3.8
8
2.3
0.1
10000
120
PDIP-8,
SOIC-8
PRODUCT
PACKAGE/
LEAD
DESCRIPTION
Low Power
Fast Settling
14
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High Precision, Low Noise
Operational Amplifiers
DAC7811
www.ti.com
SBAS337C – APRIL 2005 – REVISED JULY 2007
Table 4. Suitable High Speed Operational Amplifiers from Texas Instruments (Multiple Channel Options)
SUPPLY
VOLTAGE
(V)
GBW
PRODUCT
(MHz)
VOLTAGE
NOISE
nV/√Hz
GBW
(typ)
(MHz)
SLEW
RATE
(V/μs)
VOS
(typ)
(μV)
VOS
(max)
(μV)
CMRR
(min)
(dB)
THS4281
±2.7 to ±15
38
12.5
35
500
3500
500
1000
SOT5-23,
MSOP-8,
SOIC-8
Very Low-Power High Speed
Rail-To-Rail Input/Output
Voltage Feedback
Operational Amplifier
THS4031
±4.5 to ±16.5
200
1.6
100
500
3000
3000
8000
CDIP-8,
MSOP-8,
SOIC-8
100-MHz Low Noise
Voltage-Feedback Amplifier
THS4631
±4.5 to ±16.5
210
7
900
260
2000
50pA
2
SOIC-8,
MSOP-8
High Speed FET-Input
Operational Amplifier
OPA656
±4 to ±6
230
7
290
250
2600
2pA
5pA
SOIC-8,
SOT5-23
Wideband, Unity Gain Stable
FET-Input Operational
Amplifier
OPA820
±2.5 to ±6
280
2.5
240
200
1200
900
23,000
SOIC-8,
SOT5-23
Unity Gain Stable, Low
Noise, Voltage Feedback
Operational Amplifier
THS4032
±4.5 to ±16.5
200
1.6
100
500
3000
3000
8000
SOIC-8,
MSOP-8
100-MHz Low Noise
Voltage-Feedback Amplifier,
Dual
OPA2822
±2 to ±6.3
220
2
170
200
1200
9600
12000
SOIC-8,
MSOP-8
SpeedPlus Dual Wideband,
Low-Noise Operational
Amplifier
PRODUCT
PACKAGE/
LEAD
DESCRIPTION
Single Channel
Dual Channel
Submit Documentation Feedback
15
DAC7811
www.ti.com
SBAS337C – APRIL 2005 – REVISED JULY 2007
Positive Voltage Output Circuit
As Figure 30 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7811. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground
and a –2.5V input to the DAC7811 with an op amp.
+2.5V Reference
VDD
VIN
VOUT
GND
RFB
VDD
VREF
OPA277
C1
DAC7811 IOUT1
-2.5V
VOUT
OPA277
IOUT2
GND
0 £ VOUT £ +2.5V
Figure 30. Positive Voltage Output Circuit
Bipolar Output Section
The DAC7811, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 31,
external op amp U3 is added as a summing amp and has a gain of 2X that widens the output span to 5V. A
4-quadrant multiplying circuit is implemented by using a 2.5V offset of the reference voltage to bias U3.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full-scale produces
output voltages of VOUT = –2.5V to VOUT = +2.5V.
V OUT +
ǒ0.5 D 2
N
Ǔ
*1
V REF
(2)
External resistance mismatching is the significant error in Figure 31.
10kW
10kW
C2
VDD
VDD
+2.5V
(+10V)
5kW
RFB
VREF DAC7811 IOUT1
GND
U3
OPA277
C1
IOUT2
U2
OPA277
-2.5V £ VOUT £ +2.5V
(-10V £ VOUT £ +10V)
Figure 31. Bipolar Output Circuit
16
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VOUT
DAC7811
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SBAS337C – APRIL 2005 – REVISED JULY 2007
Programmable Current Source Circuit
A DAC7811 can be integrated into the circuit in Figure 32 to implement an improved Howland current pump for
precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3:
(R2)R3) ń R1
D
IL +
V REF
4096
R3
(3)
The value of R3 in Equation 3 can be reduced to increase the output current drive of U3. U3 can drive ±20mA in
both directions with voltage compliance limited up to 15V by the U3 voltage supply. Elimination of the circuit
compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO,
according to Equation 4:
R1ȀR3(R1)R2)
ZO +
R1(R2Ȁ)R3Ȁ) * R1Ȁ(R2)R3)
(4)
As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2¢
15kW
C1
10pF
R1¢
150kW
VDD
VREF
U3
OPA277
RFB
VDD
R3¢
50W
U1
IOUT1
DAC7811
IOUT2
GND
U2
OPA277
R1
150kW
R2
15kW
VOUT
R3
50W
IL
LOAD
Figure 32. Programmable Bidirectional Current Source Circuit
Cross-Reference
The DAC7811 has an industry-standard pinout. Table 5 provides the cross-reference information.
Table 5. Cross-Reference
PRODUCT
INL (LSB)
DNL (LSB)
SPECIFIED
TEMPERATURE
RANGE
DAC7811
±1
±1
–40°C to +125°C
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSSREFERENCE PART
10-Lead MicroSOIC
MSOP-10
AD5443YRM
Submit Documentation Feedback
17
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC7811IDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
DAC7811IDGSG4
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
DAC7811IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
DAC7811IDGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
DAC7811IDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
DAC7811IDGSTG4
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC7811IDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC7811IDGST
VSSOP
DGS
10
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC7811IDGSR
VSSOP
DGS
10
2500
366.0
364.0
50.0
DAC7811IDGST
VSSOP
DGS
10
250
366.0
364.0
50.0
Pack Materials-Page 2
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