High Common-Mode Voltage, Single-Supply Difference Amplifier AD8203 FEATURES FUNCTIONAL BLOCK DIAGRAMS NC A1 A2 +VS 6 3 4 7 AD8203 100kΩ G = ×7 G = ×2 +IN A1 –IN +IN 8 –IN 1 +IN A2 –IN 5 200kΩ 200kΩ 2 NC = NO CONNECT GND Figure 1. Functional Block Diagram INDUCTIVE 5V LOAD CLAMP DIODE OUTPUT GENERAL DESCRIPTION +IN BATTERY The AD8203 features an externally accessible 100 kΩ resistor at the output of the Preamp A1, which can be used for low-pass filter applications and for establishing gains other than 14. NC OUT 14V 4-TERM SHUNT AD8203 –IN GND A1 A2 POWER DEVICE The AD8203 is available in die and packaged form. The MSOP and SOIC packages are specified over a wide temperature range, from −40°C to +125°C, while the die is specified over a wider temperature range, from −40°C to +150°C, making the AD8203 well-suited for use in many automotive platforms. Automotive platforms demand precision components for better system control. The AD8203 provides excellent ac and dc performance keeping errors to a minimum in the user’s system. Typical offset and gain drift in the SOIC package are 0.3 μV/°C and 1 ppm/°C, respectively. Typical offset and gain drift in the MSOP package are 2 μV/°C and 1 ppm/°C, respectively. The device also delivers a minimum CMRR of 80 dB from dc to 10 kHz. +VS NC = NO CONNECT COMMON 05013-002 The AD8203 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage (CMV). The input CMV range extends from −6 V to +30 V at a typical supply voltage of 5 V. 05013-001 10kΩ APPLICATIONS Transmission control Diesel injection control Engine management Adaptive suspension control Vehicle dynamics control OUT 10kΩ Figure 2. High Line Current Sensor POWER DEVICE 5V OUTPUT +IN BATTERY +VS NC OUT 14V 4-TERM SHUNT AD8203 –IN CLAMP DIODE COMMON GND A1 A2 INDUCTIVE LOAD NC = NO CONNECT 05013-003 High common-mode voltage range −6 V to +30 V at a 5 V supply voltage Operating temperature range: −40°C to +125°C Supply voltage range: 3.5 V to 12 V Low-pass filter (1-pole or 2-pole) Excellent ac and dc performance ±1 mV voltage offset (8-lead SOIC) ±1 ppm/°C typical gain drift 80 dB CMRR minimum dc to 10 kHz Figure 3. Low Line Current Sensor Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD8203 TABLE OF CONTENTS Features .............................................................................................. 1 Current Sensing .......................................................................... 14 Applications....................................................................................... 1 Gain Adjustment ........................................................................ 14 Functional Block Diagrams............................................................. 1 Gain Trim .................................................................................... 15 Specifications..................................................................................... 3 Low-Pass Filtering...................................................................... 15 Single Supply ................................................................................. 3 High Line Current Sensing with LPF and Gain Adjustment ........................................................................ 16 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Driving Charge Redistribution ADCs..................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 Theory of Operation ...................................................................... 12 Applications..................................................................................... 14 REVISION HISTORY 10/05—Rev. A to Rev. B Added SOIC Package .........................................................Universal Replaced Figure 23 ........................................................................... 8 Added Figure 24 to Figure 29.......................................................... 9 Changes to Theory of Operation Section ................................... 12 Added Figure 41.............................................................................. 12 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 2/05—Rev. 0 to Rev. A Changes to Specifications Table...................................................... 3 Changes to Caption on Figure 6 and Figure 8 .............................. 6 Changes to Figure 12........................................................................ 7 Added Figure 14 to Figure 23.......................................................... 7 Changes to Figure 26 and Figure 27............................................. 10 Changes to Figure 29...................................................................... 11 Changes to Figure 32 and Figure 33............................................. 12 Changes to Ordering Guide .......................................................... 13 10/04—Revision 0: Initial Version Rev. B | Page 2 of 20 AD8203 SPECIFICATIONS SINGLE SUPPLY TA = operating temperature range, VS = 5 V, unless otherwise noted. Table 1. Parameter SYSTEM GAIN Initial Error vs. Temperature VOLTAGE OFFSET Input Offset (RTI) vs. Temperature INPUT Input Impedance Differential Common Mode CMV CMRR 1 PREAMPLIFIER Gain Gain Error Output Voltage Range Output Resistance OUTPUT BUFFER Gain Gain Error Output Voltage Range Input Bias Current Output Resistance DYNAMIC RESPONSE System Bandwidth Slew Rate NOISE 0.1 Hz to 10 Hz Spectral Density, 1 kHz (RTI) POWER SUPPLY Operating Range Quiescent Current vs. Temperature PSRR TEMPERATURE RANGE For Specified Performance 1 2 Conditions AD8203 SOIC Min Typ Max 0.02 ≤ VOUT ≤ 4.8 V dc @ 25°C −0.3 AD8203 MSOP Min Typ Max 14 VCM = 0.15 V; 25°C −40°C to +125°C −40°C to +150°C Continuous VCM = −6 V to +30 V f = dc f = 1 kHz f = 10 kHz 2 −1 −10 260 130 −6 14 −0.3 1 +0.3 20 +0.3 +1 +10 −2 −20 380 190 +30 260 130 −6 320 160 82 82 80 100 −0.3 0.02 97 −0.3 0.02 +0.3 4.8 −0.3 0.02 40 60 0.33 3.5 VS = 3.5 V to 12 V 0.25 75 −40 +2 +20 −1 −10 −15 380 190 +30 260 130 −6 40 100 −0.3 0.02 97 +0.3 4.8 −0.3 0.02 83 60 0.33 3.5 0.25 75 +125 −40 +0.3 +5 +1 +10 +15 mV μV/°C μV/°C 380 190 +30 kΩ kΩ V 320 160 dB dB dB 100 +0.3 4.8 103 2 40 10 300 12 1.0 1 V/V % ppm/°C 7 +0.3 4.8 103 12 1.0 83 +125 40 2 60 0.33 kHz V/μs 10 300 μV p-p nV/√Hz 0.25 −40 V/V % V kΩ V/V % V nA Ω +0.3 4.8 3.5 75 Unit +0.3 30 82 82 80 40 2 10 300 VO = 0.1 V dc +2 2 40 2 VIN = 0.01 V p-p, VOUT = 0.14 V p-p VIN = 0.28 V, VOUT = 4 V step 1 7 +0.3 4.8 103 2 0.02 ≤ VOUT ≤ 4.8 V dc −0.3 320 160 AD8203 Die Typ Max 14 +0.3 25 82 82 80 7 −0.3 0.02 97 Min 12 1.0 83 V mA dB +150 °C Source imbalance <2 Ω. The AD8203 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 kΩ resistor, even the small amount of pin-to-pin capacitance between Pin 1, Pin 8 and Pin 3, Pin 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pinto-pin coupling may be neglected in all applications by using filter capacitors at Node 3. Rev. B | Page 3 of 20 AD8203 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Transient Input Voltage (400 ms) Continuous Input Voltage (Common Mode) Reversed Supply Voltage Protection Operating Temperature Range Die SOIC MSOP Storage Temperature Output Short-Circuit Duration Lead Temperature Range (Soldering 10 sec) Rating 12.5 V 44 V 35 V 0.3 V −40°C to +150°C −40°C to +125°C −40°C to +125°C −65°C to +150°C Indefinite 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 4 of 20 AD8203 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 GND 2 AD8203 8 +IN 7 +VS 6 NC TOP VIEW A2 4 (Not to Scale) 5 OUT NC = NO CONNECT 05013-004 A1 3 Figure 4. Pin Configuration Table 3. Pin Function Descriptions Mnemonic −IN GND A1 A2 OUT NC +VS +IN 1036μm X −409.0 −244.6 +229.4 +410.0 +410.0 NA +121.0 −409.0 Y −205.2 −413.0 −413.0 −308.6 +272.4 NA +417.0 +205.2 +VS OUT +IN 1048μm –IN A2 GND A1 Figure 5. Metallization Photograph Rev. B | Page 5 of 20 05013-005 Pin No. 1 2 3 4 5 6 7 8 AD8203 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, VCM = 0 V, RL = 10 kΩ, unless otherwise noted. 0 90 80 COMMON-MODE VOLTAGE (V) –5 70 PSRR (dB) 60 50 40 30 20 –55°C –10 –40°C –15 +25°C –20 +125°C 100 1k FREQUENCY (Hz) 10k +150°C –30 3 100k Figure 6. Power Supply Rejection Ratio vs. Frequency for Common-Mode Range −6 V to +30 V 6 7 8 9 POWER SUPPLY (V) 10 11 12 40 COMMON-MODE VOLTAGE (V) 35 20 OUTPUT (dB) 5 Figure 9. Negative Common-Mode Voltage vs. Voltage Supply 25 15 10 5 +25°C 30 –55°C 25 +150°C 20 15 05013-007 0 100 4 1k 10k FREQUENCY (Hz) 100k 05013-010 0 10 05013-009 05013-006 –25 10 +125°C –40°C 10 3 1M 4 5 6 7 8 9 POWER SUPPLY (V) 10 11 12 Figure 10. Positive Common-Mode Voltage vs. Voltage Supply Figure 7. Bandwidth 100 5.0 95 90 OUTPUT VOLTAGE (dB) 4.0 80 75 70 65 60 2.0 100 1k FREQUENCY (Hz) 10k 0 10 100k Figure 8. Common-Mode Rejection Ratio vs. Frequency for Common-Mode Range −6 V to +30 V 05013-011 55 50 10 3.0 1.0 05013-008 CMRR (dB) 85 100 1k LOAD RESISTANCE (Ω) Figure 11. Output Swing vs. Load Resistance Rev. B | Page 6 of 20 10k AD8203 40 0 –6V TO +30V COMMON MODE TEMPERATURE = 25°C 35 OUTPUT MINUS SUPPLY (mV) –10 NO LOAD –20 30 25 HITS –30 –40 20 10kΩ LOAD 15 –50 10 3 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) 11 12 0 13 –80 –72 –64 –56 –48 –40 –32 –24 –16 –8 0 8 16 24 32 40 48 56 64 72 80 –70 05013-051 5 05013-012 –60 CMRR (μV/V) Figure 15. CMRR Distribution, Temperature = 25°C Figure 12. Swing Minus Supply vs. Supply Voltage 7 VSUPPLY = 5V TEMPERATURE RANGE = +25°C TO –40°C 6 OUTPUT HITS 5 4 3 4 INPUT 2 CH3 100mVΩ CH4 1.0VΩ 0 M 20μs 2.5MS/s 400NS/PT A CH3 260mV 05013-025 3 –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 05013-013 1 VOS DRIFT (μV/°C) Figure 16. Offset Drift Distribution, MSOP, Temperature Range = +25°C to −40°C Figure 13. Pulse Response 1000 8 800 7 –40°C 600 +25°C VSUPPLY = 5V TEMPERATURE RANGE = 25°C TO 85°C 6 5 HITS 200 0 –200 +85°C –400 4 3 +125°C 2 –600 –5 0 5 10 15 20 25 COMMON-MODE VOLTAGE (V) 30 05013-026 0 35 –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 –800 –1000 –10 1 05013-052 VOS (μV) 400 VOS DRIFT (μV/°C) Figure 17. Offset Drift Distribution, MSOP, Temperature Range = 25°C to 85°C Figure 14. VOS vs. Common-Mode Voltage Rev. B | Page 7 of 20 AD8203 9 8 VSUPPLY = 5V TEMPERATURE RANGE = 25°C TO 125°C 8 PACKAGE = MSOP @ –40°C 7 7 6 5 5 HITS HITS 6 4 4 3 3 2 2 VOS DRIFT (μV/°C) 05013-030 0 –2200 –2000 –1800 –1600 –1400 –1200 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 05013-027 0 1 –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 VOS (μV) Figure 21. VOS Distribution, MSOP, Temperature = −40°C Figure 18. VOS Distribution, MSOP, Temperature Range = 25°C to 125°C 8 10 PACKAGE = MSOP @ 25°C TEMPERATURE = 25°C 9 7 8 6 7 5 HITS HITS 6 5 4 4 3 3 2 2 05013-031 0.30 0.26 0.28 0.22 0.24 0.18 0.20 0.14 0.16 0.10 0.12 0.06 0.08 0.02 0.04 0 0 05013-028 0 1 –2200 –2000 –1800 –1600 –1400 –1200 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 1 ERROR (%) VOS (μV) Figure 19. VOS Distribution, MSOP, Temperature = 25°C Figure 22. MSOP Gain Accuracy, Temperature = 25°C 7 14 PACKAGE = MSOP @ 125°C TEMPERATURE = 125°C 6 10 5 8 4 ERROR (%) VOS (μV) Figure 20. VOS Distribution, MSOP, Temperature = 125°C Figure 23. MSOP Gain Accuracy, Temperature = 125°C Rev. B | Page 8 of 20 0.30 0.26 0.28 0.22 0.24 0.20 0.18 0.14 0.16 0.10 0.12 0 –2200 –2000 –1800 –1600 –1400 –1200 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 0 0.06 1 0.08 2 0.02 2 0.04 4 0 3 05013-029 6 05013-032 HITS HITS 12 AD8203 7 18 TEMPERATURE = –40°C 16 6 PACKAGE = MSOP VSUPPLY = 5V TEMPERATURE RANGE = 25°C TO 125°C 14 5 HITS HITS 12 4 3 10 8 6 2 05013-033 ERROR (%) 9 8 7 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 0 –9 0.28 2 0.30 0.24 0.26 0.20 0.22 0.16 0.18 0.12 0.14 0.08 0.10 0.04 0.06 0.02 0 0 05013-038 4 1 GAIN DRIFT (ppm/°C) Figure 24. MSOP Gain Accuracy, Temperature = −40°C Figure 27. Gain Drift Distribution, MSOP, Temperature Range = 25°C to 125°C 14 12 PACKAGE = MSOP VSUPPLY = 5V TEMPERATURE RANGE = +25°C TO –40°C PACKAGE = SOIC @ 25°C 12 10 10 8 HITS HITS 8 6 6 4 4 2 05013-039 –2000 –1800 –1600 –1400 –1200 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 05013-036 0 9 8 7 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 0 2 VOS (μV) GAIN DRIFT (ppm/°C) Figure 28. VOS Distribution, SOIC, Temperature = 25°C Figure 25. Gain Drift Distribution, Temperature Range = +25°C to −40°C 12 9 PACKAGE = MSOP VSUPPLY = 5V TEMPERATURE RANGE = 10 25°C TO 85°C PACKAGE = SOIC @ 125°C 8 7 HITS 6 6 4 5 4 3 2 05013-040 0 GAIN DRIFT (ppm/°C) –2000 –1800 –1600 –1400 –1200 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 1 9 8 7 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 0 05013-037 2 –9 HITS 8 VOS (μV) Figure 26. Gain Drift Distribution, MSOP, Temperature Range = 25°C to 85°C Figure 29. VOS Distribution, SOIC, Temperature = 125°C Rev. B | Page 9 of 20 AD8203 14 6 PACKAGE = SOIC @ –40°C 12 5 PACKAGE = SOIC VSUPPLY = 5V TEMPERATURE RANGE = 25°C TO 125°C 10 4 HITS HITS 8 3 6 2 4 VOS (μV) 5 12.0 13.5 15.0 VOS DRIFT (mV/°C) Figure 30. VOS Distribution, SOIC, Temperature = −40°C 6 –15.0 –13.5 –12.0 –10.5 –9.0 –7.5 –6.0 –4.5 –3.0 –1.5 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 05013-041 0 –2000 –1800 –1600 –1400 –1200 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 05013-044 1 2 Figure 33. Offset Drift Distribution, SOIC, Temperature Range = +25°C to 125°C 9 PACKAGE = SOIC VSUPPLY = 5V TEMPERATURE RANGE = +25°C TO –40°C TEMPERATURE = 25°C 8 7 6 HITS HITS 4 3 2 5 4 3 2 05013-045 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 1 12.0 13.5 15.0 –13.5 –12.0 –10.5 –9.0 –7.5 –6.0 –4.5 –3.0 –1.5 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 –15.0 0 05013-042 1 VOS DRIFT (μV/°C) ERROR (%) Figure 31. Offset Drift Distribution, SOIC, Temperature Range = +25°C to −40°C 6 5 Figure 34. Gain Accuracy, SOIC, Temperature = 25°C 9 PACKAGE = SOIC VSUPPLY = 5V TEMPERATURE RANGE = 25°C TO 85°C TEMPERATURE = 125°C 8 7 6 HITS 3 5 4 3 2 2 05013-046 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 1 12.0 13.5 15.0 –13.5 –12.0 –10.5 –9.0 –7.5 –6.0 –4.5 –3.0 –1.5 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 0 05013-043 1 –15.0 HITS 4 ERROR (%) VOS DRIFT (μV/°C) Figure 35. Gain Accuracy, SOIC, Temperature = 125°C Figure 32. Offset Drift Distribution, SOIC, Temperature Range = 25°C to 85°C Rev. B | Page 10 of 20 AD8203 12 10 TEMPERATURE = –40°C PACKAGE = SOIC 9 VSUPPLY = 5V TEMPERATURE RANGE = 8 25°C TO 85°C 10 7 8 HITS HITS 6 6 5 4 4 3 05013-047 ERROR (%) 9 8 6 6 5 16 14 12 8 10 6 4 2 0 –2 –4 –6 5 4 3 3 2 2 05013-048 4 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 1 0 16 14 12 8 10 6 4 2 0 –2 –4 –6 –8 –10 –12 –14 1 PACKAGE = SOIC VSUPPLY = 5V TEMPERATURE RANGE = 25°C TO 125°C 05013-050 HITS 7 –16 HITS –8 10 PACKAGE = SOIC VSUPPLY = 5V TEMPERATURE RANGE = +25°C to –40°C 7 0 –10 Figure 38. Gain Drift Distribution, SOIC, Temperature Range = 25°C to 85°C 10 8 –12 GAIN DRIFT (ppm/°C) Figure 36. Gain Accuracy, SOIC, Temperature = −40°C 9 –14 0 –16 1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 0 05013-049 2 2 GAIN DRIFT (ppm/°C) GAIN DRIFT (ppm/°C) Figure 37. Gain Drift Distribution, SOIC, Temperature Range = +25°C to −40°C Figure 39. Gain Drift Distribution, SOIC, Temperature Range = 25°C to 125°C Rev. B | Page 11 of 20 AD8203 THEORY OF OPERATION The AD8203 consists of a preamp and buffer, arranged as shown in Figure 40. Like-named resistors have equal values. The preamp incorporates a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas) consisting of RA, RB, RC, and RG, attenuate input signals applied to Pin 1 and Pin 8. Note that when equal amplitude signals are asserted at Input 1 and Input 8, and the output of A1 is equal to the common potential (that is, 0), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A1, and thus its output, is 0. B Any common-mode voltage applied to both inputs keeps the bridge balanced and the A1 output at 0. Because the resistor networks are carefully matched, the common-mode signal rejection approaches this ideal state. B By attenuating voltages at Pin 1 and Pin 8, the amplifier inputs are held within the power supply range, even if Pin 1 and Pin 8 input levels exceed the supply or fall below common (ground). The input network also attenuates normal (differential) mode voltages. RC and RG form an attenuator that scales A1 feedback, forcing large output signals to balance relatively small differential inputs. The resistor ratios establish the preamp gain at 7. Because the differential input signal is attenuated and then amplified to yield an overall gain of 7, Amplifier A1 operates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pin 1 and Pin 8. –IN 8 1 The 2-stage system architecture of the AD8203 enables the user to incorporate a low-pass filter prior to the output buffer. By separating the gain into two stages, a full-scale, rail-to-rail signal from the preamp can be filtered at Pin 3, and a half-scale signal, resulting from filtering, can be restored to full scale by the output buffer amp. The source resistance seen by the inverting input of A2 is approximately 100 kΩ to minimize the effects of the input bias current of A2. However, this current is quite small, and errors resulting from applications that mismatch the resistance are correspondingly small. The A2 input bias current has a typical value of 40 nA, however, this can increase under certain conditions. For example, if the input signal to the A2 amplifier is VCC/2, the output attempts to go to VCC due to the gain of 2. However, the output saturates because the maximum specified voltage for correct operation is 200 mV below VCC. Under these conditions the total input bias current increases (see Figure 41 for more information). –140 RA 100kΩ –120 3 4 (TRIMMED) RCM RB RB A2 5 RF RCM A3 RF RC RC RG AD8203 05013-014 RG 2 COM A2 INPUT BIAS CURRENT (nA) A1 –100 –80 –60 –40 –20 Figure 40. Simplified Schematic To minimize these errors while extending the common-mode range, a dedicated feedback loop is used to reduce the range of common-mode voltage applied to A1 for a given overall range at the inputs. By offsetting the range of voltage applied to the compensator, the input common-mode range is also offset to include voltages more negative than the power supply. The 0 05013-035 RA The output of the dynamic bridge taken from A1 is connected to Pin 3 by way of a 100 kΩ series resistor, provided for lowpass filtering and gain adjustment. The resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy. The output of the preamp drives a gain-of-2 buffer amplifier, A2, implemented with carefully matched feedback resistors RF. However, if the signals applied to the inputs differ, the result is a difference at the input to A1. A1 responds by adjusting its output to drive RB, by way of RG, to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. +IN A3 amplifier detects the common-mode signal applied to A1 and adjusts the voltage on the matched RCM resistors to reduce the common-mode voltage range at the A1 inputs. By adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. 0 0.5 1.0 1.5 2.0 DIFFERENTIAL MODE VOLTAGE (V) 2.5 Figure 41. A2 Input Bias Current vs. Input Voltage and Temperature. The Shaded Area Is the Bias Current from −40°C to +125°C. An increase in the A2 bias current, in addition to the output saturation voltage of A1, directly affects the output voltage of Rev. B | Page 12 of 20 AD8203 the AD8203 system (Pin 3 and Pin 4 shorted). An example of how to calculate the correct output voltage swing of the AD8203, by taking all variables into account, follows: • • Amplifier A1 output saturation potential can go as low as 20 mV at its output. The total error at the input of A2, 24 mV, multiplied by the buffer gain generates a resulting error of 48 mV at the output of the buffer. This is the AD8203 system output low saturation potential. • The high output voltage range of the AD8203 is specified as 4.8 V. Therefore, assuming a typical A2 input bias current, the output voltage range for the AD8203 is 48 mV to 4.8 V. A2 typical input bias current of 40 nA multiplied by the 100 kΩ preamplifier output resistor produces 40 nA × 100 kΩ = 4 mV at the A2 input • • Total voltage at the A2 input equals the output saturation voltage of A1 combined with the voltage error generated by the input bias current 20 mV + 4 mV = 24 mV For an example of the effect of changes in A2 input bias current vs. applied input potentials, see Figure 41. The change in bias current causes a change in error voltage at the input of the buffer amplifier. This results in a change in overall error potential at the output of the buffer amplifier. Rev. B | Page 13 of 20 AD8203 APPLICATIONS +VS The AD8203 difference amplifier is intended for applications that require extracting a small differential signal in the presence of large common-mode voltages. The input resistance is nominally 320 kΩ, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. The open collector output stage sources current to within 20 mV of ground and to within 200 mV of VS. OUT +IN VDIFF 2 +VS 10kΩ NC OUT 10kΩ GAIN = AD8203 VCM VDIFF REXT = 100kΩ 100kΩ 2 –IN 14REXT REXT + 100kΩ GND A1 GAIN 14 – GAIN A2 CURRENT SENSING REXT Basic automotive applications making use of the large commonmode range are shown in Figure 2 and Figure 3. The capability of the device to operate as an amplifier in primary battery supply circuits is shown in Figure 2. Figure 3 illustrates the ability of the device to withstand voltages below system ground. Low Current Sensing The AD8203 is also used in low current sensing applications, such as the 4 to 20 mA current loop shown in Figure 42. In such applications, the relatively large shunt resistor can degrade the common-mode rejection. Adding a resistor of equal value on the low impedance side of the input corrects this error. 05013-016 High Line, High Current Sensing NC = NO CONNECT Figure 43. Adjusting for Gains < 14 The overall bandwidth is unaffected by changes in gain by using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to the buffer. This can often be ignored, but if desired, it can be nulled by inserting a resistor equal to 100 kΩ minus the parallel sum of REXT and 100 kΩ, in series with Pin 4. For example, with REXT = 100 kΩ (yielding a composite gain of ×7), the optional offset nulling resistor is 50 kΩ. Gains Greater Than 14 5V Connecting a resistor from the output of the buffer amplifier to its noninverting input, as shown in Figure 44, increases the gain. The gain is now multiplied by the factor REXT/(REXT − 100 kΩ); for example, the gain is doubled for REXT = 200 kΩ. Overall gains as high as 50 are achievable this way. Note that the accuracy of the gain becomes critically dependent on the resistor value at high gains. Also, the effective input offset voltage at Pin 1 and Pin 8 (about six times the actual offset of A1) limits the part’s use in high gain, dc-coupled applications. OUTPUT +IN 10Ω 1% NC OUT AD8203 –IN GND A1 A2 NC = NO CONNECT 05013-015 + +VS +VS OUT +IN Figure 42. 4 to 20 mA Current Loop Receiver VDIFF 2 GAIN ADJUSTMENT +VS 10kΩ NC OUT 10kΩ GAIN = AD8203 The default gain of the preamplifier and buffer are ×7 and ×2, respectively, resulting in a composite gain of ×14. With the addition of external resistor(s) or trimmer(s), the gain can be lowered, raised, or finely calibrated. VCM VDIFF 2 REXT REXT = 100kΩ 100kΩ –IN GND A1 Figure 44. Adjusting for Gains > 14 Since the preamplifier has an output resistance of 100 kΩ, an external resistor connected from Pin 3 and Pin 4 to GND decreases the gain by a factor REXT/(100 kΩ + REXT), as shown in Figure 43. Rev. B | Page 14 of 20 GAIN GAIN – 14 A2 NC = NO CONNECT Gains Less Than 14 14REXT REXT – 100kΩ 05013-017 10Ω 1% AD8203 GAIN TRIM Figure 45 shows a method for incremental gain trimming by using a trim potentiometer and external resistor REXT. The following approximation is useful for small gain ranges: ΔG ≈ (10 MΩ/REXT)% Thus, the adjustment range is ±2% for REXT = 5 MΩ; ±10% for REXT = 1 MΩ, and so on. Low-pass filters can be implemented in several ways by using the features provided by the AD8203. In the simplest case, a single-pole filter (20 dB/decade) is formed when the output of A1 is connected to the input of A2 via the internal 100 kΩ resistor by strapping Pin 3, Pin 4, and a capacitor added from this node to ground, as shown in Figure 46. If a resistor is added across the capacitor to lower the gain, the corner frequency increases; it should be calculated using the parallel sum of the resistor and 100 kΩ. 5V 5V OUTPUT OUT +IN +VS NC +IN OUT VDIFF 2 VCM GND A1 fC = AD8203 AD8203 –IN OUT NC VDIFF 2 VDIFF 2 VCM +VS VDIFF 2 REXT C IN FARADS –IN A2 1 2πC105 GND A1 A2 GAIN TRIM 20kΩ MIN 05013-019 NC = NO CONNECT 05013-018 C NC = NO CONNECT Figure 45. Incremental Gain Trim Figure 46. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor Internal Signal Overload Considerations If the gain is raised using a resistor, as shown in Figure 44, the corner frequency is lowered by the same factor as the gain is raised. Thus, using a resistor of 200 kΩ (for which the gain would be doubled), the corner frequency is now 0.796 Hz μF (0.039 μF for a 20 Hz corner frequency). When configuring gain for values other than 14, the maximum input voltage with respect to the supply voltage and ground must be considered, since either the preamplifier or the output buffer reaches its full-scale output (approximately VS − 0.2 V) with large differential input voltages. The input of the AD8203 is limited to (VS − 0.2)/7 for overall gains ≤ 7, since the preamplifier, with its fixed gain of ×7, reaches its full-scale output before the output buffer. For gains greater than 7, the swing at the buffer output reaches its full scale first and limits the AD8203 input to (VS − 0.2)/G, where G is the overall gain. 5V OUT +IN +VS OUT NC VDIFF 2 AD8203 VCM C VDIFF 2 –IN GND A1 A2 LOW-PASS FILTERING When implementing a filter, the PAR should be considered so that the output of the AD8203 preamplifier (A1) does not clip before A2, since this nonlinearity would be averaged and appear as an error at the output. To avoid this error, both amplifiers should be made to clip at the same time. This condition is achieved when the PAR is no greater than the gain of the second amplifier (2 for the default configuration). For example, if a PAR of 5 is expected, the gain of A2 should be increased to 5. 255kΩ C fC(Hz) = 1/C(μF) NC = NO CONNECT 005013-020 In many transducer applications, it is necessary to filter the signal to remove spurious high frequency components, including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (PAR) greater than unity. For example, a full-wave rectified sinusoid has a PAR of 1.57, a raised cosine has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14. Signals having large spikes can have PARs of 10 or more. Figure 47. 2-Pole, Low-Pass Filter A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented using the connections shown in Figure 47. This is a Sallen-Key form based on a ×2 amplifier. It is useful to remember that a 2-pole filter with a corner frequency f2 and a 1-pole filter with a corner at f1 have the same attenuation at the frequency (f22/f1). The attenuation at that frequency is 40 log (f2/f1), which is illustrated in Figure 48. Using the standard resistor value shown and equal capacitors (see Figure 47), the corner frequency is conveniently scaled at 1 Hz μF (0.05 μF for a 20 Hz corner). A maximally flat response occurs when the resistor is lowered to 196 kΩ and the scaling is then 1.145 Hz μF. The output offset is raised by approximately 5 mV (equivalent to 250 μV at the input pins). Rev. B | Page 15 of 20 AD8203 FREQUENCY by a 1-pole low-pass filter, shown in Figure 49, set with a corner frequency of 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. A higher rate of attenuation can be obtained using a 2-pole filter with fC = 20 Hz, as shown in Figure 50. Although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the 1-pole filter. 20dB/DECADE 40log (f2/f1) INDUCTIVE 5V LOAD CLAMP DIODE OUTPUT +IN A 1-POLE FILTER, CORNER f1, AND A 2-POLE FILTER, CORNER f2, HAVE THE SAME ATTENUATION –40log (f2/f1) AT FREQUENCY f22/f1 BATTERY 05013-021 C NC = NO CONNECT NC OUT 20kΩ A1 A2 POWER DEVICE VOS/IB NULL 5% CALIBRATION RANGE fC(Hz) = 0.767Hz/C(μF) (0.22μF FOR fC = 3.6Hz) 05013-022 C COMMON COMMON fC(Hz) = 1/C(μF) (0.05μF FOR fC = 20Hz) Figure 50. 2-Pole Low-Pass Filter 133kΩ NC = NO CONNECT A2 93kΩ AD8203 GND A1 POWER DEVICE OUT 4V/AMP 14V –IN GND DRIVING CHARGE REDISTRIBUTION ADCS INDUCTIVE 5V LOAD 4-TERM SHUNT C 50kΩ Figure 49 is another refinement of Figure 2, including gain adjustment and low-pass filtering. +VS AD8203 –IN HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT +IN 301kΩ 4-TERM SHUNT Figure 48. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters CLAMP DIODE OUT 14V f22/f1 f2 NC 05013-023 f1 BATTERY +VS Figure 49. High Line Current Sensor Interface; Gain = ×40, Single-Pole Low-Pass Filter A power device that is either on or off controls the current in the load. The average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. The average differential voltage across the shunt is typically 100 mV, although its peak value is higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, conversely, extends from roughly 1 V above ground for the on condition to about 1.5 V above the battery voltage for the off condition. The conduction of the clamping diode regulates the common-mode potential applied to the device. For example, a battery spike of 20 V may result in an applied common-mode potential of 21.5 V to the input of the devices. When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection (ΔQ) can cause a significant deflection in the output voltage of the AD8203. Though generally of short duration, this deflection may persist until after the sample period of the ADC has expired due to the relatively high open-loop output impedance (21 kΩ) of the AD8203. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the AD8203. For these applications, the output signal should be taken from the midpoint of the RLAG to CLAG combination, as shown in Figure 51. Since the perturbations from the analog-to-digital converter are small, the output impedance of the AD8203 appears to be low. The transient response, therefore, has a time constant governed by the product of the two LAG components, CLAG × RLAG. For the values shown in Figure 51, this time constant is programmed at approximately 10 μs. Therefore, if samples are taken at several tens of microseconds or more, there is negligible charge stack-up. To produce a full-scale output of 4 V, a gain ×40 is used, adjustable by ±5% to absorb the tolerance in the shunt. There is sufficient headroom to allow 10% overrange (to 4.4 V). The roughly triangular voltage across the sense resistor is averaged Rev. B | Page 16 of 20 5V 4 7 +IN AD8203 RLAG 1kΩ A2 5 –IN 10kΩ CLAG 0.01μF MICROPROCESSOR A/D 10kΩ 2 Figure 51. Recommended Circuit for Driving CMOS A/D 05013-024 ATTENUATION 40dB/DECADE AD8203 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.00 (0.1968) 4.80 (0.1890) 5.15 4.90 4.65 5 5 4 4 1.27 (0.0500) BSC PIN 1 0.25 (0.0098) 0.10 (0.0040) 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 8 4.00 (0.1574) 3.80 (0.1497) 1 0.38 0.22 0.23 0.08 0.80 0.60 0.40 8° 0° SEATING PLANE COPLANARITY 0.10 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 0.50 (0.0196) × 45° 0.25 (0.0099) 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 53. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Figure 52. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model AD8203YRMZ 1 AD8203YRMZ-RL1 AD8203YRMZ-R71 AD8203YRZ1 AD8203YRZ-RL1 AD8203YRZ-R71 AD8203YCSURF 1 Temperature Package −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Die Z = Pb-free part. Rev. B | Page 17 of 20 Package Outline RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding JXA JXA JXA AD8203 NOTES Rev. B | Page 18 of 20 AD8203 NOTES Rev. B | Page 19 of 20 AD8203 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05013-0-10/05(B) Rev. B | Page 20 of 20