CY241V8A-11 MPEG Clock Generator with VCXO MPEG Clock Generator with VCXO Features Benefits ■ Integrated phase locked loop (PLL) ■ Highest performance PLL tailored for multimedia applications ■ Low jitter, high accuracy outputs ■ Meets critical timing requirements in complex system designs ■ VCXO with analog adjust ■ Application compatibility for a wide variety of designs ■ 3.3 V operation Frequency Table Part Number Outputs CY241V8A-11 1 Input Frequency Range Control Output Frequencies VCXO Curve 13.5 MHz pullable crystal input One copy of 54 MHz per Cypress specification linear Other Features Pinout-compatible with CY2411 Block Diagram 13.5 XIN OSC Output Divider PLL 54 MHz XOUT VDD VCXO VSS Pin Configuration Figure 1. 8-pin SOIC pinout Pin Descriptions Name Pin Number XIN 1 VDD 2, 5 VCXO VSS 3 4, 7 Description Reference crystal input Voltage supply Input analog control for VCXO Ground 54 MHz 6 54 MHz clock output XOUT 8 Reference crystal output Cypress Semiconductor Corporation Document Number: 38-07654 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 21, 2012 CY241V8A-11 Junction temperature .............................. –40 C to +125 C Absolute Maximum Conditions Supply voltage (VDD) ...................................... –0.5 to +7.0 V DC input voltage ................................. –0.5 V to VDD + 0.5 V Storage temperature (Non-condensing) .................................... –55 C to +125 C Data retention at Tj = 125 C ................................> 10 years Package power dissipation ...................................... 350 mW ESD (human body model) MIL-STD-883 ................ > 2000 V Pullable Crystal Specifications Parameter [1] Description Comments FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR Ratio used because typical R1 to fundamental mode ESR values are much less than the maximum spec Parallel resonance, fundamental mode, AT cut Fundamental mode Min Typ Max Unit – 13.5 – MHz – 14 – pF – – 25 3 – – – DL Crystal drive level No external series resistor assumed 150 – – W F3SEPHI Third overtone separation from 3 × FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3 × FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 – C1 Crystal motional capacitance 14.4 18 21.6 fF Min Typ Max Unit 3.135 3.3 3.465 V 0 – 70 C Recommended Operating Conditions Parameter Description VDD Operating voltage TA Ambient temperature CLOAD Max load capacitance tPU Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) – – 15 pF 0.05 – 500 ms DC Electrical Specifications Min Typ Max Unit IOH Parameter Output HIGH current Name VOH = VDD – 0.5 V, VDD = 3.3 V Description 12 24 – mA IOL Output LOW current VOL = 0.5 V, VDD = 3.3 V 12 24 – mA CIN Input capacitance Except XIN, XOUT pins – – 7 pF VVCXO VCXO input range fXO[2] VCXO pullability range IVDD Supply current 0 – VDD V Low side – – –115 ppm High side 115 – – ppm – 30 35 mA Notes 1. Crystals that meet this specification include: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. 2. –115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. Document Number: 38-07654 Rev. *D Page 2 of 9 CY241V8A-11 AC Electrical Specifications (VDD = 3.3 V) Parameter [3] Name Description Min Typ Max Unit DC Output duty cycle Duty cycle is defined in Figure 3 on page 4, 50% of VDD 45 50 55 % ER Rising edge rate Output clock edge rate, measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 4 on page 4. 0.8 1.4 – V/ns EF Falling edge rate Output clock edge rate, measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 4 on page 4. 0.8 1.4 – V/ns t9 Clock jitter Peak-to-peak period jitter – – 100 ps t10 PLL lock time – – 3 ms Test and Measurement Setup Figure 2. Test and Measurement Setup VDD 0.1 F DUT Outputs CLOAD GND Note 3. Not 100% tested. Document Number: 38-07654 Rev. *D Page 3 of 9 CY241V8A-11 Voltage and Timing Definitions Figure 3. Duty Cycle Definition t1 t2 VDD 50% of V DD Clock Output 0V Figure 4. ER = (0.6 × VDD) / t3, EF = (0.6 × VDD) / t4 t3 t4 V DD 80% of V DD Clock Output Document Number: 38-07654 Rev. *D 20% of V DD 0V Page 4 of 9 CY241V8A-11 Ordering Information Package Name Ordering Code Package Type Operating Range Operating Voltage Features CY241V8ASXC-11 S8 8-pin SOIC Commercial 3.3 V Linear VCXO control curve CY241V8ASXC-11T S8 8-pin SOIC – Tape and Reel Commercial 3.3 V Linear VCXO control curve Ordering Code Definitions CY 241V8A S X C - 11 X X = blank or T blank = Tube; T = Tape and Reel Fixed (Specific Configuration Code) Temperature Grade: C = Commercial = 0 °C to 70 °C Pb-free Package Type: S = 8-pin SOIC Base Part Number Company ID: CY = Cypress Document Number: 38-07654 Rev. *D Page 5 of 9 CY241V8A-11 Package Drawing and Dimensions Figure 5. 8-pin SOIC (150 Mils) S08.15/SZ08.15 Package Outline, 51-85066 51-85066 *E Document Number: 38-07654 Rev. *D Page 6 of 9 CY241V8A-11 Acronyms Acronym Document Conventions Description Units of Measure ESD electrostatic discharge ESR equivalent series resistance °C degree Celsius PLL phase locked loop fF femtofarad SOIC small outline integrated circuit MHz megahertz VCXO voltage controlled crystal oscillator µF microfarad µW microwatt mA milliampere ms millisecond mW milliwatt ns nanosecond ohm % percent pF picofarad ppm parts per million ps picosecond V volt Document Number: 38-07654 Rev. *D Symbol Unit of Measure Page 7 of 9 CY241V8A-11 Document History Page Document Title: CY241V8A-11, MPEG Clock Generator with VCXO Document Number: 38-07654 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 214071 See ECN RGL New data sheet. *A 220461 See ECN RGL Minor Change (Post to external web). *B 2896017 03/18/2010 CXQ Obsolete document (All are inactive parts). *C 3000820 08/06/2010 CXQ Reinstatement of data sheet. Updated Ordering Information (Added Pb-free devices). *D 3557456 03/21/2012 PURU Document Number: 38-07654 Rev. *D Updated Package Drawing and Dimensions. Added Acronyms and Units of Measure. Removed from web (Post to internal spec system only since the part is not available on web, hence removing the data sheet from Cypress web). Page 8 of 9 CY241V8A-11 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07654 Rev. *D Revised March 21, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 9 of 9