LINER LTC1343 Software-selectable multiprotocol transceiver Datasheet

LTC1343
Software-Selectable
Multiprotocol Transceiver
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FEATURES
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DESCRIPTIO
The LTC®1343 is a 4-driver/4-receiver multiprotocol transceiver that operates from a single 5V supply. Two LTC1343s
form the core of a complete software-selectable DTE or DCE
interface port that supports the RS232, RS449, EIA-530,
EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination
may be implemented using the LTC1344 software-selectable
cable termination chip or by using existing discrete designs.
The LTC1343 runs from a single 5V supply using an internal
charge pump that requires only five space saving surface mount
capacitors. The mode pins are latched internally to allow sharing
of the select lines between multiple interface ports.
Software-selectable echoed clock and loop-back modes help
eliminate the need for external glue logic between the serial
controller and line transceiver. The part features a flowthrough architecture to simplify EMI shielding and is available
in the 44-lead SSOP surface mount package.
Software-Selectable Transceiver Supports:
RS232, RS449, EIA-530, EIA-530-A, V.35, V.36,
X.21
NET1 and NET2 Compliant
Software-Selectable Cable Termination Using
the LTC1344
4-Driver/4-Receiver Configuration Provides a
Complete 2-Chip DTE or DCE Port
Operates from Single 5V Supply
Internal Echoed Clock and Loop-Back Logic
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APPLICATIO S
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Data Networking
CSU and DSU
Data Routers
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
DTE Multiprotocol Serial Interface with DB-25 Connector
CTS
DSR
DCD
DTR
RTS
RL
D3
D2
D1
TM
RXD
RXC
TXC
R3
R4
R2
TXD
LL
D3
D2
D1
LTC1343
LTC1343
D4
SCTE
D4
R1
R3
R4
R2
R1
LTC1344
13 5
22 6
10 8
23 20 19
4
21
1
7
25
16 3
17 12 15
11 24 14 2
18
LL A (141)
TXD A (103)
TXD B
SCTE A (113)
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
TM A (142)
SGND (102)
SHIELD (101)
RL A (140)
RTS A (105)
RTS B
DTR A (108)
DTR B
DCD A (109)
DCD B
DSR A (107)
CTS A (106)
DSR B
CTS B
DB-25 CONNECTOR
9
1343 TA01
1
LTC1343
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W
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W W
W
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
Supply Voltage ....................................................... 6.5V
Input Voltage
Transmitters ........................... – 0.3V to (VCC + 0.3V)
Receivers ............................................... – 18V to 18V
Logic Pins .............................. – 0.3V to (VCC + 0.3V)
Output Voltage
Transmitters ................. (VEE – 0.3V) to (VDD + 0.3V)
Receivers ................................ – 0.3V to (VCC + 0.3V)
Logic Pins .............................. – 0.3V to (VCC + 0.3V)
VEE ........................................................ – 10V to 0.3V
VDD ....................................................... – 0.3V to 10V
Short-Circuit Duration
Transmitter Output ..................................... Indefinite
Receiver Output .......................................... Indefinite
VEE .................................................................. 30 sec
Operating Temperature Range
LTC1343C .............................................. 0°C to 70°C
LTC1343I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TOP VIEW
ORDER PART
NUMBER
44 C2 +
VDD
1
C1+
2
PWRVCC
3
42 VEE
C1–
4
41 PGND
D1
5
40 GND
D2
6
D3
7
VCC
8
D4
9
43 C2 –
CHARGE PUMP
LTC1343CGW
LTC1343IGW
39 D1 A
D1
38 D2 A
D2
37 D2 B
36 D3 A
D3
D4EN 10
35 D3 B
INVERT 11
34 D4 A
D4
R1EN 12
33 D4 B
R1O 13
32 R1 A
R1
R2O 14
31 R1 B
R3O 15
30 R2 A
R2
R4O 16
29 R2 B
M0 17
28 R3 A
R3
M1 18
M2 19
27 R3 B
26 R4 A
R4
CTRL/CLK 20
25 423 SET
DCE/DTE 21
24 EC
LATCH 22
23 LB
GW PACKAGE
44-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 65°C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
VCC Supply Current (DCE Mode,
All Digital Pins = GND or VCC)
V.10 Mode, No Load
V.10 Mode, Full Load
RS530, RS530-A, X.21 Modes, No Load
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode, No Load
V.35 Mode, Full Load
V.28 Mode, No Load
V.28 Mode, Full Load
No-Cable Mode
MIN
TYP
MAX
UNITS
Supplies
ICC
●
●
●
●
PD
Internal Power Dissipation (DCE Mode,
All Digital Pins = GND or VCC)
V.10 Mode, Full Load
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode, Full Load
V.28 Mode, Full Load
V+
Positive Charge Pump Output Voltage
Any Mode, No Load
V.28 Mode, with Load
●
●
V–
Negative Charge Pump Output Voltage
V.28 Mode, Full Load
2
12
80
80
160
20
115
20
30
0.05
●
150
200
160
90
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
400
680
500
150
mW
mW
mW
mW
8.5
8.0
9.1
7.0
V
V
●
– 7.8
– 8.4
V
V.35 Mode, Full Load
– 40°C ≤ TA ≤ 85°C
●
●
– 5.8
– 5.5
– 6.7
V
V
V.10, RS530, RS530A, X.21 Modes, Full Load
– 40°C ≤ TA ≤ 85°C
●
●
– 5.0
– 4.8
– 6.1
V
V
LTC1343
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
tr
Supply Rise Time
No-Cable Mode or Power-Up to Turn On
MIN
TYP
MAX
2
UNITS
ms
Logic Inputs and Outputs
VIH
Logic Input High Voltage
●
2
VIL
Logic Input Low Voltage
●
0.8
V
IIN
Logic Input Current
●
±10
µA
VOH
Output High Voltage
IO = – 4mA
●
VOL
Output Low Voltage
IO = 4mA
●
IOSR
Output Short-Circuit Current
0V ≤ VO ≤ VCC, 0°C ≤ TA ≤ 70°C
0V ≤ VO ≤ VCC, – 40°C ≤ TA ≤ 85°C
●
●
IOZR
Three-State Output Current
M0 = M1 = M2 = VCC, 0V ≤ VO ≤ VCC
VOD
Differential Output Voltage
Open Circuit, RL = 1.95k
RL = 50Ω (Figure 1),
VOD at 50Ω > 1/2 VOD at RL = 1.95k
●
●
∆VOD
Change in Magnitude of Differential
Output Voltage
RL = 50Ω (Figure 1)
VOC
Common Mode Output Voltage
∆VOC
3
V
4.5
0.3
– 60
– 70
V
0.8
V
60
70
mA
mA
±1
µA
V.11 Driver
±6
V
V
●
0.2
V
RL = 50Ω (Figure 1)
●
3.0
V
Change in Magnitude of Common Mode
Output Voltage
RL = 50Ω (Figure 1)
●
0.2
V
ISS
Short-Circuit Current
– 0.25V ≤ VO ≤ 0.25V, Power Off or
No-Cable Mode or Driver Disabled
IOZ
Output Leakage Current
– 0.25V ≤ VO ≤ 0.25V, Power Off or
No-Cable Mode or Driver Disabled
●
t r, t f
Rise or Fall Time
(Figures 2, 6)
●
t PLH
Input to Output
(Figures 2, 6), 0°C ≤ TA ≤ 70°C
(Figures 2, 6), – 40°C ≤ TA ≤ 85°C
t PHL
Input to Output
∆t
t SKEW
±2
±150
mA
±0.01
±100
µA
4
13
25
ns
●
●
25
25
55
55
80
90
ns
ns
(Figures 2, 6), 0°C ≤ TA ≤ 70°C
(Figures 2, 6), – 40°C ≤ TA ≤ 85°C
●
●
25
25
55
55
80
90
ns
ns
Input to Output Difference, tPLH – tPHL
(Figures 2, 6), 0°C ≤ TA ≤ 70°C
(Figures 2, 6), – 40°C ≤ TA ≤ 85°C
●
●
0
0
3
3
17
25
ns
ns
Output to Output Skew
(Figures 2, 6)
3
ns
V.11 Receiver
VTH
Input Threshold Voltage
– 7V ≤ VCM ≤ 7V, 0°C ≤ TA ≤ 70°C
– 7V ≤ VCM ≤ 7V, – 40°C ≤ TA ≤ 85°C
●
●
∆VTH
Input Hysteresis
– 7V ≤ VCM ≤ 7V, 0°C ≤ TA ≤ 70°C
– 7V ≤ VCM ≤ 7V, – 40°C ≤ TA ≤ 85°C
●
●
IIN
Input Current (A, B)
– 10V ≤ VA, B ≤ 10V
●
RIN
Input Impedance
– 10V ≤ VA, B ≤ 10V
●
t r, t f
Rise or Fall Time
(Figures 2, 7)
t PLH
Input to Output
(Figures 2, 7), CTRL = GND, 0°C ≤ TA ≤ 70°C
CTRL = VCC, 0°C ≤ TA ≤ 70°C
●
35
80
400
115
ns
ns
(Figures 2, 7), CTRL = GND, – 40°C ≤ TA ≤ 85°C
CTRL = VCC, – 40°C ≤ TA ≤ 85°C
●
25
80
400
130
ns
ns
– 0.2
– 0.3
15
20
0.2
0.3
V
V
40
60
mV
mV
±0.50
mA
32
kΩ
15
ns
3
LTC1343
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t PHL
Input to Output
(Figures 2, 7), CTRL = GND, 0°C ≤ TA ≤ 70°C
CTRL = VCC, 0°C ≤ TA ≤ 70°C
●
35
80
400
115
ns
ns
(Figures 2, 7), CTRL = GND, –40°C ≤ TA ≤ 85°C
CTRL = VCC, –40°C ≤ TA ≤ 85°C
●
25
80
400
130
ns
ns
Input to Output Difference, tPLH – tPHL
(Figures 2, 7), 0°C ≤ TA ≤ 70°C
(Figures 2, 7), –40°C ≤ TA ≤ 85°C
●
●
0
0
5
5
17
25
ns
ns
Differential Output Voltage
Open Circuit
With Load, – 4.0V ≤ VCM = 4.0V (Figure 3)
●
±0.44
±0.55
6.0
±0.66
V
V
∆t
V.35 Driver
VOD
IOH
Transmitter Output High Current
VA, B = 0V
●
– 12.6
– 11
– 9.4
mA
IOL
Transmitter Output Low Current
VA, B = 0V
●
9.4
11
12.6
mA
IOZ
Transmitter Output Leakage Current
– 0.25V ≤ VA, B ≤ 0.25V
●
±0.01
±100
µA
t r , tf
t PLH
Rise or Fall Time
(Figures 3, 6)
Input to Output
(Figures 3, 6), 0°C ≤ TA ≤ 70°C
(Figures 3, 6), –40°C ≤ TA ≤ 85°C
●
●
25
25
45
45
75
90
ns
ns
t PHL
Input to Output
(Figures 3, 6), 0°C ≤ TA ≤ 70°C
(Figures 3, 6), –40°C ≤ TA ≤ 85°C
●
●
25
25
45
45
75
90
ns
ns
∆t
Input to Output Difference, tPLH – tPHL
(Figures 3, 6), 0°C ≤ TA ≤ 70°C
(Figures 3, 6), –40°C ≤ TA ≤ 85°C
●
●
0
0
5
5
17
25
ns
ns
t SKEW
Output to Output Skew
(Figures 3, 6)
5
ns
4
ns
V.35 Receiver
VTH
Differential Receiver Input
Threshold Voltage
– 2V ≤ (VA + VB)/2 ≤ 2V (Figure 3)
●
∆VTH
Receiver Input Hysteresis
– 2V ≤ (VA + VB)/2 ≤ 2V (Figure 3)
●
IIN
Receiver Input Current (A, B)
– 10V ≤ VA, B ≤ 10V
●
RIN
Receiver Input Impedance
– 10V ≤ VA, B ≤ 10V
●
t r, t f
Rise or Fall Time
(Figures 3, 7)
tPLH
Input to Output
(Figures 3, 7), 0°C ≤ TA ≤ 70°C
(Figures 3, 7), –40°C ≤ TA ≤ 85°C
●
●
80
80
115
130
ns
ns
tPHL
Input to Output
(Figures 3, 7), 0°C ≤ TA ≤ 70°C
(Figures 3, 7), –40°C ≤ TA ≤ 85°C
●
●
100
100
115
130
ns
ns
∆t
Input to Output Difference, tPLH – tPHL
(Figures 3, 7), 0°C ≤ TA ≤ 70°C
(Figures 3, 7), –40°C ≤ TA ≤ 85°C
●
●
4
4
17
25
ns
ns
VO
Output Voltage
Open Circuit, RL = 3.9k
RL = 450Ω (Figure 4)
VO at 450Ω > 0.9 VO at RL = 3.9k
Driver 1 Only
±6.0
V
V
ISS
Short-Circuit Current
VO = GND; EIA-530, X.21, EIA-530-A Modes
±150
mA
IOZ
Output Leakage Current
– 0.25V ≤ VO ≤ 0.25V, Power Off or
No-Cable Mode or Driver Disabled
±100
µA
t r, t f
Rise or Fall Time
(Figures 4, 8), RL = 450Ω, CL = 100pF
R423SET = 100k
4
µs
t PLH
Input to Output
(Figures 4, 8), RL = 450Ω, CL = 100pF
R423SET = 100k
8
µs
t PHL
Input to Output
(Figures 4, 8), RL = 450Ω, CL = 100pF
R423SET = 100k
8
µs
– 0.2
11
20
0.2
V
40
mV
±0.50
mA
32
kΩ
15
ns
V.10 Driver
4
±4.0
±3.6
●
±0.1
LTC1343
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.2
0.3
V
V
V.10 Receiver
VTH
Receiver Input Threshold Voltage
∆VTH
Receiver Input Hysteresis
IIN
Receiver Input Current
RIN
t r, t f
0°C ≤ TA ≤ 70°C
–7V ≤ VCM ≤ 7V, – 40°C ≤ TA ≤ 85°C
●
●
– 0.2
– 0.3
11
●
50
mV
±0.50
mA
– 10V ≤ VA ≤ 10V
●
Receiver Input Impedance
– 10V ≤ VA ≤ 10V
●
30
kΩ
Rise or Fall Time
(Figures 5, 9)
15
ns
t PLH
Input to Output
(Figures 5, 9)
350
ns
t PHL
Input to Output
(Figures 5, 9)
350
ns
Output Voltage
Open Circuit
RL = 3k (Figure 4)
●
20
V.28 Driver
VO
±5
±10
V
V
±150
mA
±100
µA
7.6
ISS
Short-Circuit Current
VO = GND
●
IOZ
Output Leakage Current
– 0.25V ≤ VO ≤ 0.25V, Power Off or
No-Cable Mode or Driver Disabled
●
SR
Slew Rate
(Figures 4, 8), RL = 3k, CL = 2500pF
●
30.0
V/µs
t PLH
Input to Output
(Figures 4, 8), RL = 3k, CL = 2500pF
●
1.6
2.5
µs
t PHL
Input to Output
(Figures 4, 8), RL = 3k, CL = 2500pF
●
1.6
2.5
µs
1.4
0.8
V
±0.01
4.0
V.28 Receiver
VTHL
Input Low Threshold Voltage
●
VTLH
Input High Threshold Voltage
●
2.0
1.4
∆VTH
Receiver Input Hysteresis
●
0.1
0.4
1.0
RIN
Receiver Input Impedance
– 15V ≤ VA ≤ 15V
●
3
5
7
t r, tf
tPLH
Rise or Fall Time
(Figures 5, 9)
Input to Output
(Figures 5, 9), CTRL = 0V
CTRL = VCC
●
110
330
800
ns
ns
(Figures 5, 9), CTRL = 0V
CTRL = VCC
●
170
480
800
ns
ns
tPHL
Input to Output
Note 1: Absolute Maximum Ratings are those beyond which the safety of a
device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.
V
15
V
kΩ
ns
Note 3: All typicals are given for VCC = 5V, C1 = C2 = CVCC = CVDD = 1µF,
CVEE = 3.3µF tantalum capacitors and TA = 25°C.
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PIN FUNCTIONS
VDD (Pin 1): Generated Positive Supply Voltage for
RS232. Connect a 1µF capacitor to ground.
C1 + (Pin 2): Capacitor C1 Positive Terminal. Connect a
1µF capacitor between C1 + and C1 –.
PWRVCC (Pin 3): Positive Supply for the Charge Pump.
4.75V ≤ PWRVCC ≤ 5.25V. Tie to VCC (Pin 8) and bypass
with a 1µF capacitor to ground.
C1 –␣ (Pin 4): Capacitor C1 Negative Terminal.
D1 (Pin 5): TTL Level Driver 1 Input.
D2 (Pin 6): TTL Level Driver 2 Input.
D3 (Pin 7): TTL Level Driver 3 Input. Becomes a CMOS
level output when the chip is in the echoed clock mode
(EC = 0V).
5
LTC1343
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PIN FUNCTIONS
VCC (Pin 8): Positive Supply for the Transceivers. 4.75V ≤
VCC ≤ 5.25V. Tie to PWRVCC (Pin 3).
respective input buffers. The data latch allows the logic
lines to be shared between multiple I/O ports.
D4 (Pin 9): TTL Level Driver 4 Input.
LB (Pin 23): TTL Level Loop-Back Select Input. When low
the chip enters the loop-back configuration and is configured for normal operation when LB is high. The data on LB
is latched when LATCH is high.
D4EN (Pin 10): TTL Level Enable Input for Driver 4. When
high, driver 4 outputs are enabled. When low, driver 4
outputs are forced into a high impedance state. D4EN is
not affected by the LATCH pin.
INVERT (Pin 11): TTL Level Signal Invert Input. When
high, an extra inverter will be added to the driver 4 and
receiver 1 signal path. The data stream will change polarity, i.e., a 1 becomes 0 and a 0 becomes a 1. When the pin
is low the data flows through with no polarity change.
INVERT is not affected by the LATCH pin.
R1EN (Pin 12): Logic Level Enable Input for Receiver 1.
When low, receiver 1 output is enabled. When high,
receiver 1 output is forced into a high impedance state.
R1O (Pin 13): CMOS Level Receiver 1 Output.
R2O (Pin 14): CMOS Level Receiver 2 Output.
R3O (Pin 15): CMOS Level Receiver 3 Output.
R4O (Pin 16): CMOS Level Receiver 4 Output.
M0 (Pin 17): TTL Level Mode Select Input 0. The data on
M0 is latched when LATCH is high.
EC (Pin 24): TTL Level Echoed Clock Select Input. When
low the part enters the echoed clock configuration and is
configured for normal operation when EC is high. The data
on EC is latched when LATCH is high.
423 SET (Pin 25): Analog Input Pin for the RS423 Driver
Output Rise and Fall Time Set Resistor. Connect the
resistor from the pin to ground.
R4 A (Pin 26): Receiver 4 Inverting Input.
R3 B (Pin 27): Receiver 3 Noninverting Input.
R3 A (Pin 28): Receiver 3 Inverting Input.
R2 B (Pin 29): Receiver 2 Noninverting Input.
R2 A (Pin 30): Receiver 2 Inverting Input.
R1 B (Pin 31): Receiver 1 Noninverting Input.
R1 A (Pin 32): Receiver 1 Inverting Input.
D4 B (Pin 33): Driver 4 Noninverting Output.
M1 (Pin 18): TTL Level Mode Select Input 1. The data on
M1 is latched when LATCH is high.
D4 A (Pin 34): Driver 4 Inverting Output.
M2 (Pin 19): TTL Level Mode Select Input 2. The data on
M2 is latched when LATCH is high.
D3 A (Pin 36): Driver 3 Inverting Output.
CTRL/CLK (Pin 20): TTL Level Mode Select Input. When
the pin is low the chip will be configured for clock and data
signals. When the pin is high the chip will be configured for
control signals. The data on CTRL/CLK is latched when
LATCH is high.
DCE/DTE (Pin 21): TTL Level Mode Select Input. When
high, the DCE mode is selected. When low the DTE mode
is selected. The data on DCE/DTE is latched when LATCH
is high.
LATCH (Pin 22): TTL Level Logic Signal Latch Input. When
low the input buffers on M0, M1, M2, CTRL/CLK, DCE/
DTE, LB and EC are transparent. When LATCH is pulled
high the data on the logic pins is latched into their
6
D3 B (Pin 35): Driver 3 Noninverting Output.
D2 B (Pin 37): Driver 2 Noninverting Output.
D2 A (Pin 38): Driver 2 Inverting Output.
D1 A (Pin 39): Driver 1 Inverting Output.
GND (Pin 40): Signal Ground. Connect to PGND (Pin 41).
PGND (Pin 41): Charge Pump Power Ground. Connect to
the GND (Pin 40).
VEE (Pin 42): Generated Negative Supply Voltage. Connect
a 3.3µF capacitor to ground.
C2 – (Pin 43): Capacitor C2 Negative Terminal. Connect a
1µF capacitor between C2 + and C2 –.
C2 + (Pin 44): Capacitor C2 Positive Terminal. Connect a
1µF capacitor between C2 + and C2 – .
LTC1343
TEST CIRCUITS
A
RL
50Ω
B
RL
100Ω
A
VOD
RL
50Ω
CL
100pF
B
CL
100pF
A
R
15pF
VOC
B
1343 F01
1343 F02
Figure 1. RS422 Driver Test Circuit
Figure 2. RS422 Driver/Receiver AC Test Circuit
50Ω
B
D
125Ω
VCM
50Ω
B
125Ω
R
VOD
A
A
15pF
50Ω
50Ω
1343 F03
Figure 3. V.35 Driver/Receiver Test Circuit
D
A
D
A
A
R
RL
CL
15pF
1343 F04
1343 F04
Figure 4. V.10/V.28 Driver Test Circuit
Figure 5. V.10/V.28 Receiver Test Circuit
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ODE SELECTIO
LTC1343 MODE NAME
M2
M1
M0
CTRL/CLK
D1
D2
D3
D4
R1
R2
R3
R4
V.10, RS423
0
0
0
X
V.10
V.10
V.10
V.10
V.10
V.10
V.10
V.10
EIA-530-A Clock and Data
0
0
1
0
V.10
V.11
V.11
V.11
V.11
V.11
V.11
V.10
EIA-530-A Control
0
0
1
1
V.10
V.11
V.10
V.11
V.11
V.10
V.11
V.10
Reserved
0
1
0
X
V.10
V.11
V.11
V.11
V.11
V.11
V.11
V.10
X.21
0
1
1
X
V.10
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.35 Clock and Data
1
0
0
0
V.28
V.35
V.35
V.35
V.35
V.35
V.35
V.28
V.35 Control
1
0
0
1
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
EIA-530, RS449, V.36
1
0
1
X
V.10
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.28, RS232
1
1
0
X
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
No Cable
1
1
1
X
Z
Z
Z
Z
Z
Z
Z
Z
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5V
f = 1MHz : t r ≤ 10ns : t f ≤ 10ns
1.5V
D
0V
1.5V
t PHL
t PLH
B–A
VO
90%
50%
–VO
10%
tr
90%
VDIFF = V(A) – V(B)
50%
1/2 VO
10%
tf
A
VO
B
t SKEW
t SKEW
1343 F06
Figure 6. V.11, V.35 Driver Propagation Delays
VOD2
B–A
–VOD2
f = 1MHz : t r ≤ 10ns : t f ≤ 10ns
0V
INPUT
t PLH
VOH
R
VOL
0V
t PHL
OUTPUT
1.5V
1.5V
1343 F07
Figure 7. V.11, V.35 Receiver Propagation Delays
3V
1.5V
1.5V
D
0V
t PHL
VO
t PLH
3V
3V
0V
A
0V
–3V
–VO
1343 F08
–3V
tf
tr
Figure 8. V.10, V.28 Driver Propagation Delays
VIH
1.7V
1.3V
A
VIL
VOH
R
VOL
t PHL
t PLH
2.4V
0.8V
Figure 9. V.10, V.28 Receiver Propagation Delays
8
1343 F09
LTC1343
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Overview
software-selectable cable termination chip or by using
existing discrete designs.
The LTC1343 is a 4-driver/4-receiver multiprotocol transceiver that operates from a single 5V supply. Two LTC1343s
form the core of a complete software-selectable DTE or
DCE interface port that supports the RS232, RS449,
EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols. Cable
termination may be implemented using the LTC1344
A complete DCE-to-DTE interface operating in EIA-530
mode is shown in Figure 10. The first LTC1343 of each port
is used to generate the clock and data signals along with
LL (Local Loop-back) and TM (Test Mode). The second
LTC1343 is used to generate the control signals along with
DTE
SERIAL
CONTROLLER
LL
LTC1343
DCE
LTC1344
LTC1344
LL
D1
LTC1343
R4
SERIAL
CONTROLLER
LL
TXD
D2
TXD
103Ω
R3
TXD
SCTE
D3
SCTE
103Ω
R2
SCTE
R1
D4
TXC
R1
103Ω
TXC
D4
TXC
RXC
R2
103Ω
RXC
D3
RXC
RXD
R3
103Ω
RXD
D2
RXD
TM
R4
D1
TM
TM
LTC1343
LTC1343
RL
RL
D1
RTS
D2
DTR
D3
R4
RL
RTS
R3
RTS
DTR
R2
DTR
R1
D4
DCD
R1
DCD
D4
DCD
DSR
R2
DSR
D3
DSR
CTS
R3
CTS
D2
CTS
RI
R4
D1
RI
RI
1343 F10
Figure 10. Complete Multiprotocol Interface in EIA-530 Mode
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will configure the port for DCE mode when high, and DTE
when low.
RL (Remote Loop-back) and RI (Ring Indicate). The
LTC1344 cable termination chip is used only for the clock
and data signals because they must support V.35 cable
termination. The control signals do not need any external
resistors.
The interface protocol may be selected simply by plugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable as shown in
Figure 11.
Mode Selection
The interface protocol is selected using the mode select
pins M0, M1, M2 and CTRL/CLK (see the Mode Selection
table). The CTRL/CLK pin should be pulled high if the
LTC1343 is being used to generate control signals and
pulled low if used to generate clock and data signals.
The pull-up resistors R1 through R4 will ensure a binary
1 when a pin is left unconnected and that the two LTC1343s
and the LTC1344 enter the no-cable mode when the cable
is removed. In the no-cable mode the LTC1343 supply
current drops to less than 200µA and all LTC1343 driver
outputs and LTC1344 resistive terminations are forced
into a high impedance state. Note that the data latch pin,
LATCH, is shorted to ground for all chips.
For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.
For the control signals, CTRL/CLK = 1 and the drivers and
receivers will operate in RS232 (V.28) electrical mode. For
the clock and data signals, CTRL/CLK = 0 and the drivers
and receivers will operate in V.35 electrical mode, except
for the single-ended driver and receiver which will operate
in the RS232 (V.28) electrical mode. The DCE/DTE pin
LATCH
The interface protocol may also be selected by the serial
controller or host microprocessor as shown in Figure 12.
The mode selection pins M0, M1, M2 and DCE/DTE can be
shared between multiple interface ports, while each port
21
LTC1344
DCE/
DTE M2
22
23
M1 M0 (DATA)
24
1
CONNECTOR
(DATA)
R1, 10k
LTC1343
M0
17
R2, 10k
20
CTRL/CLK
M1
LATCH
M2
18
R3, 10k
22
19
21
VCC
VCC
NC
R4, 10k
DCE/DTE
VCC
VCC
NC
CABLE
LTC1343
DCE/DTE
M2
VCC
20
22
CTRL/CLK
M1
LATCH
M0
21
19
18
17
(DATA)
Figure 11: Single Port DCE/V.35 Mode Selection in the Cable
10
1343 F11
LTC1343
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APPLICATIONS INFORMATION
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
PORT #1
M1
M2
DCE/DTE
CONNECTOR #1
M0
LATCH
PORT #2
V.10 (RS423) Interface
M2
DCE/DTE
CONTROLLER
CONNECTOR #2
M0
M1
LATCH
M0
M1
M1
M2
M2
DCE/DTE
DCE/DTE
LATCH 1
CONNECTOR #3
PORT #3
M0
Using the LTC1344 along with the LTC1343 solves the
cable termination switching problem. Via software control, the LTC1344 provides termination for the V.10
(RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical
protocols.
A typical V.10 unbalanced interface is shown in Figure 13.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' connected to A, and input B' connected to the signal return
ground C. The receiver’s ground C' is separate from the
signal return. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 14.
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LATCH 2
LATCH 3
LOAD
CABLE
TERMINATION
LATCH
A
A'
C
B'
RECEIVER
1343 F12
Figure 12: Mode Selection by the Controller
has a unique data latch signal which acts as a write enable.
When the LATCH pin is low the buffers on the M0, M1, M2,
CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high the buffers latch the
data and changes on the input pins will no longer affect
the chip.
C'
1343 F13
Figure 13. Typical V.10 Interface
IZ
3.25mA
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or VCC.
Cable Termination
Traditional implementations have included switching resistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head, or separate terminations are built on the board and a custom cable routes
the signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must
–10V
–3V
VZ
3V
10V
1343 F14
–3.25mA
Figure 14. V.10 Receiver Input Impedance
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The V.10 receiver configuration in the LTC1343 and
LTC1344 is shown in Figure 15. In V.10 mode switches S1
and S2 inside the LTC1344 and S3 inside the LTC1343 are
turned off. Switch S4 inside the LTC1343 shorts the
noninverting receiver input to ground so the B input at the
connector can be left floating. The cable termination is
then the 30k input impedance to ground of the LTC1343
V.10 receiver.
V.11 (RS422) Interface
A typical V.11 balanced interface is shown in Figure 16. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.11 interface has a differential termination at the receiver
end that has a minimum value of 100Ω. The termination
resistor is optional in the V.11 specification, but for the
high speed clock and data lines, the termination is required
to prevent reflections from corrupting the data. The re-
ceiver inputs must also be compliant with the impedance
curve shown in Figure 14.
In V.11 mode, all switches are off except S1 inside the
LTC1344 which connects a 103Ω differential termination
impedance to the cable as shown in Figure 17.
V.28 (RS232) Interface
A typical V.28 unbalanced interface is shown in Figure 18.
A. V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with inputs A' connected to A, ground C' connected via the signal return
ground C.
In V.28 mode all switches are off except S3 inside the
LTC1343 which connects a 6k (R8) impedance to ground
in parallel with 20k (R5) plus 10k (R6) for a combined
impedance of 5k as shown in Figure 19. The noninverting
input is disconnected inside the LTC1343 receiver and
connected to a TTL level reference voltage for a 1.4V
receiver trip point.
A'
A'
A
R1
51.5Ω
S1
LTC1344
R8
6k
R2
51.5Ω
R5
20k
R1
51.5Ω
R6
10k
S3
R3
124Ω
S2
R4
20k
B
R7
10k
1343 F15
B'
C
C'
R7
10k
S4
C'
GND
1343 F17
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
A
A'
C
C'
RECEIVER
100Ω
MIN
Figure 16. Typical V.11 Interface
12
B
GENERATOR
A'
B
R4
20k
Figure 17. V.11 Receiver Configuration
LOAD
CABLE
TERMINATION
RECEIVER
S3
B'
Figure 15. V.10 Receiver Configuration
A
R8
6k
R3
124Ω
R2
51.5Ω
GND
GENERATOR
LTC1343
R5
20k
R6
10k
S1
S4
BALANCED
INTERCONNECTING
CABLE
LTC1344
RECEIVER
S2
B'
C'
A
LTC1343
1343 F16
Figure 18. Typical V.28 Interface
1343 F18
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A'
A'
A
R1
51.5Ω
S1
S2
LTC1344
R8
6k
R2
51.5Ω
R5
20k
R1
51.5Ω
R6
10k
S3
R3
124Ω
A
LTC1343
B'
R7
10k
R4
20k
B
B'
GND
1343 F19
Figure 19. V.28 Receiver Configuration
A typical V.35 balanced interface is shown in Figure 20. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T or delta network termination at
the receiver end and the generator end. The receiver
differential impedance measured at the connector must be
100Ω␣ ±10Ω, and the impedance between shorted terminals (A' and B) and ground C' must be 150Ω ±15Ω.
In V.35 mode, both switches S1 and S2 inside the LTC1344
are on, connecting the T network impedance as shown in
Figure 21. Both switches in the LTC1343 are off. The 30k
input impedance of the receiver is placed in parallel with
the T network termination, but does not affect the overall
input impedance significantly.
S4
C'
GND
1343 F21
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals (A
and B) and ground C must be 150Ω ±15Ω. For the
generator termination, switches S1 and S2 are both on and
the top side of the center resistor is brought out to a pin so
it can be bypassed with an external capacitor to reduce
common mode noise as shown in Figure 22.
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground, causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable.
A
LTC1344
GENERATOR
LOAD
CABLE
TERMINATION
A
R7
10k
Figure 21. V.35 Receiver Configuration
V.35 Interface
BALANCED
INTERCONNECTING
CABLE
RECEIVER
S3
R3
124Ω
R2
51.5Ω
S4
C'
R8
6k
R6
10k
S2
B
LTC1343
R5
20k
RECEIVER
S1
R4
20k
LTC1344
V.35 DRIVER
124Ω
51.5Ω
S2
ON
S1
ON
RECEIVER
51.5Ω
A'
B
50Ω
125Ω
125Ω
50Ω
50Ω
C1
100pF
B
B'
C
C'
C
1343 F22
50Ω
Figure 22. V.35 Driver Using the LTC1344
1343 F20
Figure 20. Typical V.35 Interface
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Echoed Clock Mode
Loop-Back
The LTC1343 contains the logic to generate the echoed
clock when using a serial controller with only two clock
pins. Figure 23 shows the chip in both the DTE and DCE
echoed clock in EIA-530 mode. The control signals are not
shown. The echoed clock configuration is selected by
pulling the EC pin low. On the DTE side the transmit clock
TXC receiver output is connected to the echoed clock,
SCTE, driver input. The TXC pin on the serial controller is
configured as an input. On the DCE side, the transmit clock
from the serial controller is used to generate both TXC and
RXC. A phase inverter is placed in the TXC signal path on
both the DTE and DCE side to help correct phase problems
with long cables. If the Invert pin is high, the phase of the
data is inverted.
The LTC1343 contains logic for placing the interface into
a loop-back configuration for testing. Both DTE and DCE
loop-back configurations are supported. Figure 24 shows
a complete DTE interface in the loop-back configuration
with the EC pin pulled high. The loop-back configuration is
selected by pulling the LB pin low. Both the line side and
logic side signals are looped back. The DCE loop-back
configuration is shown in Figure 25.
If the echoed clock mode is selected by pulling EC low, D3
becomes an output and is connected to receiver 2’s output
R3 in DTE mode as shown in Figure 26. In the echoed clock
DCE loop-back mode, driver 4 is connected to driver 3’s
input D3 as shown in Figure 27.
DTE
SERIAL
CONTROLLER
LL
DCE
LTC1343
LTC1344
LTC1344
LTC1343
LL
D1
R4
SERIAL
CONTROLLER
LL
TXD
D2
TXD
103Ω
R3
RXD
TXC
D3
SCTE
103Ω
R2
RXC
R1
D4
INVERT
INVERT
R1
103Ω
TXC
D4
RXC
R2
103Ω
RXC
D3
TXC
RXD
R3
103Ω
RXD
D2
TXD
TM
R4
D1
TM
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
M0
M1
M2
DCE/DTE
LATCH
M0
M1
M2
DCE/DTE
LATCH
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
TM
1
0
1
0
0
1
0
0
1 0 1 0 0
1 0 1 1 0
1
0
1
0
1
1
0
0
1343 F23
Figure 23. EIA-530 Echoed Clock Configuration
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APPLICATIONS INFORMATION
SERIAL
CONTROLLER
LL
LTC1343
LTC1344
D1
LTC1344
LL
LL
LTC1343
R4
SERIAL
CONTROLLER
LL
TXD
D2
TXD
TXD
103Ω
R3
TXD
SCTE
D3
SCTE
SCTE
103Ω
R2
SCTE
D4
R1
RXD
D2
RXD
TM
R4
TM
TM
D1
TM
LATCH
RXD
EC
103Ω
LB
R3
DCE/DTE
RXD
CTRL/CLK
RXC
M2
D3
M1
RXC
M0
RXC
M0
M1
M2
DCE/DTE
LATCH
103Ω
M0
M1
M2
DCE/DTE
LATCH
R2
LATCH
RXC
EC
TXC
LB
D4
DCE/DTE
TXC
CTRL/CLK
TXC
M2
103Ω
M1
R1
M0
TXC
1
0
1
0
0
0
1
0
1 0 1 0 0
1 0 1 1 0
1
0
1
0
1
0
1
0
LTC1343
LTC1343
RL
RL
D2
RTS
D3
DTR
RL
D1
RTS
DTR
R4
RL
RTS
R3
RTS
DTR
R2
DTR
D4
R1
D2
CTS
RI
R4
RI
RI
D1
RI
1
0
1
1
0
0
1
0
Figure 24. Normal DTE Loop-Back
1343 F24
LATCH
CTS
EC
CTS
LB
R3
DCE/DTE
CTS
CTRL/CLK
DSR
M2
D3
M1
DSR
M0
DSR
LATCH
R2
EC
DSR
LB
DCD
DCE/DTE
D4
CTRL/CLK
DCD
M2
DCD
M1
R1
M0
DCD
1343 F25
1
0
1
1
1
0
1
0
Figure 25. Normal DCE Loop-Back
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SERIAL
CONTROLLER
LL
LTC1343
LTC1344
D1
LTC1344
LL
LL
LTC1343
R4
SERIAL
CONTROLLER
LL
TXD
D2
TXD
TXD
103Ω
R3
RXD
TXC
D3
TXCE
SCTE
103Ω
R2
RXC
D4
R1
TXD
TM
R4
TM
TM
D1
TM
LATCH
D2
EC
RXD
LB
RXD
DCE/DTE
103Ω
CTRL/CLK
R3
M2
RXD
M1
TXC
M0
D3
M0
M1
M2
DCE/DTE
LATCH
RXC
M0
M1
M2
DCE/DTE
LATCH
RXC
LATCH
103Ω
EC
R2
LB
RXC
DCE/DTE
D4
CTRL/CLK
TXC
M2
TXC
M1
103Ω
M0
R1
1
0
1
0
0
0
0
0
1 0 1 0 0
1 0 1 1 0
1
0
1
0
1
0
0
0
LTC1343
LTC1343
RL
RL
D2
RTS
D3
DTR
RL
D1
RTS
DTR
R4
RL
RTS
R3
RTS
DTR
R2
DTR
D4
R1
D2
CTS
RI
R4
RI
RI
D1
RI
1
0
1
1
0
0
1
0
Figure 26. Echoed Clock, DTE Loop-Back
16
1343 F26
LATCH
CTS
EC
CTS
LB
R3
DCE/DTE
CTS
CTRL/CLK
DSR
M2
D3
M1
DSR
M0
DSR
LATCH
R2
EC
DSR
LB
DCD
DCE/DTE
D4
CTRL/CLK
DCD
M2
DCD
M1
R1
M0
DCD
1
0
1
1
1
0
1
0
Figure 27. Echoed Clock, DCE Loop-Back
1343 F27
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The no-cable mode (M0 = M1 = M2 = 1) is intended for the
case when the cable is disconnected from the connector.
The charge pump, bias circuitry, drivers and receivers are
turned off, the driver outputs are forced into a high
impedance state, and the supply current drops to less than
200µA. It can also be used to share I/O lines with other
drivers and receivers without loading down the signals.
5V
1
+
C3
1µF
+
+
2
C1
1µF 3
C4
1µF
4
8
44
VDD
C2 +
C1+
43
C2 –
LTC1343
PWRVCC
VEE
C1–
PGND
VCC
GND
+
C2
1µF
42
+
No-Cable Mode
41
C5
3.3µF
40
1343 F28
Charge Pump
Receiver Fail-Safe and Glitch Filter
All LTC1343 receivers feature fail-safe operation in all
modes except no-cable mode. If the receiver inputs are left
floating or shorted together by a termination resistor, the
receiver output will always be forced to a logic high.
External pull-up resistors are required on receiver outputs
if fail-safe operation in the no-cable mode is desired.
When the chip is configured for control signals by pulling
the CTRL/CLK pin high, a glitch filter is connected to all
receiver inputs. The filter will reject any glitches at the
receiver inputs less than 300ns.
Figure 28. Charge Pump
100
DRIVER RISE/FALL TIME (µs)
The LTC1343 uses an internal capacitive charge pump to
generate VDD and VEE as shown in Figure 28. A voltage
doubler generates about 8V on VDD and a voltage inverter
generates about – 7.5V for VEE. Four 1µF surface mounted
tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The VEE capacitor C5 should be a minimum of
3.3µF. All capacitors are 16V.
10
1
0.1
1k
10k
100k
RESISTANCE (Ω)
1M
5M
1343 F29
Figure 29. V.10 Driver Rise and Fall Time vs Resistor Value
V.10 Driver Rise and Fall Times
The rise and fall times of the V.10 drivers is programmed
by placing a 1/8W, 5% resistor between the 423 SET (Pin
25) and ground. The graph of Driver Rise and Fall Times
vs Resistor Value is shown in Figure 29.
LTC1343
5
DCE/DTE
D1
21
16
Enabling the Single-Ended Driver and Receiver
When the LTC1343 is being used to generate the control
signals (CTRL/CLK = high) and the EC pin is pulled low, the
DCE/DTE pin becomes an enable for driver 1 and receiver
4 so their inputs and outputs can be tied together as shown
in Figure 30.
VCC
39
20
24
R4
26
CTRL/CLK
EC
1343 F30
Figure 30. Single-Ended Driver and Receiver Enable
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APPLICATIONS INFORMATION
The EC pin has no affect on the configuration when CTRL/
CLK is high except to allow the DCE/DTE pin to become an
enable. When DCE/DTE is low, the driver 1 output is
enabled. The receiver 4 output goes into three-state and
the input presents a 30kΩ load to ground.
drivers and receivers into a high impedance state. In the
DCE mode, the middle two LTC1343s are enabled and the
top and bottom LTC1343s disabled. With this scheme, any
connector pin can be configured for sending or receiving
signals. Note that only one LTC1344 is required.
When DCE/DTE is high, the driver 1 output goes into threestate and the receiver 4 output is enabled. The receiver 4
input presents a 30kΩ load to ground in all modes except
when configured for RS232 operation when the input
impedance is 5kΩ to ground.
Multiprotocol Interface with Ring-Indicate and a
DB-25 Connector
DTE vs DCE Operation
The DCE/DTE pin does not allow a given LTC1343 pin to be
reconfigured as a driver or receiver. The DCE/DTE pin only
selects the loop-back topology and acts as an enable for
the single-ended driver and receiver for control signals.
However, the LTC1343 can be configured for either DTE or
DCE operation in one of three ways: a dedicated DTE or
DCE port with a connector of appropriate gender, a port
with one connector that can be configured for DTE or DCE
operation by rerouting the signals to the LTC1343 using a
dedicated DTE cable or dedicated DCE cable, or a port with
one connector and one cable using four LTC1343s.
A dedicated DTE port using a DB-25 male connector is
shown in Figure 31. The interface mode is selected by logic
outputs from the controller or from jumpers to either VCC
or GND on the mode select pins. A dedicated DCE port
using a DB-25 female connector is shown in Figure 32.
A port with one DB-25 connector that can be configured
for either DTE or DCE operation is shown in Figure 33. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. For example, in DTE
mode, the TXD signal is routed to connector Pins 2 and 14
via driver 2 in the LTC1343. In DCE mode, driver 2 now
routes the RXD signal to Pins 2 and 14.
A combination DTE/DCE port that doesn’t require separate
DCE/DTE cables is shown in Figure 34. In DTE mode, the
top and bottom LTC1343s are enabled and the middle two
are placed in the no-cable mode, which forces all of the
18
If the RI signal in RS232 mode is implemented, driver 4
and receiver 1 in the control chip can be tied to connector
Pin 22 in order to implement the RI signal in RS232 mode
and DSR B signal for the other modes. Figure 35 shows the
DTE configuration and Figure 36 the DCE configuration. In
DCE mode, the DCE/DTE pin should be driven with a logic
signal from the controller that goes low only when the
interface is in the RS232 mode. Since the receiver 4 input
impedance is greater than 30kΩ in all modes except
RS232, it can be enabled at all other times and not load
down the line. When driver 1 is disabled, it remains in a
high impedance state and does not load the line.
Cable-Selectable Multiprotocol Interface
A cable-selectable multiprotocol DTE/DCE interface is
shown in Figure 37. The control signals LL, RL and TM are
not implemented. The select lines M0, M1 and DCE/DTE
are brought out to the connector. The mode is selected
through the cable by wiring M0 (connector Pin 18), M1
(connector Pin 21) and DCE/DTE (connector Pin 25) to
ground (connector Pin 7) or letting them float. If M0, M1
or DCE/DTE are floating, pull-up resistors R3, R4 and R5
will pull the signals to VCC. The select bit M1 is hard wired
to VCC. When the cable is pulled out, the interface will go
into the no-cable mode.
Multiprotocol Interface with a µDB-26 Connector
The controller-selectable multiprotocol DTE/DCE interface with a standard µDB-26 connector is shown in Figure
38. The RL, LL and TM signals are implemented and RI is
mapped to Pin 26 on the connector. A cable-selectable
version is shown in Figure 39. The TM and RL signals have
been dropped, but LL is still implemented.
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
+
C1
1µF
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
41
8
6
TXD
D4
10
12
13
TXC
R1
14
RXC
R2
15
RXD
R3
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
TM
R1
100k
+
VCC
C11
1µF
C9
1µF
+
C12
1µF
CHARGE
PUMP
14
15
CTS
16
VCC
LATCH
R2
100k
LB
18 17 19 20 22 23 24 1
18
LL A (141)
2
TXD A (103)
14
TXD B
24
SCTE A (113)
11
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
TM A (142)
VCC
7
+ C10
1
SGND (102)
SHIELD (101)
1µF
C13
3.3µF
LTC1343
10
12
13
DSR
24
41
9
DCD
16 15
25
43
42
7
DTR
9 10
26
21
2
6
RTS
7
15
12
17
9
3
16
44
5
RL
6
19
M2
18
M1
17
M0
EC
8
DB-25 MALE
CONNECTOR
32
31
30
29
28
27
1
3
+
DCE
40
GND
23
LB
4
4
38
37
36
35
34
33
D3
9
LATCH
DCE/
DTE M2 M1 M0
5
D2
7
SCTE
2
VEE
C4
3.3µF
39
D1
21
1µF
LTC1343
5
LL
LATCH
+ C2
+
C3
1µF
44
+
+
1
VCC
D1
D2
D3
D4
39
38
37
36
35
34
33
R2
32
31
30
29
R3
28
27
R1
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
24
EC
21
RL A (140)
4 RTS A (105)
19 RTS B
20
DTR A (108)
23
DTR B
8
DCD A (109)
10
DCD B
6
DSR A (107)
22
DSR B
5
CTS A (106)
13
CTS B
1343 F31
40
GND
23
LB
M2
M1
M0
Figure 31: Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
19
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
C1
1µF
+
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
41
8
6
RXD
D2
7
RXC
D3
9
TXC
D4
10
12
13
VCC
R2
15
TXD
LL
R1
100k
+
VCC
C11
1µF C9
1µF
+
27
44
2
43
42
3
+
C12
1µF
41
8
6
7
DSR
9
DCD
10
12
13
VCC
VCC
LATCH
R2
100k
LB
D2
D3
16 15 18 17 19 20 22 23 24 1
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
24
SCTE A (113)
11
SCTE B
2
TXD A (103)
14
TXD B
18 LL A (141)
VCC
VCC
7
+ C10
1 SHIELD (101)
SGND (102)
1µF
C13
3.3µF
D4
28
27
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
40
GND
23
LB
5
13
6
22
8
10
R1
EC
CTS A (106)
CTS B
DSR A (107)
DSR B
DCD A (109)
DCD B
20
DTR A (108)
23
DTR B
4
RTS A (105)
19
RTS B
21
RL A (140)
VCC
24
M2
M1
M0
Figure 32: Controller-Selectable Multiprotocol DCE Port with DB-25 Connector
20
TM A (142)
VCC
35
34
33
R3
16
RL
10
38
37
36
R2
15
CTS
9
39
D1
32
31
30
29
14
DTR
7
LTC1343
5
CTS
24
1
CHARGE
PUMP
6
3
16
17
9
15
12
26
21
DCE
19
M2
18
M1
17
M0
4
4
25
R3
EC
DB-25 FEMALE
CONNECTOR
DCE/
DTE M2 M1 M0
38
37
36
35
34
33
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
40
GND
23
LB
LATCH
39
32
31
30
29
28
R1
14
SCTE
2
VEE
C4
3.3µF
5
D1
21
1µF
LTC1343
5
TM
LATCH
+ C2
+
C3
1µF
44
+
+
1
VCC
1343 F32
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
+
C1
1µF
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
41
8
6
DTE_TXD/DCE_RXD
D2
7
DTE_SCTE/DEC_RXC
D3
9
D4
10
12
13
DTE_TXC/DCE_TXC
R1
14
DTE_RXC/DCE_SCTE
R2
15
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
R1
100k
+
C11
1µF
C9 +
1µF
VCC
C12
1µF
43
42
41
7
DTE_DTR/DCE_DSR
9
10
12
13
DTE_DCD/DCE_DCD
D2
D3
D4
R3
28
27
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
21
DCE
19
M2
18
M1
17
M0
R1
16
VCC
LATCH
R2
100k
LB
18 17 19 20 22 23 24 1
DTE
LL A
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
25 TM A
VCC
7
+ C10
1
DCE
TM A
RXD A
RXD B
RXC A
RXC B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
LL A
SGND
SHIELD
1µF
C13
3.3µF
38
37
36
35
34
33
R2
15
DTE_CTS/DCE_RTS
16 15
39
D1
32
31
30
29
14
DTE_DSR/DCE_DTR
10
LTC1343
6
DTE_RTS/DCE_CTS
24
2
5
DTE_RL/DCE_RL
9
15
12
17
9
3
16
44
8
7
32
31
30
29
28
1
CHARGE
PUMP
6
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
27
4
4
38
37
36
35
34
33
26
21
DCE
19
M2
18
M1
17
M0
EC
DB-25 CONNECTOR
DCE/
DTE M2 M1 M0
18
R3
40
GND
23
LB
LATCH
39
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
3
+
2
VEE
C4
3.3µF
5
D1
21
1µF
LTC1343
5
DTE_LL/DCE_TM
LATCH
+ C2
+
C3
1µF
44
+
+
1
VCC
40
GND
23
LB
21
RL A
4 RTS A
19 RTS B
20
DTR A
23
DTR B
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13
CTS B
RL A
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
26
EC
1343 F33
24
DCE/DTE
M2
M1
M0
Figure 33. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
21
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
LTC1343
5
D1
6
D2
7
21
DCE
9
D3
D4
10
12
39
38
37
36
35
34
33
C6
100pF
C7
100pF
3
8
C8
100pF
11
12 13
LTC1344
13
R2
32
31
30
29
R3
28
27
R1
14
15
DCE/
DTE
5
16
R4
4
6
7
9
10
16 15
18 17 19 20 22
26
DCE/DTE
DB-25 CONNECTOR
LTC1343
5
TM
D1
6
RXD
D2
7
21
DCE
9
RXC
TXC
VCC
D3
D4
10
12
13
15
TXD
16
LL
25
38
37
36
35
34
33
3
16
17
9
15
12
R2
32
31
30
29
R3
28
27
R1
14
SCTE
39
R4
26
7
CTS
DSR
VCC
DCD
DTR
RTS
RL
D1
6
D2
7
21
DCE
9
D3
D4
10
12
13
14
15
16
38
37
36
35
34
33
R2
R3
28
27
R4
26
LTC1343
5
6
7
21
DCE
9
10
12
13
14
15
16
D1
D2
D3
D4
38
37
36
35
34
33
R2
R3
28
27
R4
26
Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25
22
5
13
6
22
8
10
1
CTS A (106)
CTS B
DSR A (107)
DSR B
DCD A (109)
DCD B
SHIELD (101)
20
DTR A (108)
23
DTR B
4
RTS A (105)
19
RTS B
21
RL A (140)
1343 F34
39
32
31
30
29
R1
SGND (102)
39
32
31
30
29
R1
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
24
SCTE A (113)
11
SCTE B
2
TXD A (103)
14
TXD B
18
LL A (141)
LTC1343
5
TM A (142)
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
C1
1µF
+
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
41
8
TXD
D4
10
12
13
TXC
R1
14
RXC
R2
15
RXD
TM
R1
100k
+
C11
1µF
C9
1µF
VCC
+
R3
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
C12
1µF
LATCH
R2
100k
LB
18 17 19 20 22 23 24 1
18
LL A (141)
2
TXD A (103)
14
TXD B
24
SCTE A (113)
11
SCTE B
12
17
9
3
16
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
TM A (142)
VCC
7
+ C10
1 SHIELD (101)
SGND (102)
1µF
C13
3.3µF
40
GND
23
LB
RL A (140)
4 RTS A (105)
19 RTS B
20
DTR A (108)
23
DTR B
38
37
36
D2
D3
35
34
33
D4
R2
32
31
30
29
R3
28
27
R1
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
21
39
D1
8
DCD A (109)
10
DCD B
6
DSR A (107)
22
DSR B/RI A (125)
5
CTS A (106)
13
CTS B
26
16
VCC
16 15
LTC1343
15
RI
24
41
14
CTS
EC
8
10
12
13
DSR
10
19
M2
18
M1
17
M0
CHARGE
PUMP
9
DCD
9
25
43
42
7
DTR
7
26
21
2
6
RTS
6
15
44
5
RL
DB-25 MALE
CONNECTOR
32
31
30
29
28
27
1
3
+
DCE
40
GND
23
LB
4
4
38
37
36
35
34
33
D3
9
LATCH
DCE/
DTE M2 M1 M0
5
D2
7
SCTE
2
VEE
C4
3.3µF
39
D1
6
21
1µF
LTC1343
5
LL
LATCH
+ C2
+
C3
1µF
44
+
+
1
VCC
DCE
21
1343 F35
19
M2
18
M1
17
M0
EC
24
VCC
M2
M1
M0
Figure 35. Controller-Selectable Multiprotocol DTE Port with RI and DB-25 Connector
23
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
C1
1µF
+
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
6
RXD
D2
7
RXC
D3
9
TXC
D4
10
12
13
VCC
LL
R1
100k
+
C11
1µF
+
C9
1µF
VCC
C12
1µF
44
2
43
42
4
CHARGE
PUMP
41
8
6
CTS
7
DSR
9
DCD
VCC
10
12
13
D2
D3
D4
R3
28
27
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
21
DCE
19
M2
18
M1
17
M0
R1
16
RL
VCC
LATCH
R2
100k
10
16 15 18 17 19 20 22 23 24 1
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
24
SCTE A (113)
11
SCTE B
2
TXD A (103)
14
TXD B
18
LL A (141)
VCC
VCC
7
+ C10
1
SGND (102)
SHIELD (101)
1µF
C13
3.3µF
40
GND
23
LB
5
13
6
22
8
10
26
EC
CTS A (106)
CTS B
DSR A (107)
DSR B/RI A (125)
DCD A (109)
DCD B
20
DTR A (108)
23
DTR B
4
RTS A (105)
19
RTS B
21
RL A (140)
RIEN = RS232
24
M2
M1
M0
Figure 36. Controller-Selectable Multiprotocol DCE Port with RI and DB-25 Connector
24
TM A (142)
VCC
38
37
36
35
34
33
R2
15
CTX
9
39
D1
32
31
30
29
14
DTR
7
LTC1343
5
RI
24
1
3
+
EC
6
3
16
17
9
15
12
26
21
DCE
19
M2
18
M1
17
M0
40
GND
23
LB
4
25
R3
15
TXD
DB-25 FEMA;E
CONNECTOR
DCE/
DTE M2 M1 M0
38
37
36
35
34
33
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
R2
LATCH
39
32
31
30
29
28
27
R1
14
SCTE
2
VEE
C4
3.3µF
5
D1
21
1µF
LTC1343
5
TM
LB
41
8
LATCH
+ C2
+
C3
1µF
44
+
+
1
VCC
1343 F36
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
12 13
11
LTC1344
VCC
5V
14
+
C1
1µF
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
41
8
D4
10
12
13
R2
15
DTE_RXD/DCE_TXD
R1
100k
+
C11
1µF
C9
1µF
VCC
+
R3
27
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
40
GND
23
LB
C12
1µF
44
43
42
CHARGE
PUMP
41
8
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
15
12
17
9
3
16
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
7
1
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
SHIELD
VCC
+ C10
1µF
VCC
R3
10k
VCC
R4
10k
VCC
R5
10k
25
C13
3.3µF
21
18
DCE/DTE
M1
M0
39
D1
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
40
GND
23
LB
DCE
RXD A
RXD B
RXC A
RXC B
SGND
VCC
28
27
16
LB
23 24 1
VCC
R3
15
R2
100k
18 17 19 20 22
R2
14
VCC
16 15
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13
CTS B
10
12
13
DTE_CTS/ DCE_RTS
10
32
31
30
29
9
DTE_DSR/DCE_DTR
9
4 RTS A
19 RTS B
20
DTR A
23
DTR B
7
DTE_DCD/DCE_DCD
7
38
37
36
35
34
33
6
DTE_DTR/DCE_DSR
6
LTC1343
5
DTE_RTS/DCE_CTS
24
1
3
+
EC
2
4
4
32
31
30
29
28
R1
14
DTE_RXC/DCE_SCTE
DB-25 CONNECTOR
DCE/
DTE M2 M1 M0
38
37
36
35
34
33
D3
9
DTE_TXC/DCE_TXC
2
VEE
C4
3.3µF
5
D2
7
DTE_SCTE/DEC_RXC
21
39
D1
6
DTE_TXD/DCE_RXD
LATCH
1µF
LTC1343
5
VCC
+ C2
+
C3
1µF
44
+
+
1
D2
D3
D4
R1
24
EC
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
1343 F37
VCC
CABLE WIRING FOR MODE SELECTION
MODE
PIN 18
PIN 21
V.35
PIN 7
PIN 7
EIA-530, RS449,
NC
PIN 7
V.36, X.21
RS232
PIN 7
NC
CABLE WIRING FOR DTE/DCE
SELECTION
MODE
PIN 25
DTE
PIN 7
DCE
NC
Figure 37. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
25
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
11
12 13
LTC1344
VCC
5V
14
C1
1µF
+
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
41
8
6
DTE_TXD/DCE_RXD
D2
7
DTE_SCTE/DEC_RXC
D3
9
D4
10
12
13
DTE_TXC/DCE_TXC
R1
14
DTE_RXC/DCE_SCTE
R2
15
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
R1
100k
+
C11
1µF
+
C9
1µF
VCC
C12
1µF
43
42
41
7
DTE_DTR/DCE_DSR
9
10
12
13
DTE_DCD/DCE_DCD
VCC
LATCH
R2
100k
LB
D2
D3
D4
R3
28
27
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
16
DTE_RI/DCE_RL
18 17 19 20 22 23 24 1
VCC
7
+
1
C10
1µF
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
DCE
TM A
RXD A
RXD B
RXC A
RXC B
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
LL A
SGND
SHIELD
C13
3.3µF
40
GND
23
LB
21
RL A
4 RTS A
19 RTS B
20
DTR A
23
DTR B
R1
EC
24
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5 CTS A
13 CTS B
26
RI A
RI A
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
RL A
1343 F38
VCC
DCE/DTE
M2
M1
M0
Figure 38. Controller-Selectable Multiprotocol DTE/DCE Port with DB-26 Connector
26
DTE
LL A
25 TM A
38
37
36
35
34
33
R2
15
DTE_CTS/DCE_RTS
16 15
39
D1
32
31
30
29
14
DTE_DSR/DCE_DTR
10
LTC1343
6
DTE_RTS/DCE_CTS
24
2
5
DTE_RL/DCE_RI
9
15
12
17
9
3
16
44
8
7
32
31
30
29
28
1
CHARGE
PUMP
6
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
27
4
4
38
37
36
35
34
33
26
21
DCE
19
M2
18
M1
17
M0
EC
µDB-26 CONNECTOR
DCE/
DTE M2 M1 M0
18
R3
40
GND
23
LB
LATCH
39
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
3
+
2
VEE
C4
3.3µF
5
D1
21
1µF
LTC1343
5
DTE_LL/DCE_TM
LATCH
+ C2
+
C3
1µF
44
+
+
1
VCC
LTC1343
U
U
W
U
APPLICATIONS INFORMATION
C6
100pF
C7
100pF
3
C8
100pF
8
12 13
11
LTC1344
VCC
5V
14
C1
1µF
+
44
2
43
42
4
CHARGE
PUMP
3
+
C5
1µF
41
8
DTE_TXD/DCE_RXD
D4
10
12
13
DTE_TXC/DCE_TXC
R3
32
31
30
29
28
27
16
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
R1
14
DTE_RXC/DCE_SCTE
R2
15
DTE_RXD/DCE_TXD
R1
100k
+
C11
1µF
C9
1µF
VCC
+
40
GND
23
LB
C12
1µF
44
43
42
CHARGE
PUMP
41
8
LB
DTE
2
TXD A
14
TXD B
24
SCTE A
11
SCTE B
15
12
17
9
3
16
TXC A
TXC B
RXC A
RXC B
RXD A
RXD B
7
1
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
SHIELD
VCC
+
VCC
C10
1µF
R3
10k
VCC
R4
10k
VCC
R5
10k
25
C13
3.3µF
21
18
DCE/DTE
M1
M0
39
D1
R4
20
CTRL
22
LATCH
11
INVERT
25
423 SET
26
21
DCE
19
M2
18
M1
17
M0
40
GND
23
LB
DCE
RXD A
RXD B
RXC A
RXC B
SGND
VCC
28
27
16
R2
100k
VCC
R3
15
VCC
18 17 19 20 22 23 24 1
R2
14
DTE_CTS/DCE_RTS
16 15
8
DCD A
10
DCD B
6
DSR A
22
DSR B
5
CTS A
13
CTS B
26
LL B
10
12
13
DTE_DSR/DCE_DTR
10
32
31
30
29
9
DTE_DCD/DCE_DCD
9
4 RTS A
19 RTS B
20
DTR A
23
DTR B
7
DTE_DTR/DCE_DSR
7
38
37
36
35
34
33
6
DTE_RTS/DCE_CTS
6
LTC1343
5
DTE_LL/DCE_LL
24
1
3
+
EC
2
4
4
38
37
36
35
34
33
D3
9
µDB-26 CONNECTOR
DCE/
DTE M2 M1 M0
5
D2
7
DTE_SCTE/DEC_RXC
21
39
D1
6
LATCH
1µF
2
VEE
C4
3.3µF
LTC1343
5
VCC
+ C2
+
C3
1µF
+
+
1
D2
D3
D4
R1
24
EC
CTS A
CTS B
DSR A
DSR B
DCD A
DCD B
DTR A
DTR B
RTS A
RTS B
LL B
VCC
1343 F39
CABLE WIRING FOR MODE SELECTION
MODE
PIN 18
PIN 21
V.35
PIN 7
PIN 7
EIA-530, RS449,
NC
PIN 7
V.36, X.21
RS232
PIN 7
NC
CABLE WIRING FOR DTE/DCE
SELECTION
MODE
PIN 25
DTE
PIN 7
DCE
NC
Figure 39. Cable-Selectable Multiprotocol DTE Port with DB-26 Connector
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC1343
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GW Package
44-Lead Plastic SSOP (Wide 0.300)
(LTC DWG # 05-08-1642)
17.805 – 18.059*
(0.701 – 0.711)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
10.160 – 10.414
(0.400 – 0.410)
7.417 – 7.595**
(0.292 – 0.299)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
2.286 – 2.387
(0.090 – 0.094)
2.463 – 2.641
(0.097 – 0.104)
0.254 – 0.406 × 45°
(0.010 – 0.016)
0° – 8° TYP
0.231 – 0.3175
(0.0091 – 0.0125)
0.610 – 1.016
(0.024 – 0.040)
0.800
(0.0315)
BSC
0.127 – 0.292
(0.005 – 0.0115)
0.304 – 0.431
(0.012 – 0.017)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
G44 SSOP 1098
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1321
Dual RS232/RS485 Transceiver
2 RS232 Driver/Receiver Pairs or 2 RS485 Driver/Receiver Pairs
LTC1334
Single 5V RS232/RS485 Multiprotocol Transceiver
2 RS232 Driver/Receiver or 4 RS232 Driver/Receiver Pairs
LTC1344/LTC1344A
Software-Selectable Cable Terminator
Perfect for Terminating the LTC1343
LTC1345
Single Supply V.35 Transceiver
3 Driver/3 Receiver for Data and Clock Signals
LTC1346A
Dual Supply V.35 Transceiver
3 Driver/3 Receiver for Data and Clock Signals
LTC1543
Software-Selectable Multiprotocol Transceiver
3 Driver/3 Receiver for Data and Clock Signals
LTC1544
Software-Selectable Multiprotocol Transceiver
4 Driver/4 Receiver for Control Signals Including LL
LTC1545
Software-Selectable Multiprotocol Transceiver
5 Driver/5 Receiver for Control Signals Including LL, RL, TM
28
Linear Technology Corporation
1343fa LT/TP 0899 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1996