AD AD5450YUJZ-REEL7 8-/10-/12-/14-bit high bandwidth multiplying dacs with serial interface Datasheet

8-/10-/12-/14-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5450/AD5451/AD5452/AD5453
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5450/
AD5451/
AD5452/
AD5453
VREF
R
8-/10-/12-/14-BIT REF
R-2R DAC
RFB
IOUT1
DAC REGISTER
POWER-ON
RESET
INPUT LATCH
SYNC
SCLK
SDIN
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
04587-001
12 MHz multiplying bandwidth
INL of ±0.25 LSB at 8-bit
8-lead TSOT and MSOP packages
2.5 V to 5.5 V supply operation
Pin-compatible 8-/10-/12-/14-bit current output DACs
±10 V reference input
50 MHz serial interface
2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detect
<0.4 µA typical current consumption
Guaranteed monotonic
Qualified for automotive applications
GND
APPLICATIONS
Figure 1.
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5450/AD5451/AD5452/AD54531 are CMOS 8-/10-/12-/
14-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to several applications, including batterypowered applications.
As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics of up to 12 MHz.
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. Upon power-up, the internal shift register
and latches are filled with 0s, and the DAC output is at zero scale.
1
The applied external reference input voltage (VREF) determines
the full-scale output current. These parts can handle ±10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
The AD5450/AD5451/AD5452/AD5453 DACs are available in
small 8-lead TSOT, and the AD5452/AD5453 are also available
in MSOP packages. The AD5453 also comes in 8-lead LFCSP.
The EV-AD5443/46/53SDZ evaluation board is available for
evaluating DAC performance. For more information, see the UG327 evaluation board user guide.
U.S. Patent Number 5,689,257.
Rev. G
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5450/AD5451/AD5452/AD5453
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Section................................................................................ 16
Applications ....................................................................................... 1
Circuit Operation ....................................................................... 16
Functional Block Diagram .............................................................. 1
Single-Supply Applications ....................................................... 18
General Description ......................................................................... 1
Adding Gain ................................................................................ 18
Revision History ............................................................................... 2
Divider or Programmable Gain Element ................................ 19
Specifications..................................................................................... 3
Reference Selection .................................................................... 19
Timing Characteristics ................................................................ 5
Amplifier Selection .................................................................... 19
Absolute Maximum Ratings............................................................ 6
Serial Interface ............................................................................ 21
ESD Caution .................................................................................. 6
Microprocessor Interfacing ....................................................... 22
Pin Configurations and Function Descriptions ........................... 7
PCB Layout and Power Supply Decoupling ........................... 24
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 26
Terminology .................................................................................... 15
Ordering Guide .......................................................................... 27
General Description ....................................................................... 16
Automotive Products ................................................................. 27
REVISION HISTORY
6/13—Rev. F to Rev. G
Change to General Description Section ........................................ 1
Change to Figure 56 and Figure 57 .............................................. 22
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
4/12—Rev. E to Rev. F
Changes to General Description Section ...................................... 1
Deleted Evaluation Board for the DAC Section, Power Supplies
for the Evaluation Board Section, and Figure 64;
Renumbered Sequentially.............................................................. 25
Deleted Figure 65 and Figure 66 ................................................... 26
Deleted Figure 67 ............................................................................ 27
Changes to Ordering Guide .......................................................... 27
3/11—Rev. D to Rev. E
Changes to SYNC Function Section ............................................ 21
Added Figure 54 (Renumbered Sequentially) ............................ 21
Added Figure 55 and Table 11 ..................................................... 22
2/11—Rev. C to Rev. D
Added 8-Lead LFCSP ......................................................... Universal
Changes to Features Section............................................................ 1
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
Added Automotive Products Section .......................................... 28
1/10—Rev. B to Rev. C
Changes to DAC Control Bits C1, C0 .......................................... 21
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
3/06—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Specifications .................................................................4
Changes to Figure 27 and Figure 28............................................. 11
Change to Table 9 ........................................................................... 20
Changes to Table 12 ....................................................................... 26
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
7/05—Rev. 0 to Rev. A
Added AD5453 ................................................................... Universal
Changes to Specifications .................................................................4
Change to Figure 21 ....................................................................... 10
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
1/05—Revision 0: Initial Version
Rev. G | Page 2 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise
noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
AD5450
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
AD5451
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
AD5452
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
AD5453
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error
Gain Error
Gain Error Temperature Coefficient 1
Output Leakage Current
REFERENCE INPUT1
Reference Input Range
VREF Input Resistance
RFB Feedback Resistance
Input Capacitance
Zero-Scale Code
Full-Scale Code
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH
Min
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
Max
Unit
Test Conditions
8
±0.25
±0.5
±0.5
±0.25
Bits
LSB
LSB
LSB
LSB
Guaranteed monotonic
10
±0.25
±0.5
±0.5
±0.25
Bits
LSB
LSB
LSB
LSB
Guaranteed monotonic
12
±0.5
±1
±1
±0.5
Bits
LSB
LSB
LSB
LSB
Guaranteed monotonic
14
±2
−1/+2
±4
±2.5
±1
±10
Bits
LSB
LSB
LSB
LSB
ppm FSR/°C
nA
nA
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000, TA = −40°C to +125°C, IOUT1
±10
9
9
11
11
V
kΩ
kΩ
Input resistance, TC = −50 ppm/°C
Input resistance, TC = −50 ppm/°C
18
18
22
22
pF
pF
±2
7
7
2.0
1.7
Input Low Voltage, VIL
Output High Voltage, VOH
Typ
0.8
0.7
VDD − 1
VDD − 0.5
0.4
0.4
±1
±10
10
V
V
V
V
V
V
V
V
nA
nA
pF
Rev. G | Page 3 of 28
Guaranteed monotonic
VDD = 3.6 V to 5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
TA = 25°C
TA = −40°C to +125°C
AD5450/AD5451/AD5452/AD5453
Parameter
DYNAMIC PERFORMANCE1
Reference-Multiplying BW
Multiplying Feedthrough Error
Min
Data Sheet
Typ
Max
Unit
Test Conditions
12
MHz
72
64
44
dB
dB
dB
VREF = ±3.5 V, DAC loaded with all 1s
VREF = ±3.5 V, DAC loaded with all 0s
100 kHz
1 MHz
10 MHz
VREF = 10 V, RLOAD = 100 Ω; DAC latch alternately
loaded with 0s and 1s
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
IOUT1
100
24
16
20
10
2
IOUT2
Digital Feedthrough
Analog THD
Digital THD
50 kHz fOUT
20 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz fOUT
20 kHz fOUT
SFDR Performance (Narrow Band)
50 kHz fOUT
20 kHz fOUT
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range
IDD
110
40
33
40
30
13
28
18
5
0.5
pF
pF
pF
pF
nV-s
83
dB
71
77
25
dB
dB
nV/√Hz
78
74
dB
dB
Interface delay time
Rise and fall times, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
DAC latches loaded with all 0s
DAC latches loaded with all 1s
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, VREF = 3.5 V
@ 1 kHz
Clock = 1 MHz, VREF = 3.5 V
Clock = 1 MHz, VREF = 3.5 V
87
85
79
2.5
5.5
10
0.6
0.001
0.4
Power Supply Sensitivity1
1
ns
ns
ns
ns
ns
nV-s
dB
dB
dB
f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
V
µA
µA
%/%
TA = −40°C to +125°C, logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or VDD
∆VDD = ±5%
Guaranteed by design and characterization, not subject to production test.
Rev. G | Page 4 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
Update Rate
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Description
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
Consists of cycle time, SYNC high time, data setup, and
output voltage settling time
Guaranteed by design and characterization, not subject to production test.
t1
SCLK
t2
t8
t3
t7
t4
SYNC
t6
t5
DIN
DB15
DB0
Figure 2. Timing Diagram
Rev. G | Page 5 of 28
04587-002
1
VDD = 2.5 V to 5.5 V
50
20
8
8
8
5
4.5
5
30
2.7
AD5450/AD5451/AD5452/AD5453
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREF, RFB to GND
IOUT1 to GND
Input Current to Any Pin Except Supplies
Logic Inputs and Output 1
Operating Temperature Range, Extended
(Y Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
8-Lead MSOP
8-Lead TSOT
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
1
Rating
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
±10 mA
−0.3 V to VDD + 0.3 V
−40°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−65°C to +150°C
150°C
206°C/W
211°C/W
300°C
235°C
Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes.
Rev. G | Page 6 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SYNC 4
8
IOUT1
7
GND
6
SCLK
SDIN
5
IOUT1 1
GND 2
SCLK 3
SDIN 4
Figure 3. 8-Lead TSOT Pin Configuration
GND 2
SCLK 3
8
AD5452/
AD5453
SDIN 4
TOP VIEW
(Not to Scale)
8 RFB
7 VREF
6 VDD
5 SYNC
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
RFB
7
VREF
6
VDD
5
SYNC
Figure 5. 8-Lead LFCSP Pin Configuration
04587-004
IOUT1 1
AD5453
04587-205
VDD 3
AD5450/
AD5451/
AD5452/
AD5453
04587-003
RFB 1
VREF 2
Figure 4. 8-Lead MSOP Pin Configuration
Table 4. Pin Function Descriptions
TSOT
1
Pin No 1
MSOP LFCSP
8
8
Mnemonic
RFB
2
3
4
7
6
5
7
6
5
VREF
VDD
SYNC
5
4
4
SDIN
6
3
3
SCLK
7
8
N/A
2
1
N/A
2
1
EPAD
GND
IOUT1
EPAD
1
Description
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
DAC Reference Voltage Input.
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge
of the serial clock input. Alternatively, by means of the serial control bits, the device can be
configured such that data is clocked into the shift register upon the rising edge of SCLK.
Ground Pin.
DAC Current Output.
Exposed pad must be connected to ground.
N/A = not applicable.
Rev. G | Page 7 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
0.25
TA = 25°C
VREF = 10V
VDD = 5V
1.2
0.10
0.8
0.05
0.4
0
–0.05
0
–0.4
–0.10
–0.8
–0.15
–1.2
–0.20
–0.25
32
64
96
128
160
192
224
04587-023
INL (LSB)
0.15
0
TA = 25°C
VREF = 10V
VDD = 5V
1.6
04587-020
INL (LSB)
0.20
–1.6
–2.0
0
256
2048
4096
6144
Figure 6. INL vs. Code (8-Bit DAC)
0.5
TA = 25°C
VREF = 10V
VDD = 5V
0.3
0.10
0.2
0.05
0.1
DNL (LSB)
0.15
0
–0.05
0
–0.1
–0.2
–0.15
–0.3
04587-021
–0.10
–0.20
–0.25
0
128
TA = 25°C
VREF = 10V
VDD = 5V
0.4
256
384
512
640
768
896
04587-024
0.20
INL (LSB)
10240 12288 14336 16384
Figure 9. INL vs. Code (14-Bit DAC)
0.25
–0.4
–0.5
0
1024
32
64
96
128
160
192
224
256
896
1024
CODE
CODE
Figure 7. INL vs. Code (10-Bit DAC)
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
0.5
TA = 25°C
VREF = 10V
VDD = 5V
0.3
0.2
0.2
0.1
0.1
DNL (LSB)
0.3
0
–0.1
0
–0.1
–0.2
–0.3
–0.3
04587-022
–0.2
–0.4
–0.5
0
512
TA = 25°C
VREF = 10V
VDD = 5V
0.4
1024
1536
2048
2560
3072
2584
04587-025
0.4
INL (LSB)
8192
CODE
CODE
–0.4
–0.5
0
4096
128
256
384
512
640
768
CODE
CODE
Figure 8. INL vs. Code (12-Bit DAC)
Figure 11. DNL vs. Code (10-Bit DAC)
Rev. G | Page 8 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
2.0
1.0
TA = 25°C
VREF = 10V
VDD = 5V
0.8
TA = 25°C
VDD = 5V
AD5452
1.5
0.6
1.0
MAX DNL
0.5
0.2
DNL (LSB)
DNL (LSB)
0.4
0
–0.2
0
MIN DNL
–0.5
–0.4
–1.0
–0.6
–1.0
0
512
1024
1536
2048
2560
3072
2584
04587-071
–1.5
04587-026
–0.8
–2.0
4096
2
3
4
CODE
Figure 12. DNL vs. Code (12-Bit DAC)
9
10
224
256
896
1024
Figure 15. DNL vs. Reference Voltage
2.0
0.5
TA = 25°C
VREF = 10V
VDD = 5V
0.3
0.8
0.2
0.4
0.1
TUE (LSB)
1.2
0
–0.4
0
–0.1
–0.2
–1.2
–0.3
04587-027
–0.8
–1.6
–2.0
0
2048
TA = 25°C
VREF = 10V
VDD = 5V
AD5450
0.4
4096
6144
8192
04587-030
1.6
DNL (LSB)
5
6
7
8
REFERENCE VOLTAGE (V)
–0.4
–0.5
10240 12288 14336 16384
0
32
64
96
CODE
128
160
192
CODE
Figure 13. DNL vs. Code (14-Bit DAC)
Figure 16. TUE vs. Code (8-Bit DAC)
1.00
0.25
TA = 25°C
VDD = 5V
AD5452
0.75
TA = 25°C
VREF = 10V
VDD = 5V
AD5451
0.20
0.15
0.50
MAX INL
0.10
TUE (LSB)
0
MIN INL
–0.25
0.05
0
–0.05
–0.10
–0.50
–1.00
2
3
4
5
6
7
8
REFERENCE VOLTAGE (V)
9
04587-031
–0.15
–0.75
04587-070
INL (LSB)
0.25
–0.20
–0.25
10
0
128
256
384
512
640
768
CODE
Figure 14. INL vs. Reference Voltage
Figure 17. TUE vs. Code (10-Bit DAC)
Rev. G | Page 9 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
1.0
0.3
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.2
0.6
GAIN ERROR (LSB)
0.2
0
–0.2
–0.4
–0.6
0.1
VDD = 3V
VDD = 5V
0
–0.1
04587-032
–0.2
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
2584
04587-073
TUE (LSB)
0.4
–0.3
–60
4096
–40
20
40
0
60
TEMPERATURE (°C)
–20
CODE
Figure 18. TUE vs. Code (12-Bit DAC)
80
100
120
140
9
10
Figure 21. Gain Error (LSB) vs. Temperature
2.0
2.0
TA = 25°C
VREF = 10V
VDD = 5V
1.6
TA = 25°C
VDD = 5V
AD5452
1.5
1.2
1.0
GAIN ERROR (LSB)
INL (LSB)
0.8
0.4
0
–0.4
–0.8
0.5
0
–0.5
–1.0
–1.2
–2.0
0
2048
4096
6144
8192
04587-074
–1.5
04587-033
–1.6
–2.0
10240 12288 14336 16384
2
3
4
CODE
Figure 19. TUE vs. Code (14-Bit DAC)
Figure 22. Gain Error (LSB) vs. Reference Voltage
2.0
2.0
TA = 25°C
VDD = 5V
AD5452
1.5
IOUT1 VDD = 5V
1.6
1.0
IOUT1 LEAKAGE (nA)
MAX TUE
0.5
0
MIN TUE
–0.5
–1.0
IOUT1 VDD = 3V
1.2
0.8
–2.0
2
3
4
5
8
6
7
REFERENCE VOLTAGE (V)
9
0
–40
10
04587-039
0.4
–1.5
04587-072
TUE (LSB)
5
8
6
7
REFERENCE VOLTAGE (V)
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 20. TUE vs. Reference Voltage
Figure 23. IOUT1 Leakage Current vs. Temperature
Rev. G | Page 10 of 28
120
Data Sheet
AD5450/AD5451/AD5452/AD5453
1.8
2.5
TA = 25°C
TA = 25°C
1.6
VIH
1.5
1.0
VDD = 5V
04587-038
0.5
VDD = 3V
0
0
1
2
3
4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5
5
3.0
3.5
INPUT VOLTAGE (V)
ALL 1s
ALL 0s
0
0.6
5.0
5.5
–10
GAIN (dB)
VDD = 5V
0.4
0.3
TA = 25°C
LOADING
ZS TO FS
ALL ON
DB13
DB12
0.5
–20
DB11
DB10
–30
DB9
DB8
–40
DB7
DB6
–50
DB5
0.2
–70
04587-037
0.1
0
–40
–20
0
20
DB4
DB3
–60
VDD = 3V
40
80
60
100
DB2
–80
10k
120
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
100k
1M
10M
04587-108
CURRENT (µA)
4.5
10
0.7
100M
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 25. Supply Current vs. Temperature
0.6
TA = 25°C
AD5452
LOADING 010101010101
5
4.0
VOLTAGE (V)
Figure 27. Threshold Voltage vs. Supply Voltage
Figure 24. Supply Current vs. Logic Input Voltage
6
VIL
1.4
04587-076
THRESHOLD VOLTAGE (V)
CURRENT (mA)
2.0
0.4
0
3
GAIN (dB)
4
VDD = 5V
2
–0.2
–0.4
–0.6
VDD = 3V
0
1
10
100
1k
10k
100k
1M
–1.0
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
–1.2
10k
10M
100k
04587-109
–0.8
1
04587-075
CURRENT (mA)
0.2
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29. Reference Multiplying Bandwidth—All 1s Loaded
Figure 26. Supply Current vs. Update Rate
Rev. G | Page 11 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
3
10
TA = 25°C
VDD = 5V
TA = 25°C
VDD = 3V
AD8038 AMPLIFIER
0
–10
0
–20
PSRR (dB)
GAIN (dB)
–30
–3
–40
FULL SCALE
–50
–60
100k
ZERO SCALE
–70
= ±2V, AD8038 C COMP = 1pF
= ±2V, AD8038 C COMP = 1.5pF
= ±15V, AD8038 C COMP = 1pF
= ±15V, AD8038 C COMP = 1.5pF
= ±15V, AD8038 C COMP = 1.8pF
–80
1M
10M
04587-082
–9
10k
VREF
VREF
VREF
VREF
VREF
04587-079
–6
–90
–100
100M
1
10
100
1k
FREQUENCY (Hz)
THD + N (dB)
–0.06
75
100
125
150
–85
175
200
225
04587-083
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nVs
50
–75
–80
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nVs
04587-080
–90
100
250
1k
100k
Figure 34. THD + Noise vs. Frequency
Figure 31. Midscale Transition, VREF = 0 V
100
–1.66
TA = 25°C
VDD = 3.5V
AD8038 AMPLIFIER
CCOMP = 1.8pF
VDD = 5V
0x7FF TO 0x800
NRG = 2.154nVs
–1.68
VDD = 3V
0x7FF TO 0x800
NRG = 1.794nVs
MCLK = 1MHz
SFDR (dB)
–1.70
–1.72
–1.74
–1.76
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nVs
VDD = 5V
0x800 TO 0x7FF
NRG = 0.694nVs
–1.78
–1.80
50
75
100
125
150
MCLK = 200kHz
MCLK = 500kHz
80
60
40
20
04587-081
OUTPUT VOLTAGE (V)
10k
FREQUENCY (Hz)
TIME (ns)
175
200
225
250
TA = 25°C
VREF = ±3.5V
AD8038 AMPLIFIER
04587-084
OUTPUT VOLTAGE (V)
–70
0
–0.04
TA = 25°C
VDD = 5V
VREF = ±3.5V
–65
0.02
–0.02
10M
–60
TA = 25°C
VDD = 0V
AD8038 AMPLIFIER
CCOMP = 1.8pF
VDD = 3V
0x7FF TO 0x800
NRG = 1.794nVs
0.04
1M
Figure 33. Power Supply Rejection Ratio vs. Frequency
0.08
0.06
100k
FREQUENCY (Hz)
Figure 30. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
VDD = 5V
0x7FF TO 0x800
NRG = 2.154nVs
10k
0
0
10
20
30
40
fOUT (kHz)
TIME (ns)
Figure 32. Midscale Transition, VREF = 3.5 V
Figure 35. Wideband SFDR vs. fOUT Frequency
Rev. G | Page 12 of 28
50
Data Sheet
AD5450/AD5451/AD5452/AD5453
0
0
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
–20
–40
–60
–60
–80
–100
–100
04587-085
–80
–120
0
100k
200k
300k
400k
–120
10k
500k
04587-087
SFDR (dB)
–40
SFDR (dB)
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
–20
15k
Figure 36. Wideband SFDR, fOUT = 20 kHz, Clock = 1 MHz
25k
30k
Figure 38. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz
0
0
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
–20
TA = 25°C
VDD = 5V
VREF = 3.5V
AD8038 AMPLIFIER
–20
–40
–40
–60
–60
–80
–100
–100
04587-086
–80
–120
0
100k
200k
300k
400k
–120
30k
500k
FREQUENCY (Hz)
04587-088
SFDR (dB)
SFDR (dB)
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
40k
50k
60k
70k
FREQUENCY (Hz)
Figure 37. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz
Figure 39. Narrow-Band SFDR , fOUT = 50 kHz, Clock = 1 MHz
Rev. G | Page 13 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
80
0
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
–10
TA = 25°C
AD8038 AMPLIFIER
70
IMD (dB)
–40
–50
–60
–70
60
FULL SCALE
LOADED TO DAC
50
40
MIDSCALE
LOADED TO DAC
30
20
–80
–100
10k
15k
20k
25k
30k
0
100
35k
FREQUENCY (Hz)
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
–20
IMD (dB)
–30
–40
–50
–60
–70
04587-090
–80
–90
–100
100k
200k
300k
10k
100k
FREQUENCY (Hz)
0
0
1k
Figure 42. Output Noise Spectral Density
Figure 40. Narrow-Band IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
–10
ZERO SCALE
LOADED TO DAC
10
04587-089
–90
400k
500k
FREQUENCY (Hz)
Figure 41. Wideband IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz
Rev. G | Page 14 of 28
04587-091
OUTPUT NOISE (nV/ Hz)
–20
–30
1M
Data Sheet
AD5450/AD5451/AD5452/AD5453
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the IOUT pins. This
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Differential Nonlinearity
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temperature
range ensures monotonicity.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
VREF − 1 LSB. Gain error of the DACs is adjustable to zero with
external resistance.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as
second to fifth, are included.
Output Leakage Current
The current that flows into the DAC ladder switches when it is
turned off. For the IOUT1 terminal, it can be measured by loading
all 0s to the DAC and measuring the IOUT1 current.
Output Capacitance
Capacitance from IOUT1 to AGND.
Output Current Settling Time
The amount of time it takes for the output to settle to a specified
level for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground. The settling time specification
includes the digital delay from the SYNC rising edge to the fullscale output change.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s, depending
on whether the glitch is measured as a current or voltage signal.
THD = 20 log
V 2 2 + V3 2 + V 4 2 + V5 2
V1
Digital Intermodulation Distortion (IMD)
Second-order intermodulation measurements are the relative
magnitudes of the fa and fb tones generated digitally by the
DAC and the second-order products at 2fa − fb and 2fb − fa.
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Spurious-Free Dynamic Range (SFDR)
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
or fS/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
Rev. G | Page 15 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
GENERAL DESCRIPTION
DAC SECTION
The AD5450/AD5451/AD5452/AD5453 are 8-/10-/12-/14-bit
current output DACs, respectively, consisting of a segmented
(4-bit) inverting R-2R ladder configuration. A simplified
diagram for the 12-bit AD5452 is shown in Figure 43.
R
R
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
VDD
VDD
R
VREF
VREF
2R
2R
2R
2R
S1
S2
S3
S12
VREF
R1
2R
R2
AD5450/
AD5451/
AD5452/
AD5453
C1
RFB
IOUT1
A1
GND
VOUT = 0 TO –VREF
SYNC SCLK SDIN
R
RFB
AGND
IOUT1
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 43. AD5452 Simplified Ladder
The feedback resistor, RFB, has a value of R. The value of R is
typically 9 kΩ (with a minimum value of 7 kΩ and a maximum
value of 11 kΩ). If IOUT1 is kept at the same potential as GND, a
constant current flows in each ladder leg, regardless of digital
input code. Therefore, the input resistance presented at VREF is
always constant and nominally of value R. The DAC output
(IOUT1) is code-dependent, producing various resistances and
capacitances. When choosing the external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
Access is provided to the VREF, RFB, and IOUT1 terminals of the
DAC, making the device extremely versatile and allowing it to be
configured in several operating modes; for example, it can provide
a unipolar output or can provide 4-quadrant multiplication in
bipolar mode. Note that a matching switch is used in series with
the internal RFB feedback resistor. If users attempt to measure
RFB, power must be applied to VDD to achieve continuity.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide a 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 44. When an output amplifier
is connected in unipolar mode, the output voltage is given by
VOUT = −
04587-009
AGND
04587-060
µCONTROLLER
DAC DATA LATCHES
AND DRIVERS
Figure 44. Unipolar Mode Operation
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used by
the internal digital logic to drive the on and off states of the
DAC switches.
These DACs are designed to accommodate ac reference input
signals in the range of −10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 44 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between the digital code and
the expected output voltage for a unipolar operation using the
8-bit AD5450.
Table 5. Unipolar Code Table for the AD5450
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
D
× V REF
2n
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
= 0 to 16,383 (14-bit AD5453).
n is the number of bits.
Rev. G | Page 16 of 28
Analog Output (V)
−VREF (255/256)
−VREF (128/256) = −VREF/2
−VREF (1/256)
−VREF (0/256) = 0
Data Sheet
AD5450/AD5451/AD5452/AD5453
Bipolar Mode
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. Table 6 shows the relationship between the
digital code and the expected output voltage for a bipolar
operation using the 8-bit AD5450.
In some applications, it may be necessary to generate a full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 45. In
this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from Code 0 (VOUT = − VREF) to midscale
(VOUT − 0 V ) to full scale (VOUT = +VREF).
Table 6. Bipolar Code Table for the AD5450
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
+VREF (127/128)
0
−VREF (127/128)
−VREF (128/128)
D
VOUT =  VREF × n −1  − VREF
2 

where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
n is the resolution of the DAC.
R3
20kΩ
VDD
VDD
VREF
±10V
VREF
R1
R5
20kΩ
R2
AD5450/
AD5451/
AD5452/
AD5453
C1
RFB
IOUT1
A1
R4
10kΩ
A2
GND
VOUT = –VREF TO +VREF
SYNC SCLK SDIN
AGND
Figure 45. Bipolar Mode Operation (4-Quadrant Multiplication)
Rev. G | Page 17 of 28
04587-010
µCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
AD5450/AD5451/AD5452/AD5453
Data Sheet
Stability
Positive Output Voltage
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and −2.5 V, respectively, as shown in Figure 47.
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 46 shows these DACs operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin, and
the output voltage is available at the VREF terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at a constant impedance (the
DAC ladder resistance); therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code;
therefore, the voltage input should be driven from a low
impedance source.
VDD
RFB
VIN
R1
R2
VDD
IOUT1
VOUT
VREF
GND
VIN
VOUT
GND
+5V
VDD
–2.5V
C1
RFB
IOUT1
VREF
VOUT = 0V TO +2.5V
GND
–5V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04587-012
An optional compensation capacitor, C1, can be added in parallel
with RFB for stability, as shown in Figure 44 and Figure 45. Too
small a value of C1 can produce ringing at the output, and too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
VDD = +5V
ADR03
Figure 47. Positive Output Voltage with Minimum Components
ADDING GAIN
In applications in which the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. It is important
to consider the effect of the temperature coefficients of the
DAC’s thin film resistors. Simply placing a resistor in series
with the RFB resistor causes mismatches in the temperature
coefficients and results in larger gain temperature coefficient
errors. Instead, increase the gain of the circuit by using the
recommended configuration shown in Figure 48. R1, R2, and
R3 should have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains greater than 1
are required.
04587-011
VDD
VDD
Figure 46. Single-Supply Voltage-Switching Mode
VIN
It is important to note that with this configuration VIN is limited
to low voltages because the switches in the DAC ladder do not
have the same source-drain drive voltage. As a result, their on
resistance differs, which degrades the integral linearity of the
DAC. Also, VIN must not go negative by more than 0.3 V, or an
internal diode turns on, causing the device to exceed the
maximum ratings. In this type of application, the full range of
multiplying capability of the DAC is lost.
R1
C1
RFB
IOUT1
VREF
VOUT
R3
GND
R2
GAIN =
R2 + R3
R2
R2R3
R1 =
NOTES
R2 + R3
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Rev. G | Page 18 of 28
Figure 48. Increasing Gain of Current-Output DAC
04587-013
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Data Sheet
AD5450/AD5451/AD5452/AD5453
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
REFERENCE SELECTION
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
resistor as shown in Figure 49, the output voltage is inversely
proportional to the digital input fraction, D.
When selecting a reference for use with this series of currentoutput DACs, pay attention to the reference’s output voltage
temperature coefficient specification. This parameter not only
affects the full-scale error, but also may affect the linearity (INL
and DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
For example, an 8-bit system is required to hold its overall
specification to within 1 LSB over the temperature range 0°C to
50°C, and the system’s maximum temperature drift should be
less than 78 ppm/°C.
For D = 1 − 2−n, the output voltage is
VOUT =
−V IN
−V IN
=
(1 − 2 −n )
D
As D is reduced, the output voltage increases. For small values
of the digital fraction, D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (00010000), that is, 16 decimal, in the circuit of Figure 49
should cause the output voltage to be 16 times VIN.
AMPLIFIER SELECTION
VDD
VIN
RFB
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the variable
gain of the circuit due to the code-dependent output resistance of
the DAC. A change in this noise gain between two adjacent digital
fractions produces a step change in the output voltage due to the
offset voltage of the amplifier’s input. This output voltage change
is superimposed on the desired change in output between the two
codes and gives rise to a differential linearity error, which if
large enough, could cause the DAC to be nonmonotonic.
VDD
IOUT1
A 12-bit system within 2 LSB accuracy requires a maximum
drift of 10 ppm/°C. Choosing a precision reference with a low
output temperature coefficient minimizes this error source.
Table 7 lists some dc references available from Analog Devices
that are suitable for use with this range of current-output DACs.
VREF
GND
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
04587-014
VOUT
Figure 49. Current-Steering DAC Used as a Divider or
Programmable Gain Element
However, if the DAC has a linearity specification of ±0.5 LSB, D
can have weight anywhere in the range of 15.5/256 to 16.5/256.
Therefore, the possible output voltage is in the range of 15.5 VIN
to 16.5 VIN—an error of 3%, even though the DAC itself has a
maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current in the VREF terminal is
routed to the IOUT1 terminal, the output voltage changes as follows:
Output Error Voltage Dueto Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain
(that is, 1/D) of 16, the error voltage is 1.6 mV.
The input bias current of an op amp generates an offset at the
voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent significant errors in 12-bit applications.
However, for 14-bit applications, some consideration should be
given to selecting an appropriate amplifier.
Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolutions.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration, it
is important to minimize capacitance at the VREF node (the voltage
output node in this application) of the DAC. This is done by using
low input-capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. There is a large range of single-supply amplifiers
available from Analog Devices.
Rev. G | Page 19 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
Table 7. Suitable ADI Precision References
Part No.
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
Output Voltage (V)
10
10
5
5
2.5
2.5
3
3
2.5
5
2.5
5
Initial Tolerance (%)
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
Temp Drift (ppm/°C)
3
9
3
9
3
9
3
9
3
3
9
9
ISS (mA)
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
Output Noise (µV p-p)
20
20
10
10
6
6
10
10
3.5
8
5
8
Package
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
Table 8. Suitable ADI Precision Op Amps
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
±2 to ±20
±2.5 to ±15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (µV)
25
60
5
50
5
IB (Max) (nA)
0.1
2
0.05
0.001
0.1
0.1 Hz to 10 Hz
Noise (µV p-p)
0.5
0.4
1
2.3
0.5
Supply Current (µA)
600
500
975
50
850
Package
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
TSOT, SOIC-8
Table 9. Suitable ADI High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
5 to 24
±2.5 to ±12
3 to 12
±3 to ±6
BW @ ACL (MHz)
145
490
350
320
Slew Rate (V/µs)
180
120
425
1300
Rev. G | Page 20 of 28
VOS (Max) (µV)
1500
1000
3000
10000
IB (Max) (nA)
0.006
10500
750
7000
Package
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
Data Sheet
AD5450/AD5451/AD5452/AD5453
SERIAL INTERFACE
The AD5450/AD5451/AD5452/AD5453 have an easy-to-use
3-wire interface that is compatible with SPI, QSPI, MICROWIRE,
and most DSP interface standards. Data is written to the device in
16-bit words. This 16-bit word consists of two control bits and 8,
10, 12, or 14 data bits, as shown in Figure 50, Figure 51, Figure 52,
and Figure 53. The AD5453 uses all 14 bits of DAC data, the
AD5452 uses 12 bits and ignores the two LSBs, the AD5451 uses
10 bits and ignores the four LSBs, and the AD5450 uses 8 bits
and ignores the six LSBs.
Control Bits C1 and C0 allow the user to load and update the
new DAC code and to change the active clock edge. By default,
the shift register clocks data upon the falling edge; this can be
changed via the control bits. If changed, the DAC core is
inoperative until the next data frame, and a power recycle is
required to return it to active on the falling edge. A power cycle
resets the core to default condition. On-chip power-on reset
circuitry ensures that the device powers on with zero scale
loaded to the DAC register and IOUT line.
Table 10. DAC Control Bits
•
Loading 0x3FFF (a complete data sequence) will update
the output to 10 V (full scale).
User intends to write 0x3200 but after 12 active edges
SYNC goes high (incomplete write sequence). This will
actually update the following code: 0xF200.
The user expects an output of 5.6 V. However, if SYNC
goes high after 12 valid clock edges then an incomplete
data sequence of 12 bits is loaded. To complete the shift
register the 4 LSBs from the previous sequence are taken
and used as the 4 MSBs missing. The addition of these
4 bits will put the part in rising edge mode and the output
will show no change. Figure 54, Figure 55, and Table 11
show the data frames for this example.
•
Also note that if more then 16-bits are loaded to the part before
SYNC goes high the last 16-bits will be latched.
DB15 (MSB)
C1
C0
DB0 (LSB)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
X
X
X
X
04587-005
Function Implemented
Load and update (power-on default)
Reserved
Reserved
Clock data to shift register upon rising edge
DATA BITS
CONTROL BITS
Figure 50. AD5450 8-Bit Input Shift Register Contents
DB15 (MSB)
After the falling edge of the 16th SCLK pulse, bring SYNC high
to transfer data from the input shift register to the DAC register.
DB0 (LSB)
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
X
X
DATA BITS
CONTROL BITS
Figure 51. AD5451 10-Bit Input Shift Register Contents
DB15 (MSB)
C1
C0
DB0 (LSB)
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
04587-007
SYNC is an edge-triggered input that acts as a framesynchronization signal and chip enable. Data can only be
transferred to the device while SYNC is low. To start the serial
data transfer, SYNC should be taken low, observing the
minimum SYNC falling to SCLK falling edge setup time, t4. To
minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
upon the falling edge of SYNC. The SCLK and SDIN input
buffers are powered down upon the rising edge of SYNC.
C0
04587-006
C1
DATA BITS
CONTROL BITS
Figure 52. AD5452 12-Bit Input Shift Register Contents
DB15 (MSB)
C1
C0
DB0 (LSB)
DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
04587-008
SYNC Function
DATA BITS
CONTROL BITS
Figure 53. AD5453 14-Bit Input Shift Register Contents
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
DATA BITS
CONTROL BITS
Figure 54. AD5453 First Write, Complete Data Sequence (0x3FFF)
Rev. G | Page 21 of 28
1
04587-054
C0
0
1
0
1
For example,
•
DAC Control Bits C1, C0
C1
0
0
1
1
The serial interface to the AD5450 uses a 16-bit shift register.
Take care to avoid incomplete data sequences as these will be
latched to update the DAC output.
AD5450/AD5451/AD5452/AD5453
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
DATA BITS
0
0
0
0
0
0
0
0
0
DATA BITS
CONTROL BITS
04587-055
0
Data Sheet
CONTROL BITS
INTENDED DATA FRAME
ACTUAL DATA FRAME
Figure 55. AD5453 Second Write, Incomplete Data Sequence (0x3200) and Subsequent Additional Bits (0xF200)
Table 11.
Writing
Sequence
1
Data Write in
Shift Register
0x3FFF
Action Expected
Load and update 0x3FFF
Data Transfer to
the Device
0x3FFF
Action Carried Out
Load and update 0x3FFF
2
0x3200
Load and update 0x3200
0xF200
Clock data to shift register upon rising edge (0xF200)
Table 12. SPORT Control Register Setup
SCLK
04587-100
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 56. ADSP-2191M SPI-to-AD5450/AD5451/AD5452/AD5453 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 57. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
output takes place upon the rising edge of the SYNC signal.
SCLK
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame SYNC delay and frame SYNC setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC interface
expects a t4 (SYNC falling edge to SCLK falling edge setup time)
of 13 ns minimum. See the ADSP-21xx User Manual for information on clock and frame SYNC frequencies for the SPORT
register. Table 12 shows the setup for the SPORT control register.
SYNC
SCK
SDIN
Figure 57. ADSP-2101/ADSP-2191Mto-AD5450/AD5451/AD5452/AD5453 Interface
AD5450/AD5451/
AD5452/AD5453*
MOSI
SYNC
DT
*ADDITIONAL PINS OMITTED FOR CLARITY
The ADSP-21xx family of DSPs is easily interfaced to a AD5450/
AD5451/AD5452/AD5453 DAC without the need for extra glue
logic. Figure 56 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial data line,
SDIN. SYNC is driven from one of the port lines, in this case
SPIxSEL.
SPIxSEL
TFS
SCLK
ADSP-21xx-to-AD5450/AD5451/AD5452/AD5453
Interface
ADSP-2191M*
AD5450/AD5451/
AD5452/AD5453*
ADSP-2101/
ADSP-2191M*
Microprocessor interfacing to a AD5450/AD5451/AD5452
/AD5453 DAC is through a serial bus that uses standard protocol
and is compatible with microcontrollers and DSP processors.
The communication channel is a 3-wire interface consisting of
a clock signal, a data signal, and a synchronization signal. The
AD5450/AD5451/AD5452/AD5453 require a 16-bit word, with
the default being data valid upon the falling edge of SCLK, but
this is changeable using the control bits in the data-word.
04587-051
MICROPROCESSOR INTERFACING
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
Setting
1
1
00
1
1
1
1111
Description
Alternate framing
Active low frame signal
Right justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453
Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPIcompatible devices. A serial interface between the BlackFin®
processor and the AD5450/AD5451/AD5452/AD5453 DAC is
shown in Figure 58. In this configuration, data is transferred
through the MOSI (master output, slave input) pin. SYNC is
driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
Rev. G | Page 22 of 28
AD5450/AD5451/AD5452/AD5453
MOSI
SCK
TxD
SDIN
RxD
SDIN
SCLK
P1.1
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 58. ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453 Interface
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 59. When the SPORT is
enabled, initiate transmission by writing a word to the Tx register.
The data is clocked out upon each rising edge of the DSP’s serial
clock and clocked into the DAC’s input shift register upon the
falling edge its SCLK. The DAC output is updated by using the
transmit frame synchronization (TFS) line to provide a SYNC
signal.
AD5450/AD5451/
AD5452/AD5453*
TFS
SYNC
DT
SDIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-103
ADSP-BF5xx*
SCLK
SYNC
04587-102
SPIxSEL
AD5450/AD5451/
AD5452/AD5453*
8051*
Figure 59. ADSP-BF5xx SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
80C51/80L51-to-AD5450/AD5451/AD5452/AD5453
Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 60. 80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface
MC68HC11-to-AD5450/AD5451/AD5452/AD5453
Interface
Figure 61 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5450/AD5451/AD5452/AD5453,
the SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid upon the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
AD5450/AD5451/
AD5452/AD5453*
MC68HC11*
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 60. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and is used
to drive SYNC. As data is transmitted to the switch, P1.1 is taken
low. The 80C51/80L51 transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller upon the rising edge of TxD and is valid upon
the falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P1.1 is taken high following
the completion of this cycle. The 80C51/80L51 provide the LSB
of its SBUF register as the first bit in the data stream. The DAC
input register acquires its data with the MSB as the first bit received.
The transmit routine should take this into account.
PC7
SYNC
SCK
SCLK
MOSI
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-105
AD5450/AD5451/
AD5452/AD5453*
ADSP-BF5xx*
04587-104
Data Sheet
Figure 61. MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11. In this configuration with SYNC low, the shift
register clocks data out upon the rising edges of SCLK.
Rev. G | Page 23 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
MICROWIRE-to-AD5450/AD5451/AD5452/AD5453
Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
Figure 62 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
SK
SCLK
SO
SDIN
CS
SYNC
04587-106
AD5450/AD5451/
AD5452/AD5453*
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 62. MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface
PIC16C6x/PIC16C7x-toAD5450/AD5451/AD5452/AD5453 Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller
User Manual.
In this example, I/O Port RA1 is used to provide a SYNC signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 63 shows the connection diagram.
AD5450/AD5451/
AD5452/AD5453*
SCK/RC3
SCLK
SDI/RC4
SDIN
RA1
SYNC
04587-107
PIC16C6x/PIC16C7x*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 63. PIC16C6x/7x-to-AD5450/AD5451/AD5452/AD5453 Interface
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which a
AD5450/AD5451/AD5452/AD5453 DAC is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast switching signals
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
Rev. G | Page 24 of 28
Data Sheet
AD5450/AD5451/AD5452/AD5453
Table 13. Overview of AD54xx and AD55xx Devices
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
1
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL (LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package 1
RU-16, CP-20
RM-10
RU-20
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
UJ-8
RM-10
RM-10
RU-24
CP-40
RU-20, CP-20
RU-24
RU-16
UJ-8, RM-8
RM-10
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. G | Page 25 of 28
Features
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHZ BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
12 MHz BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial interface
12 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 n WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
AD5450/AD5451/AD5452/AD5453
Data Sheet
OUTLINE DIMENSIONS
2.90 BSC
8
7
6
5
1
2
3
4
2.80 BSC
1.60 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
*0.90
0.87
0.84
*1.00 MAX
0.10 MAX
0.38
0.22
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
SEATING
PLANE
*COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 64. 8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-8)
Dimensions shown in millimeters
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 65. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. G | Page 26 of 28
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Data Sheet
AD5450/AD5451/AD5452/AD5453
0.35
0.30
0.25
0.65 BSC
8
5
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
BOTTOM VIEW
0.80 MAX
0.55 NOM
0.80
0.75
0.70
SEATING
PLANE
1
4
TOP VIEW
0.05 MAX
0.02 NOM
0.20 REF
2.48
2.38
2.23
0.20 MIN
PIN 1
INDICATOR
(R 0.2)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
3.10
3.00 SQ
2.90
Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD5450YUJZ-REEL
AD5450YUJZ-REEL7
AD5451YUJZ-REEL
AD5451YUJZ-REEL7
AD5452YUJZ-REEL
AD5452YUJZ-REEL7
AD5452YRM
AD5452YRM-REEL
AD5452YRMZ
AD5452YRMZ-REEL
AD5452YRMZ-REEL7
AD5453WBCPZ-RL
AD5453YUJZ-REEL
AD5453YUJZ-REEL7
AD5453YRM
AD5453YRM-REEL
AD5453YRM-REEL7
AD5453YRMZ
AD5453YRMZ-REEL
AD5453YRMZ-REEL7
EV-AD5443/46/53SDZ
1
2
Resolution
8
8
10
10
12
12
12
12
12
12
12
14
14
14
14
14
14
14
14
14
INL
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±2
±2
±2
±2
±2
±2
±2
±2
±2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead TSOT
8-Lead TSOT
8-Lead TSOT
8-Lead TSOT
8-Lead TSOT
8-Lead TSOT
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead LFCSP_WD
8-Lead TSOT
8-Lead TSOT
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Evaluation Board
Package Option
UJ-8
UJ-8
UJ-8
UJ-8
UJ-8
UJ-8
RM-8
RM-8
RM-8
RM-8
RM-8
CP-8-3
UJ-8
UJ-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
D6Y
D6Y
D6Z
D6Z
D70
D70
D1Z
D1Z
D70
D70
D70
DG3
DAH
DAH
D26
D26
D26
DAH
DAH
DAH
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD5453WBCPZ-RL model is available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. G | Page 27 of 28
AD5450/AD5451/AD5452/AD5453
Data Sheet
NOTES
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04587-0-6/13(G)
Rev. G | Page 28 of 28