MC10EP105, MC100EP105 3.3V / 5VECL Quad 2−Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS* Features MCxxx EP105 AWLYYWWG • 275 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V LQFP−32 FA SUFFIX CASE 873A with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V • • • with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs Pb−Free Packages are Available* 1 1 32 QFN32 MN SUFFIX CASE 488AM xxx A WL, L YY, Y WW, W G or G MCxxx EP105 AWLYYWWG G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 11 1 Publication Order Number: MC10EP105/D MC10EP105, MC100EP105 D0b D1a D1a D1b D1b D2a D2a D2b D0b D1a D1a D1b D1b D2a D2a D2b 24 23 22 21 20 19 18 24 17 23 22 21 20 19 18 17 D0b 25 16 D2b D0b 25 16 D2b D0a 26 15 D3a D0a 26 15 D3a D0a 27 14 D3a D0a 27 14 D3a VEE 28 13 VCC VEE 28 13 VCC Q0 29 12 D3b Q0 29 12 D3b Q0 30 11 D3b Q0 30 11 D3b VCC 31 10 VEE VCC 31 10 VEE VCC 32 9 NC VCC 32 9 NC MC10EP105 MC100EP105 1 2 3 4 5 6 7 8 Exposed Pad (EP) 1 2 3 4 5 6 7 8 VCC Q1 Q1 Q2 Q2 Q3 Q3 VCC VCC Q1 Q1 Q2 Q2 Q3 Q3 VCC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32−Lead LQFP Pinout (Top View) D0a Figure 2. 32−Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION Q0 D0a D0b D0b Q0 D1a Q1 D1a D1b D1b FUNCTION PIN Q1 Dna*, Dnb*, Dna*, Dnb* ECL Data Inputs Qn, Qn ECL Data Outputs VCC Positive Supply VEE Negative Supply NC No Connect * Pins will default LOW when left open. D2a Q2 D2a D2b D2b Table 2. TRUTH TABLE Q2 D3a Q3 D3a D3b D3b Q3 Dna Dnb Dna L L H H L H L H H H L L VEE Figure 3. Logic Diagram http://onsemi.com 2 Dnb Qn Qn H L H L L L L H H H H L MC10EP105, MC100EP105 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP−32 QFN−32 Flammability Rating Pb Pkg Pb−Free Pkg Level 2 − Level 2 Level 1 Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in Transistor Count 444 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 32 LQFP 32 LQFP 80 55 °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 32 LQFP 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 32 QFN 32 QFN 31 27 °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P 32 QFN 12 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free VI ≤ VCC VI ≥ VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 MC10EP105, MC100EP105 Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 58 75 45 59 75 45 60 75 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 3. All loading with 50 W to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP105, MC100EP105 Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 58 75 45 59 75 45 60 75 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 0.5 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 6. All loading with 50 W to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8) −40°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 45 58 75 45 59 75 45 60 75 mA VOH Output HIGH Voltage (Note 9) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 9) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 150 0.5 0.0 VEE+2.0 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC − 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC10EP105, MC100EP105 Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 59 80 45 62 85 45 65 85 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 12) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 12) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 12. All loading with 50 W to VCC − 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 45 63 80 45 66 85 45 69 85 mA VOH Output HIGH Voltage (Note 15) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note15) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 15. All loading with 50 W to VCC − 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 MC10EP105, MC100EP105 Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17) −40°C Symbol Characteristic VCC = −3.3 V VCC = −5.0 V 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 45 59 63 80 80 45 45 62 66 85 85 45 45 65 69 85 85 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 18) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 18) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 0.0 150 0.5 VEE+2.0 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 W to VCC − 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20) −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 4 Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential tSKEW Min Typ 25°C Max Min >3 175 85°C Max Min >3 250 325 Within Device Skew Device to Device Skew (Note 21) 10 tJITTER Cycle−to−Cycle Jitter (See Figure 4 Fmax/JITTER) VPP Input Voltage Swing (Differential Configuration) tr tf Output Rise/Fall Times (20% − 80%) Q Typ 200 Typ Max >3 275 350 50 10 0.2 <1 150 800 1200 100 150 200 225 Unit GHz 300 375 ps 50 15 50 ps 0.2 <1 0.2 <1 ps 150 800 1200 150 800 1200 mV 120 170 220 150 200 250 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 21. Skew is measured between outputs under identical transitions. http://onsemi.com 7 1000 10 900 9 800 8 700 7 600 6 500 5 400 4 300 3 200 100 0 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 2 (JITTER) 0 1000 2000 1 3000 4000 JITTER OUT ps (RMS) VOUTpp (mV) MC10EP105, MC100EP105 ÉÉ ÉÉ 5000 FREQUENCY (MHz) Figure 4. Fmax/Jitter Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 8 MC10EP105, MC100EP105 ORDERING INFORMATION Package Shipping † MC10EP105FA LQFP−32 250 Units / Tray MC10EP105FAG LQFP−32 (Pb−Free) 250 Units / Tray MC10EP105FAR2 LQFP−32 2000 / Tape & Reel MC10EP105FAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel MC100EP105FA LQFP−32 250 Units / Tray MC100EP105FAG LQFP−32 (Pb−Free) 250 Units / Tray MC100EP105FAR2 LQFP−32 2000 / Tape & Reel MC100EP105FAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel Device MC10EP105MNG MC100EP105MNG MC10EP105MNR4G 74 Units / Rail 74 Units / Rail QFN−32 (Pb−Free) 1000 / Tape & Reel MC100EP105MNR4G 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 9 MC10EP105, MC100EP105 PACKAGE DIMENSIONS 32 A1 A −T−, −U−, −Z− 32 LEAD LQFP CASE 873A−02 ISSUE C 4X 25 0.20 (0.008) AB T−U Z 1 AE −U− −T− B P V 17 8 BASE METAL DETAIL Y V1 AC T−U Z AE DETAIL Y ÉÉ ÉÉ ÉÉ ÉÉ 9 −Z− S1 4X 0.20 (0.008) AC T−U Z F S 8X M_ D DETAIL AD G −AB− SECTION AE−AE C E −AC− H W K X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X http://onsemi.com 10 MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF Q_ 0.250 (0.010) 0.10 (0.004) AC GAUGE PLANE SEATING PLANE J R M N 9 0.20 (0.008) B1 MC10EP105, MC100EP105 PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O A B D ÉÉ PIN ONE LOCATION 2X 0.15 C 2X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 32 X 0.08 C C L 32 X 9 D2 SEATING PLANE A1 SIDE VIEW MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 −−− −−− 0.300 0.400 0.500 EXPOSED PAD 16 SOLDERING FOOTPRINT* K 32 X 17 5.30 8 3.20 E2 32 X 1 0.63 24 32 25 b 0.10 C A B 32 X e 3.20 5.30 0.05 C BOTTOM VIEW 32 X 0.28 28 X 0.50 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10EP105/D