CA3304, CA3304A ® November 2002 T ODUC DUC T TE PR E E P RO a t L T O U S IT T OB S ter B LE SU Support Cen /tsc IB S S O l m P a o FOR A our Technic ww.intersil.c t c w a r t o n IL co NT E RS 1-888-I 4-Bit, 25 MSPS, Flash A/D Converters Features Description • • • • The Intersil CA3304 is a CMOS parallel (FLASH) analog-todigital converter designed for applications demanding both low-power consumption and high speed digitization. Digitizing at 25MHz, for example, requires only about 35mW. • • • • • CMOS/SOS Low Power with Video Speed (Typ) . . 25mW Parallel Conversion Technique Single Power Supply Voltage . . . . . . . . . . . 3V to 7.5V 25MHz Sampling Rate (40ns Conversion Time) at 5V Supply 4-Bit Latched Three-State Output with Overflow and Data Change Outputs 1/ LSB Maximum Nonlinearity (A Version) 8 Inherent Resistance to Latch-Up Due to SOS Process Bipolar Input Range with Optional Second Supply Wide Input Bandwidth (Typ) . . . . . . . . . . . . . . . . 25MHz The CA3304 operates over a wide, full-scale signal input voltage range of 0.5V up to the supply voltage. Power consumption is as low as 10mW, depending upon the clock frequency selected. The intrinsic high conversion rate makes the CA3304 types ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3304s in series to increase the resolution of the conversion system. A series connection of two CA3304s may be used to produce a 5-bit, 25MHz converter. Operation of two CA3304s in parallel doubles the conversion speed (i.e., increases the sampling rate from 25MHz to 50MHz). A data change pin indicates when the present output differs from the previous, thus allowing compaction of data storage. Applications • • • • • • • • • • High Speed A/D Conversion Ultrasound Signature Analysis Transient Signal Analysis High Energy Physics Research General-Purpose Hybrid ADCs Optical Character Recognition Radar Pulse Analysis Motion Signature Analysis Robot Vision RSSI Circuits Sixteen paralleled auto-balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel-bit outputs in the CA3304. Fifteen comparators are required to quantize all input voltage levels in this 4-bit converter, and the additional comparator is required for the overflow bit. Part Number Information PART NUMBER LINEARITY (INL, DNL) SAMPLING RATE TEMP. RANGE (oC) 25MHz (40ns) -40 to 85 PACKAGE PKG. NO. CA3304E ±0.25 LSB CA3304AE ±0.125 LSB 25MHz (40ns) -40 to 85 16 Ld PDIP E16.3 CA3304M ±0.25 LSB 25MHz (40ns) -40 to 85 16 Ld SOIC (W) M16.3 CA3304AM ±0.125 LSB 25MHZ (40ns) -40 to 85 16 Ld SOIC (W) M16.3 CA3304D ±0.25 LSB 25MHz (40ns) -55 to 125 16 Ld SBDIP D16.3 CA3304AD ±0.125 LSB 25MHz (40ns) -55 to 125 16 Ld SBDIP D16.3 16 Ld PDIP E16.3 Pinout CA3304 (SBDIP, PDIP, SOIC) TOP VIEW BIT 1 (LSB) 1 16 VDD BIT 2 2 15 CLK BIT 3 3 14 VAA- BIT 4 4 13 VREF - DATA CHANGE (DC) 5 12 VREF + OVERFLOW (OF) 6 11 VIN CE2 7 10 VAA+ VSS 8 9 CE1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 1 FN1790.3 CA3304, CA3304A Absolute Maximum Ratings Thermal Information DC Supply Voltage Range (VDD or VAA+) (Voltage Referenced to VSS or VAA- Terminal, Whichever is More Negative) . . . . . . . . . . . . . . . . . . -0.5V to +8V Input Voltage Range CE1, CE2 Inputs . . . . . . . . . . . . . . . . . . . VSS -0.5V to VDD +0.5V Clock, VREF+, VREF-, VIN Inputs . . . . . VAA- -0.5V to VAA- +0.5V DC Input Current, Any Input . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . . . 80 22 PDIP Package . . . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package. . . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Recommended Supply Voltage Range (VDD or VAA+). . . . . 3V to 7.5V Recommended VAA+ Voltage Range. . . . . . VDD -1V to VDD +2.5V Recommended VAA- Voltage Range . . . . . . . VSS -2.5V to VSS +1V Operating Temperature CA3304D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CA3304E, CA3304M. . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VREF+ = 2V, VDD = VAA+ = 5V, VAA- = VREF - = VSS = GND, fCLK = 25MHz Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution Input Errors 4 - - Bits Integral Linearity Error CA3304A - ±0.1 ±0.125 LSB CA3304 - ±0.125 ±0.25 LSB Differential Linearity Error CA3304A - ±0.1 ±0.125 LSB CA3304 - ±0.125 ±0.25 LSB Offset Error (Unadjusted) CA3304A - - ±0.75 LSB CA3304 - - ±1.0 LSB Gain Error (Unadjusted) CA3304A - - ±0.75 LSB CA3304 - - ±1.0 LSB - 3 - ns DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Conversion Timing Aperture Delay Signal to Noise Ratio, SNR RMS Signal = RMS Noise fS = 25MHz, fIN = 100kHz - 23.7 - dB fS = 25MHz, fIN = 5MHz - 23.6 - dB Signal to Noise Ratio, SINAD RMS Signal = RMS Noise + Distortion fS = 25MHz, fIN = 100kHz - 23.4 - dB fS = 25MHz, fIN = 5MHz - 22.8 - dB Total Harmonic Distortion, THD fS = 25MHz, fIN = 100kHz - -34.5 - dBc fS = 25MHz, fIN = 5MHz - -31.0 - dBc fS = 25MHz, fIN = 100kHz - 3.67 - Bits fS = 25MHz, fIN = 5MHz - 3.57 - Bits 0.5 - VAA V - 10 - pF - 150 200 µA Effective Number of Bits, ENOB ANALOG INPUTS Input Range Full Scale Input Range Input Loading Input Capacitance Input Current (Notes 1, 4) VIN = 2V (Note 2) 2 CA3304, CA3304A Electrical Specifications TA = 25oC, VREF+ = 2V, VDD = VAA+ = 5V, VAA- = VREF - = VSS = GND, fCLK = 25MHz Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS Allowable Input Bandwidth (Note 4) -3dB Input Bandwidth MIN TYP MAX UNITS - 25 fCLK/2 MHz - 40 - MHz REFERENCE INPUTS Input Range Input Loading VREF+ Range (Note 4) VAA+0.5 - VAA+ V VREF- Range (Note 4) VAA- - VAA+ 0.5 V Resistor Ladder Impedance VIN = 5V, CLK = Low 640 - 960 Ω Maximum VIN, Low CLOCK (Notes 3, 4) - - 0.3 x VAA V CE1, CE2 (Note 4) - - 0.3 x VDD V CLOCK (Notes 3, 4) 0.7 x VAA - - V CE1, CE2 (Note 4) 0.7 x VDD - - V DIGITAL INPUTS Digital Input Minimum VIN, High Input Leakage, Except CLK V = 0V, 5V - - ±1 µA Input Leakage, CLK (Note 3) - ±100 ±150 µA DIGITAL OUTPUTS Digital Outputs Output Low (Sink) Current VO = 0.4V 6 - - mA Output High (Source) Current VO = 4.6V -3 - - mA Three-State Leakage Current VO = 0V, 5V - ±0.2 ±5 µA 25 35 - MSPS 20 - - ns TIMING CHARACTERISTICS Conversion Timing Maximum Conversion Speed CLK = Square Wave Auto-Balance Time (φ1) Sample Time (φ2) Output Timing 20 - 5000 ns Data Valid Delay (Note 4) - 30 40 ns Data Hold Time (Note 4) 15 25 - ns Output Enable Time - 15 - ns Output Disable Time - 10 - ns Continuous Clock - 5.5 - mA Continuous φ2 - 0.4 - mA POWER SUPPLY CHARACTERISTICS Device Current, IAA Device Current, IDD VAA+ = 5V, VSS = CE1 = VAA- = CLK = GND VAA+ = 7V Continuous φ1 - 2 - mA Continuous Clock - 1.5 - mA Continuous φ2 - 5 10 mA Continuous φ1 - 5 20 mA NOTES: 1. Full scale input range, VREF + - VREF -, may be in the range of 0.5V to VAA+ -VAA- volts. Linearity errors increase at lower full scale ranges, however. 2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD voltage. 3. The CLK input is a CMOS inverter with a 50kΩ feedback resistor. It operates from the VAA+ and VAA- supplies. It may be AC-coupled with a 1VP-P minimum source. 4. Parameter not tested, but guaranteed by design or characterization. 3 CA3304, CA3304A Pin Descriptions PIN NUMBER NAME 1 Bit 1 Bit 1 (LSB). 2 Bit 2 Bit 2. 3 Bit 3 Bit 3. 4 Bit 4 Bit 4 (MSB). 5 DC Data Change. 6 OF Overflow. 7 CE2 Three-State Output Enable Input, active low. See the Chip Enable Truth Table. 8 VSS Digital Ground. Three-State Output Enable Input, active high. See the Chip Enable Truth Table. 9 CE1 10 VAA+ 11 VIN DESCRIPTION Output Data Bits (High = True) Analog Power Supply, +5V. Analog Signal Input. 12 VREF+ Reference Voltage Positive Input. 13 VREF- Reference Voltage Negative Input. 14 VAA- Analog Ground. 15 CLK Clock Input. 16 VDD Digital Power Supply, +5V. CHIP ENABLE TRUTH TABLE CE1 CE2 BIT 1 - BIT 4 DC, OF 0 1 Valid Valid 1 1 Three-State Valid X 0 Three-State Three-State X = Don't Care TABLE 1. OUTPUT CODE TABLE INPUT VOLTAGE (V) CODE DESCRIPTION VREF + = 1V VREF - = -1V 1.6V 0V 2V 0V OUTPUT CODE 3.2V 0V 4.8V 0V OF B4 B3 B2 B1 DECIMAL COUNT Zero -1.000 0 0 0 0 0 0 0 0 0 0 1 LSB -0.875 0.1 0.125 0.2 0.3 0 0 0 0 1 1 2 LSB -0.750 0.2 0.250 0.4 0.6 0 0 0 1 0 2 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1/ Full Scale -1 LSB 2 1/ Full Scale 2 1/ Full Scale +1 LSB 2 -0.125 0.7 0.875 1.4 2.1 0 0 1 1 1 7 0 0.8 1.000 1.6 2.4 0 1 0 0 0 8 0.125 0.9 1.125 1.8 2.7 0 1 0 0 1 9 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Full Scale -1 LSB 0.750 1.4 1.750 2.8 4.2 0 1 1 1 0 14 Full Scale 0.875 1.5 1.875 3.0 4.5 0 1 1 1 1 15 Overflow 1.000 1.6 2.000 3.2 4.8 1 1 1 1 1 31 Step Size 0.125 0.1 0.125 0.2 0.3 NOTE: 1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage See Ideal Transfer Curve Figure 6. The output code should exist for an input equal to the ideal center voltage ±1/2 of the step size. 4 CA3304, CA3304A Functional Diagram φ2 φ1 φ2 φ1 φ1 φ1 VAA+ VDD 10 16 THREE-STATE DRIVERS OUTPUT REGISTER 5 DATA CHANGE D Q CLK VIN 11 D 1/ R 2 12 LATCH 16 †CAB #16 VREF + COUNT 16 Q R COUNT ENCODER 8 LOGIC Q D ARRAY LATCH 8 R †CAB #8 D Q CLK 6 OVERFLOW D Q CLK 4 BIT 4 D Q CLK 3 BIT 3 D Q CLK 2 BIT 2 D Q CLK 1 BIT 1 (LSB) R R VREF - 1 D /2R 13 LATCH 0 †CAB COMPARATOR #1 50kΩ COUNT 1 Q φ1 (AUTO BALANCE) CLOCK 15 9 CE1 φ2 (SAMPLE UNKNOWN) 14 8 VAA- VSS 7 CE2 †Cascaded Auto Balance (CAB) NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to VDD and VSS . Analog inputs and clock have standard CMOS protection networks to VAA+ and VAA-. Timing Diagrams DATA SHIFTED INTO OUTPUT REGISTERS 1 CLOCK φ1 AUTO BALANCE 0 COMPARATOR DATA LATCHED φ2 SAMPLE 1 1 B1 - B4, DC & OF AUTO BALANCE SAMPLE 2 DATA VALID 0 0 AUTO BALANCE SAMPLE 3 DATA VALID 1 DATA VALID 2 tHO tD FIGURE 1. TIMING DIAGRAM CE1 CE2 tDIS BITS 1-4 tEN HIGH IMPEDANCE tDIS tEN HIGH IMPEDANCE HIGH DC, OF IMPEDANCE FIGURE 2. OUTPUT ENABLE/DISABLE TIMING 5 CA3304, CA3304A Timing Diagrams (Continued) SAMPLE ENDS φ2 CLOCK SAMPLE ENDS φ1 φ2 φ1 CLOCK φ1 φ2 tD OUTPUT φ1 φ2 tD OLD DATA NEW DATA OUTPUT FIGURE 3A. With φ2 as standby state (fastest method, but standby limited to 5µs maximum) OLD DATA + 1 OLD DATA NEW DATA FIGURE 3B. With φ1 as standby state (indefinite standby, double pulse needed) SAMPLE ENDS φ1 φ2 CLOCK φ1 φ2 φ2 tD OUTPUT INVALID DATA OLD DATA NEW DATA FIGURE 3C. With φ2 as standby state (indefinite standby, lower power than 3B) FIGURE 3. PULSE-MODE TIMING DIAGRAMS Typical Performance Curves 8 40 7 38 6 IDD + IAA (MA) TD (ns) 36 34 32 5 4 30 3 28 -50 -25 0 25 50 75 100 2 TEMPERATURE (oC) 5 10 15 20 25 30 fS (MHz) FIGURE 4. DATA DELAY vs TEMPERATURE FIGURE 5. DEVICE CURRENT vs SAMPLE FREQUENCY 6 CA3304, CA3304A Typical Performance Curves (Continued) 0.10 0.25 0.09 0.22 0.08 0.17 NON-LINEARITY (LSB) NON-LINEARITY (LSB) 0.20 INL 0.15 0.12 DNL 0.10 0.07 0.06 0.04 0.03 0.02 0.02 0.01 0 10 20 30 40 50 TEMPERATURE (oC) 60 70 80 0.00 90 INL 0.05 0.05 0.00 -40 -30 -20 -10 DNL 1 2 3 4 5 REFERENCE VOLTAGE (V) FIGURE 6. NON-LINEARITY vs TEMPERATURE FIGURE 7. NON-LINEARITY vs REFERENCE VOLTAGE 0.50 4.00 0.45 3.80 0.40 3.60 0.35 3.40 INL 0.30 ENOB (LSB) NON-LINEARITY (LSB) 0.07 0.25 0.20 0.15 0.10 3.20 3.00 2.80 2.60 2.40 0.05 2.20 DNL 0.00 15 20 25 fS (MHz) 30 2.00 -40 35 FIGURE 8. NON-LINEARITY vs SAMPLE FREQUENCY -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (oC) 60 70 FIGURE 9. EFFECTIVE BITS vs TEMPERATURE 7 80 90 CA3304, CA3304A Typical Performance Curves (Continued) 7.00 4.00 6.80 3.80 6.60 3.60 6.40 IDD (mA) ENOB (LSB) 3.40 3.20 3.00 6.20 6.00 2.80 5.80 2.60 5.60 2.40 5.40 2.20 5.20 5.00 -40 2.00 0 1 2 3 4 5 6 7 8 9 10 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (oC) fI (MHz) FIGURE 10. EFFECTIVE BITS vs INPUT FREQUENCY FIGURE 11. DEVICE CURRENT vs TEMPERATURE 27Ω +5V SUPPLY CA3304 + 4.7µF TAN 2V REFERENCE + 4.7µF TAN 0.1µF CER VAA+ VDD CE2 VREF+ 0.1µF CER REMOTE 2V INTO 50Ω SOURCE DC, OF, B1-B4 VIN CLK VREF- CE1 VSS VAA- 50Ω ANALOG GROUND 0.1µF CER + 4.7µF TAN OUTPUT DATA CMOS CLOCK SOURCE DIGITAL GROUND FIGURE 12A. TYPICAL CA3304 UNIPOLAR CIRCUIT CONFIGURATION 8 90 CA3304, CA3304A Typical Performance Curves (Continued) 27Ω +5V SUPPLY CA3304 + 4.7µF TAN +1V REFERENCE REMOTE ±1V INTO 50Ω SOURCE 0.1µF CER 0.1µF CER VAA+ VDD CE2 0.1µF CER VREF + + DC, OF, VIN B1 - B4 -1V REFERENCE 50Ω OUTPUT DATA IN914 CMOS CLOCK SOURCE VREF - CLK 0.1µF CER VAA- 0.1µF CER CE1 VSS 4.7µF TAN 10K 0.001µF -1.5V SUPPLY 4.7µF TAN ANALOG GROUND DIGITAL GROUND FIGURE 12B. TYPICAL CA3304 BIPOLAR CIRCUIT CONFIGURATION FIGURE 12. 9 CA3304, CA3304A Description Continuous Clock Operation Device Operation One complete conversion cycle can be traced through the CA3304 via the following steps. (Refer to timing diagram Figure 3). The rising edge of the clock input will start a “sample” phase. During this entire “High” state of the clock, the 16 comparators will track the input voltage and the 16 latches will track the comparator outputs. At the falling edge of the clock, all 16 comparator outputs are captured by the 16 latches. This ends the “sample” phase and starts the “auto balance” phase for the comparators. During this “Low” state of the clock the output of the latches propagates through the decode array and a 6-bit code appears at the D inputs of the output registers. On the next rising edge of the clock, this 6-bit code is shifted into the output registers and appears with time delay tD as valid data at the output of the three-state drivers. This also marks the start of a new “sample” phase, thereby repeating the conversion process for this next cycle. A sequential parallel technique is used by the CA3304 converter to obtain its high speed operation. The sequence consists of the “Auto Balance” phase and the “Sample Unknown” phase (Refer to the circuit diagram). Each conversion takes one clock cycle (see Note). The “Auto Balance” (φ1) occurs during the Low period of the clock cycle, and the “Sample Unknown” (φ2) occurs during the High period of the clock cycle. NOTE: This device requires only a single-phase clock. The terminology of φ1 and φ2 refers to the High and Low periods of the same clock. During the “Auto Balance” phase, a transmission-gate switch is used to connect each of 16 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: VTAP(N) = [(VREF/16) x N] - [VREF/(2 x 16)] Pulse Mode Operation = VREF [(2N - 1)/32], For sampling high speed nonrecurrent or transient data, the converter may be operated in a pulse mode in one of three ways. The fastest method is to keep the converter in the Sample Unknown phase, φ2, during the standby state. The device can now be pulsed through the Auto Balance phase with as little as 20ns. The analog value is captured on the leading edge of φ1 and is transferred into the output registers on the trailing edge of φ1. We are now back in the standby state, φ2, and another conversion can be started within 20ns, but not later than 5µs due to the eventual droop of the commutating capacitors. Another advantage of this method is that it has the potential of having the lowest power drain. The larger the time ratio between φ2 and φ1, the lower the power consumption. (See Timing Diagram Figure 3A). Where: VTAP(N) = Reference ladder tap voltage at point N, VREF = Voltage across VREF - to VREF +, and N = Tap number (1 through 16). The other side of the capacitor is connected to a singlestage inverting amplifier whose output is shorted to its input by a switch. This biases the amplifier at its intrinsic trip point, which is approximately (VDD - VSS)/2. The capacitors now charge to their associated tap voltages, priming the circuit for the next phase. In the “Sample Unknown” phase, all ladder tap switches are opened, the comparator amplifiers are no longer shorted, and VIN is switched to all 16 capacitors. Since the other end of the capacitor is now looking into an effectively open circuit, any voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators whose tap voltages were lower than VIN will drive the comparator outputs to a “low” state. All comparators whose tap voltages were higher than VIN will drive the comparator outputs to a “high” state. A second, capacitorcoupled, auto-zeroed amplifier further amplifies the outputs. The second method uses the Auto Balance phase, φ1, as the standby state. In this state the converter can stay indefinitely waiting to start a conversion. A conversion is performed by strobing the clock input with two φ2 pulses. The first pulse starts a Sample Unknown phase and captures the analog value in the comparator latches on the trailing edge. A second φ2 pulse is needed to transfer the date into the output registers. This occurs on the leading edge of the second pulse. The conversion now takes place in 40ns, but the repetition rate may be as slow as desired. The disadvantage to this method is the slightly higher device dissipation due to the low ratio of φ2 to φ1. (See Timing Diagram Figure 3B). The status of all these comparator amplifiers are stored at the end of this phase (φ2), by a secondary latching amplifier stage. Once latched, the status of the 16 comparators is decoded by a 16 to 5 bit decode array and the results are clocked into a storage register at the rising edge of the next φ2. For applications requiring both indefinite standby and lowest power, standby can be in the φ2 (Sample Unknown) state with two φ1 pulses to generate valid data (see Figure 3C). The conversion process now takes 60ns. [Note that the above numbers do not include the tD (Output Delay) time.] If the input is greater than 31/32 x VREF , the overflow output will go “high”. (The bit outputs will remain high). If the output differs from that of the previous conversion, the data change output will go “high”. Increased Accuracy A three-state buffer is used at the output of the 7 storage registers which are controlled by two chip-enable signals. CE1 will independently disable B1 through B4 when it is in a high state. CE2 will independently disable B1 through B4 and the OF and DC buffers when it is in the low state. In most case the accuracy of the CA3304 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, two adjustments can be made to obtain better accuracy; i.e., offset trim and gain trim. 10 CA3304, CA3304A Offset Trim Digital Input And Output Levels In general offset correction can be done in the preamp circuitry by introducing a DC shift to VIN or by the offset trim of the op amp. When this is not possible the VREF - input can be adjusted to produce an offset trim. The clock input is a CMOS inverter operating from and with logic input levels determined by the VAA supplies. If VAA+ or VAA- are outside the range of the digital supplies, it may be necessary to level shift the clock input to meet the required 30% to 70% of VAA input swing. Figure 12B shows an example for a negative VAA-. The theoretical input voltage to produce the first transition is 1/ LSB. The equation is as follows: 2 An alternate way of driving the clock is to capacitively couple the pin from a source of at least 1VP-P . An internal 50kΩ feedback resistor will keep the DC level at the intrinsic trip point. Extremely non-symmetrical clock waveforms should be avoided, however. VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/16) = VREF/32. Adjust offset by applying this input voltage and adjusting the VREF - voltage or input amplifier offset until an output code alternating between 0 and 1 occurs. The remaining digital inputs and outputs are referenced to VDD and VSS . If TTL or other lower voltage sources are to drive the CA3304, either pull-up resistors or CD74HCT series “QMOS” buffers are recommended. Gain Trim In general the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the op amp. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, VIN should be set to the 15 to overflow transition. That voltage is 1/2 LSB less than VREF + and is calculated as follows: 5-Bit Resolution To obtain 5-bit resolution, two CA3304s can be wired together. Necessary ingredients include an open-ended ladder network, an overflow indicator, three-state outputs, and chip-enable controls - all of which are available on the CA3304. VlN (15 to 16 transition) = VREF - VREF/32 = VREF (31/32). The first step for connecting a 5-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 13. Since the absolute-resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. To perform the gain trim, first do the offset trim and then apply the required VIN for the 15 to overflow transition. Now adjust VREF+ until that transition occurs on the outputs. Layout, Input And Supply Considerations The overflow output of the lower device now becomes the fifth bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overflow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D converter. The three-state outputs of the two devices (bits 1 through 4) are now connected in parallel to complete the circuitry. The CA3304 should be mounted on a ground-planed, printed-circuit board, with good high-frequency decoupling capacitors mounted as close as possible. If the supply is noisy, decouple VAA+ with a resistor as shown in Figure 12A. The CA3304 outputs current spikes to its input at the start of the auto-balance and sample clock phases. A low impedance source, such as a locally-terminated 50Ω coax cable, should be used to drive the input terminal. A fastsettling buffer such as the HA-5033, HA-5242, or CA3450 should be used if the source is high impedance. The VREF terminals also have current spikes, and should be well bypassed. Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the CA3304. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. Care should be taken to keep digital signals away from the analog input, and to keep digital ground currents away from the analog ground. If possible, the analog ground should be connected to digital ground only at the CA3304. Bipolar Operation The CA3304, with separate analog (VAA+, VAA-) and digital (VDD , VSS) supply pins, allows true bipolar or negative input operation. The VAA- pin may be returned to a negative supply (observing maximum voltage ratings to VAA+ or VDD and recommended rating to VSS), thus allowing the VREFpotential also to be negative. Figure 12B shows operation with an input range of -1V to +1V. Similarly, VAA+ and VREF + could be maintained at a higher voltage than VDD , for an input range above the digital supply. Signal-to-Noise (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. 11 Effective Number of Bits (ENOB) +5V The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: +FULL SCALE REF. ENOB = (SINAD - 1.76 + VCORR)/6.02, where: VCORR = 0.5dB. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. BUFFER INPUT 1K ADJUST CENTER Operating and Handling Considerations +5V HANDLING All inputs and outputs of CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in lCAN-6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.” VAA+ VDD DC NC OF NC VREF + VIN VREF VAA- B4 B3 B2 B1 VSS CE1 CLK CE2 CLOCK INPUT CA3304 NC CLK VAA+ DC VDD B4 B4 VREF + B3 VIN B2 B3 B2 B5 MSB OF VREF B1 VAACE1 VSS CE2 B1 +5V CA3304 OPERATING FIGURE 13. TYPICAL CA3304 5-BIT CONFIGURATION Operating Voltage During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause the power supply voltages to exceed the absolute maximum rating. OVERFLOW DECIMAL COUNT Input Signals To prevent damage to the input protection circuit, input signals should never be greater than VDD or VAA+ nor less than VSS or VAA- (depending upon which supply the protection network is referenced. See Maximum Ratings.). Input currents must not exceed 20mA even when the power supply is off. Unused Inputs A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS , whichever is appropriate. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 Output Short Circuits INPUT VOLTAGE Shorting of outputs to any supply potential may damage CMOS devices by exceeding the maximum device dissipation. FIGURE 14. IDEAL TRANSFER CURVE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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