IDTQS74FCT2841AT/BT/CT HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH INDUSTRIAL TEMPERATURE RANGE HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH IDTQS74FCT2841AT/BT/CT DESCRIPTION: FEATURES: The IDTQS74FCT2841T is a 10-bit high-speed CMOS TTL-compatible buffered latch with 3-state outputs, with a 25Ω resister that is useful for driving transmission lines and reducing system noise. The 2841 eliminates the need for external series resistors in high speed systems and can replace the 841 series to reduce noise in an existing design. All inputs have clamp diodes for undershoot noise suppression. All outputs have ground bounce suppression. Outputs will not load an active bus when Vcc is removed from the device. • • • • • • CMOS power levels: <7.5mW static Undershoot clamp diodes on all outputs True TTL input and output compatibility Ground bounce controlled outputs Reduced output swing of 0 to 3.5V Ω series resistor outputs reduce reflection and other Built-in 25Ω system noise • A, B, and C speed grades with 5.5ns tPD for C • IOL = 12mA • Available in SOIC and QSOP packages FUNCTIONAL BLOCK DIAGRAM 25Ω Dx D LE LE Yx Q OE INDUSTRIAL TEMPERATURE RANGE MARCH 2002 1 c 2002 Integrated Device Technology, Inc. DSC-5260/4 IDTQS74FCT2841AT/BT/CT HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol OE 24 1 VCC Unit VTERM Terminal Voltage with Respect to GND –0.5 to +7 V TSTG Storage Temperature –65 to +150 °C 2 23 Y0 IOUT DC Output Current Max Sink Current/Pin 120 mA D1 3 22 Y1 IIK Input Diode Current, VIN < 0 –20 mA IOK Output Diode Current, VOUT < 0 –50 mA D2 4 21 Y2 D3 5 20 Y3 D4 6 19 Y4 D5 7 18 Y5 D6 8 17 Y6 D7 9 16 Y7 D8 10 15 Y8 D9 11 14 Y9 13 12 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit Input Capacitance VIN = 0V 4 — pF (3) COUT Output Capacitance VOUT = 0V 6 — pF COUT(4) Output Capacitance VOUT = 0V 4 — pF (2) CIN LE NOTES: 1. This parameter is measured at characterization but not tested. 2. Pins 1-11, 13. 3. Pins 15-22. 4. Pins 14, 23. SOIC/ QSOP TOP VIEW PIN DESCRIPTION Pin Names I/O Dx I Latch Data Inputs LE I The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. Yx O 3-State Latch Outputs OE I The output enable control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs Yx are in high-impedance (off) state. Description FUNCTION TABLE(1) Inputs LOGIC SYMBOL Dx Max D0 GND 10 Description D Q 10 Dx LE LE OE 2 Outputs Value Qx Yx Function OE LE H H L L Z High-Z H H H H Z High-Z H L X NC Z Latched (High-Z) L H L L L Transparent L H H H H Transparent L L X NC NC NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care NC = No Change Z = High-Impedance Yx Internal Latched IDTQS74FCT2841AT/BT/CT HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5% Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit — — V VIH Input HIGH Level Guaranteed Logic HIGH Level 2 VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V ∆VT Input Hysteresis VTLH - VTHL for all inputs — 0.2 — V IIH Input HIGH Current VCC = Max. 0 ≤ VIN ≤ VCC — — ±5 µA IIL Input LOW Current IOZ Off-State Output Current (Hi-Z) 0 ≤ VIN ≤ VCC — — ±5 µA VCC = Max 2.0V(2) IOR VIC Current Drive Input Clamp Voltage VCC = Max., VOUT = VCC = Min, IIN = -18mA , TA = 25°C(2) 50 — — –0.7 — –1.2 mA V VOH VOL ROUT(3) Output HIGH Voltage Output LOW Voltage Output Resistance VCC = Min. VCC = Min. VCC = Min. 2.4 — 18 — — 25 — 0.5 40 V V Ω IOH = -15mA IOL = 12mA IOH = 12mA NOTES: 1. Typical values are at VCC = 5.0V, TA = 25°C. 2. This parameter is measured at characterization but not tested. 3. ROUT changed on March 8, 2002. See rear page for more information. POWER SUPPLY CHARACTERISTICS Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 5% Symbol ICC Parameter Quiescent Power Supply Current ∆ICC Supply Current per Input TTL Inputs HIGH ICCD Supply Current per Input per MHz Test Conditions(1) VCC = Max. freq = 0 0V ≤ VIN ≤ 0.2V or VCC - 0.2V ≤ VIN ≤ Vcc VCC = Max. VIN = 3.4V(2) freq = 0 VCC = Max. Outputs Open and Enabled One Bit Toggling 50% Duty Cycle Other inputs at GND or Vcc(3,4) Min. — Max. 1.5 Unit mA — 2 mA — 0.25 mA/MHz NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TLL driven input (VIN = 3.4V). 3. For flip-flops, ICCD is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption only and does not include power to drive load capacitance or tester capacitance. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 3 IDTQS74FCT2841AT/BT/CT HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) Symbol tPLH tPHL tPLH tPHL tSU tH tLEY tLEY tW tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ Parameter(2) Data to Y Delay OE = LOW Data to Y Delay(3,4) OE = LOW Data to LE Setup Time Data to LE Hold Time LE to Y Delay OE = LOW LE to Y Delay(3,4) OE = LOW LE Pulse Width, HIGH(3) Output Enable Time OE to Yx Output Enable Time(3,4) OE to Yx Output Disable Time(3,5) OE to Yx Output Disable Time(3) OE to Yx FCT2841AT Min. Max. — 9.5 FCT2841BT Min. Max. — 6.5 FCT2841CT Min. Max. — 5.5 Unit ns — 20 — 13 — 13 ns 2.5 2.5 — — — 12 2.5 2.5 — — — 8 2.5 2.5 — — — 8 ns ns ns — 16 — 15.5 — 15 ns 6 — — 11.5 4 — — 8 4 — — 6.5 ns ns — 23 — 14 — 12 ns — 7 — 6 — 5.7 ns — 8 — 7 — 6 ns NOTES: 1. CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted. 2. See Test Circuits and Waveforms 3. This parameter is guaranteed by design but not tested. 4. CLOAD = 300pF. 5. CLOAD = 5pF. 4 IDTQS74FCT2841AT/BT/CT HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS VCC SWITCH POSITION 7.0V 500Ω Pulse Generator VOUT VIN D.U.T. 50pF RT 500Ω Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL FCTL link Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V 3V 1.5V 0V tREM tSU LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH FCTL link Pulse Width FCTL link Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V 1.5V CONTROL INPUT OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH FCTL link SWITCH CLOSED tPZH SWITCH OPEN 0V tPLZ tPZL VOH 1.5V VOL 3.5V 1.5V 3.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V FCTL link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 5 IDTQS74FCT2841AT/BT/CT HIGH-SPEED CMOS BUS INTERFACE 10-BIT LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDTQS XX FCT XXXX Device Type Temp. Range XX Package SO Q Small Outline IC (gull wing) Quarter Size Small Outline Package 2841AT High-Speed CMOS Bus Interface 10-Bit Latch 2841BT 2841CT 74 –40°C to +85°C As per PCN L0201-02, the Output Resistance (ROUT) specifications have changed as of March 8, 2002. The original specifications were: Parameter ROUT Description Min. Typ. Max. Unit VCC = Min, IOL = -15mA 20 28 40 Ω CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459