ASAHI KASEI [AK2363] AK2363 Radio Signaling LSI Features □ DTMF Receiver including an AGC circuit □ Built-in MSK modem allowing selection from 1200 and 2400 bit/s □ Programmable modem frame detection pattern □ Built-in 3.6864MHz oscillator circuit □ Support of external clocks with frequencies twice, three times, and four times higher than 3.6864MHz □ Operating voltage range: □ Operating temperature range: -40°C to +85°C □ Package: 2.6V to 3.7V 24-pin QFNJ (4.0 x 4.0 x 0.75mm, 0.5mm pitch) Overview The AK2363 is a radio signaling LSI device into which an MSK modem and a DTMF Receiver are integrated on a single chip. The MSK modem supports 1200 and 2400 bit/s, and the demodulator has a 16-bit frame pattern detection function that allows any settings. When the signal-to-noise (S/N) ratio is 12dB, the BER characteristic at 1200 bit/s is 5.0E-06, and the BER characteristic at 2400 bit/s is 1.0E-04. The DTMF Receiver operates in two modes: Normal mode (AGD Disable) indicating input signal detection levels ranging from -27dBx to 0dBx and high sensitivity mode (AGC Enable) in which the receiver operates at –40dBx to 0dBx. In addition to a fundamental frequency of 3.686MHz, the oscillator circuit supports external clock input with frequencies of 7.3728MHz (twice higher than 3.6864MHz), 11.0592MHz (three times higher than 3.6864MHz), and 14.7456MHz (four times higher than 3.6864MHz). The internal operation is controlled by the three-wire serial method in which serial input data (SDATA) consisting of a 1-bit instruction, a 4-bit address, and 8-bit data is set in synchronization with the CSN and SCLK signals. The 24-pin QFNJ package (4.0mm ´ 4.0mm) is employed to realize compact, high-density packaging. MS0583-E-01 2008/06 -1- ASAHI KASEI [AK2363] Contents Features............................................................................................................................ 1 Overview........................................................................................................................... 1 Contents ........................................................................................................................... 2 Block Diagram.................................................................................................................. 3 Pin Assignments.............................................................................................................. 3 Block Functions............................................................................................................... 4 Pin Functions ................................................................................................................... 5 Absolute Maximum Ratings ............................................................................................ 7 Recommended Operating Conditions............................................................................ 7 Digital DC Characteristics............................................................................................... 7 Clock Input Characteristics ............................................................................................ 8 System Reset ................................................................................................................... 8 Current Consumption...................................................................................................... 9 Analog Characteristics.................................................................................................. 10 Digital AC Timing ........................................................................................................... 11 Register Functions ........................................................................................................ 17 MSK Modem Operation ................................................................................................. 22 DTMF Receiver Operation ............................................................................................. 25 Recommended External Circuit Examples .................................................................. 29 Package .......................................................................................................................... 32 Important Notice ............................................................................................................ 33 MS0583-E-01 2008/06 -2- ASAHI KASEI [AK2363] MODIN MSKOUT Block Diagram 24 3 TCLK TDATA 2 MOD MSKTX MSK Modulator 23 MSK LPF MSK DAC + VR 22 TXA RXINO RXIN 19 20 Power ON at Mode 1,2,3, 4,5,6 + MSK BPF RXA VDD Power ON Power ON at Mode 2,4,6 at Mode 3,4,6 Data Demodulator 3.6864MHz 15 Digital PLL DIV (1/2,3,4) OSC XIN 16 6 + XOUT DTMFSL 9 DTMF Receiver STD 10 DTMFIN RDFFD/RDATA RSTN 18 RCLK 8 1 17 4 TEST 5 CSN AGND 7 SDATA 21 + AGC (PGA) Control Register AGND 11 12 SD ACK 13 LOADN 14 SCLK VSS Power ON at Mode 5,6 DTMFIN TEST XOUT XIN VSS LOADN Pin Assignments 18 17 16 15 14 13 11 SD AGND 21 10 STD MOD 22 9 RCLK MODIN 23 8 RDFFD/RDATA M SKOUT 24 7 SDATA 1 2 3 4 5 6 VDD 20 SCLK RXIN CSN ACK TCLK 12 TDATA 19 RSTN RXINO MS0583-E-01 2008/06 -3- ASAHI KASEI [AK2363] Block Functions Block MSK Modulator MSK DAC MSK LPF VR TXA RXA MSK BPF Data Demodulator Digital PLL AGC(PGA) Function This circuit generates an MSK signal according to the logic of a digital signal input from the TDATA pin. DAC that converts data generated by the MSK Modulator into an analog signal. This circuit is a low-pass filter for eliminating the clock component included in the MSK DAC signal. A switch for changing between the mute and active states is provided between this filter and VR and is set by setting register MSKTX. This control adjusts the output level of the transmit MSK signal. Setting register: VR[4:0] Adjustment range: -6.0dB to +6.0dB in 0.5dB steps Operational amplifier for gain adjustment of the transmit MSK signal and for forming a smoothing filter for removing noise components included in the output signal. Use an external resistor and capacitor to set the gain to 0dB and the cut-off frequency to around 13kHz. Operational amplifier for gain adjustment of the receive demodulation signal and for forming a filter for preventing aliasing noise in the SCF circuit in the subsequent stage. Use external resistors and capacitors to set the gain to 20dB or less and the cut-off frequency to around 40kHz. Band-pass filter to eliminate out-of-band components included in the receive MSK signal. This circuit demodulates the MSK signal and generates data. This circuit detects the carrier signal from the MSK signal and regenerates a clock signal. AGC (Auto Gain Control) circuit for adjusting the input level of the DTMF signal automatically. Setting register: AGCSW or AGCSW. When disabled, this circuit functions as a PGA (Programmable Gain Amp) circuit. Setting register: PGA[1:0] Adjustment range: 0dB to +12dB in 4dB steps A switch for changing the input is provided between this circuit and RXA and is set by setting register DTMFSL. DTMF Receiver DTMF signal detection circuit. It decodes the input signal and outputs 4-bit code. OSC This circuit generates a 3.6864MHz reference clock signal from an external crystal oscillator and resistor. DIV (1/2,1/3,1/4) When a signal of which frequency is twice, three times, or four times higher than 3.6864MHz is input from the outside, this circuit divides the signal frequency by two, three, or four. Setting register: MCKSL[1:0] AGND This circuit generates the reference voltage (1/2VDD) for internal analog signals. Control Register Control registers set the switches and control in the IC according to the serial input data consisting of a 1-bit instruction, a 4-bit address, and 8-bit data. A built-in data buffer is provided to hold 8-bit MSK receive data for easier interfacing with the CPU. At power-on, a system reset is caused by the RSTN pin. A soft reset is set by the SRST register. (Refer to the description of the registers.) MS0583-E-01 2008/06 -4- ASAHI KASEI [AK2363] Pin Functions Pin No. Pin name Pin type Pin status at powerdown Function 1 RSTN DI Z Reset pin 2 TDATA DI Z Data is input from this pin on the rising edge of the clock signal on the TCLK pin. 3 TCLK DO L MSK signal transmit clock output pin 4 CSN DI Z Chip select input pin for serial data 5 SCLK DI Z Clock input pin for serial data MSK signal transmit data input pin VDD power supply pin 6 VDD 7 SDATA PWR - Connect this pin to a power supply ranging from 2.6V to 3.7V with less noise. Connect a bypass capacitor of 0.1mF or higher between this pin and the VSS pin. DB Z Serial data I/O pin MSK signal receive flag/frame detection signal/RDATA signal output pin Two types of information is output depending on the FSL register status. 8 RDFFD/ RDATA DO L If FSL is set to 1 to set the MSK signal receive flag output mode (RDF), this pin is set to the low output level when 8 bits of the MSK receive signal have been written to the receive data register. If FSL is set to 0 to set the frame detection signal output mode (FD), a low-level pulse is output on this pin when a frame pattern is detected. If setting register MSKRCLK is set to 1, the RDATA signal is output. 9 RCLK DO L MSK signal receive clock output pin Steering delay output pin for DTMF signal detection 10 STD DO L This pin goes high when internal data has been updated after completion of DTMF RX signal decoding. DTMF signal receive data output pin 11 SD DO L If the LOADN pin input is low, the result of DTMF RX signal decoding is output serially starting from the MSB in synchronization with the falling edge of the ACK pin input. If the LOADN pin input is high, the high level is output. 12 ACK DI Z 13 LOADN DI Z Clock input pin for DTMF signal receive data read Enable signal input pin for DTMF signal receive data read If the low level is input, DTMF signal receive data can be read. MS0583-E-01 2008/06 -5- ASAHI KASEI Pin No. 14 [AK2363] Pin name Pin type Pin status at powerdown VSS PWR - Function VSS power supply pin Always apply 0V. Pin for connecting a crystal oscillator 15 XIN 16 XOUT DI/AO *4) AI *4) A reference clock used within this IC is generated by connecting a 3.6864MHz oscillator between this pin and the adjacent XOUT pin. For detailed information about the connection method and the method for supplying an external clock, refer to “Recommended External Circuit Examples.” Pin for connecting a crystal oscillator Test output pin 17 TEST DI Z This pin is used as a test pin before shipment. Normally, connect this pin to VSS. 18 DTMFIN AI Z DTMF signal input pin 19 RXINO AO Z RXA amplifier output pin *1) 20 RXIN AI Z Demodulated receive signal input pin Inverted input pin of the RXA amplifier. This pin, with resistors and capacitors externally connected, forms a pre-filter. Analog ground output pin 21 AGND AO *3) 22 MOD AO Z Connect a 0.1mF capacitor between this pin and the VSS pin to stabilize the analog ground level. Modulated transmit signal output pin *2) Modulated transmit signal input pin 23 MODIN AI Z Inverted input pin of the TXA amplifier. This pin, with a resistor and capacitor externally connected, forms a smoothing filter. 24 MSKOUT AO Z MSK signal level output pin *1) Note A: Analog, D: Digital, PWR: Power, I: Input, O: Output, B: Bidirectional, Z: High-Z, L: Low *1) *2) Output load requirement: Load impedance > 30kΩ, load capacitance < 15pF Output load requirement: Load impedance > 10kΩ, load capacitance < 50pF *3) *4) AGND level The XIN pin output level is determined by the XOUT pin input level. MS0583-E-01 2008/06 -6- ASAHI KASEI [AK2363] Absolute Maximum Ratings Parameter Symbol Power supply voltage VDD Ground level VSS Input voltage VIN Input current (except power pin) IIN Storage temperature Tstg Note All voltages are relative to the VSS pin. Caution Min. -0.3 0 -0.3 -10 -55 Max. 4.6 0 VDD+0.3 +10 130 Unit V V V mA °C If the device is used in conditions exceeding these values, the device may be destroyed. Normal operations are not guaranteed in such extreme conditions. Recommended Operating Conditions Symbol Condition Parameter Ta Operating temperature Operating power supply VDD voltage Analog reference AGND voltage Note All voltages are relative to the VSS pin. Min. -40 Typ. Max. 85 Unit °C 2.6 3.0 3.7 V V 1/2VDD Digital DC Characteristics Parameter Symbol High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL High level output voltage VOH Low level output voltage VOL Condition Min. SCLK, SDATA, CSN, LOADN, ACK, TDATA, 0.8VDD RSTN, SCLK, SDATA, CSN, LOADN, ACK, TDATA, RSTN, VIH=VDD SCLK, SDATA, CSN, LOADN, ACK, TDATA, RSTN, VIL=0V SCLK, SDATA, CSN, -10 LOADN, ACK, TDATA, RSTN, IOH=+0.2mA SDATA, RDFFD/RDATA, VDD-0.4 RCLK, STD, SD, TCLK IOL=-0.4mA SDATA, RDFFD/RDATA, 0.0 RCLK, STD, SD, TCLK MS0583-E-01 Typ. Max. Unit V 0.2VDD V 10 mA mA VDD V 0.4 V 2008/06 -7- ASAHI KASEI [AK2363] Clock Input Characteristics Parameter Clock frequency Symbol Condition MCK0 XIN,XOUT MCK1,2 XIN High level input voltage VMCK1_IH XIN Low level input voltage VMCK1_IL XIN VMCK2 XIN Input amplitude *1) *2) Min. Typ. Max. Unit Remarks 3.6864 MHz 7.3728 11.0592 14.7456 MHz *1), *2) V *1) 0.4 V *1) 1.0 VPP *2) 1.5 0.2 These values apply when the clock signal is input on the XIN pin directly. For details, refer to 6), "Oscillator circuit", in "Recommended External Circuit Examples". These values apply when the clock signal is input on the XIN pin via DC cut. For details, refer to 6), "Oscillator circuit", in "Recommended External Circuit Examples". System Reset Parameter Symbol Hardware reset signal input width tRSTN RSTN pin Min. Typ. Max. 1 Unit Remarks us *1) SRST register Software reset *1) Condition *2) After power-on and passed 35ms or longer, be sure to perform a hardware reset operation (register initialization). The system is reset by a low pulse input of 1ms (min.) and enters the normal operation state. At this moment, the digital (DI) pins are set as follows: RSTN pin to high, TDATA pin to low, CSN pin to high, SCLK pin to low, ACK pin to high, LOADN pin to high, TEST pin to VSS. tRSTN VIH RSTN VIL *2) When data 0xAA:10101010 is written to the SRST[8:0] register, a software reset is performed. This setting initializes the registers and the operation mode is set to mode 1 (standby). For details, refer to "Register Functions". MS0583-E-01 2008/06 -8- ASAHI KASEI [AK2363] Current Consumption Parameter Symbol IDD0 IDD1 IDD2 Current consumption IDD3 IDD4 IDD5 IDD6 Condition Mode 0 OSC: OFF, DTMF Receiver: OFF, MSK_Tx: OFF, MSK_Rx: OFF Mode 1 OSC: ON, DTMF Receiver: OFF, MSK_Tx: OFF, MSK_Rx: OFF Mode 2 OSC: ON, DTMF Receiver: OFF, MSK_Tx: ON, MSK_Rx: OFF Mode 3 OSC: ON, DTMF Receiver: OFF, MSK_Tx: OFF, MSK_Rx: ON Mode 4 OSC: ON, DTMF Receiver: OFF, MSK_Tx: ON, MSK_Rx: ON Mode 5 OSC: ON, DTMF Receiver: ON, MSK_Tx: OFF, MSK_Rx: OFF Mode 6 OSC: ON, DTMF Receiver: ON, MSK_Tx: ON, MSK_Rx: ON MS0583-E-01 Min. Typ. Max. 0.1 0.2 0.6 1.0 1.3 2.1 1.1 1.8 1.7 2.7 1.3 2.2 2.4 3.8 Unit mA 2008/06 -9- ASAHI KASEI [AK2363] Analog Characteristics Unless otherwise specified, the following apply: MCLK = 3.6864MHz, f = 1kHz, VR = 0dB The external circuit constants are set based on the recommended external circuit examples on pages 29 to 31. dBx is a standardized notation to match the operating voltage and is defined by equation 0dBx = -5 + 20log(VDD/2)dBm. 0dBm = 0.775Vrms 1) MSK modem characteristics Parameter Condition Min. Typ. Max. Unit Remarks TX signal @MOD -12 -11 -10 dBx 1.2kHz signal output TX signal distortion @MOD -32 dB 1.2kHz signal output RX signal @RXINO -17 -11 -1 dBx 1.2kHz signal output VR gain deviation @MSKOUT -0.5 0.5 dB -6.0dB to +6.0dB, in 0.5dB steps Linearity 2) DTMF Receiver characteristics Parameter Condition @RXINO, AGC Disable, PGA=0dB *2), *3), *6) Tone input level accept (for each tone of composite signal) Twist accept @RXINO, AGC Enable, *2), *3), *6) @DTMFIN, AGC Disable, PGA=0dB *2), *3), *6) @DTMFIN, AGC Enable, *2), *3), *6) *3), *6), *8) Frequency deviation accept Frequency deviation reject Third tone tolerance *2), *6) Noise tolerance *1), *2), *4), *6), *7) Dial tone tolerance *1), *2), *5), *6), *7) PGA gain deviation 0dB to +12dB, in 4dB steps *1) *2) *3) *4) *5) *6) *7) *8) Min. Typ. Max. Unit -27 0 dBx -40 0 dBx -27 -2 dBx -40 -2 dBx ±10 Remarks dB ±1.5% ±2Hz *2), *6) ±3.5% *1), *2), *6), *7) -0.5 -16 dB -12 dB +17 dB +0.5 dB Refers to nominal DTMF frequencies. High/low tones have the same amplitudes. High/low tones are deviated by ±1.5%±2Hz. Bandwidth is limited from 0 to 3kHz Gaussian noise. Dialtones of 350Hz and 440Hz ±2% Error rates better than 1 in 10000 Reference DTMF signal input level is -22dBx or less. Twist = high tone/low tone MS0583-E-01 2008/06 - 10 - ASAHI KASEI [AK2363] Digital AC Timing 1) Serial interface timing The AK2363 writes and reads data via the three-wire synchronous serial interface by means of CSN, SCLK, and SDATA. SDATA (serial data) consists of a write/read identification bit (R/W), a register address (starting from the MSB, A3 to A0), and control data (starting from the MSB, D7 to D0). Write (WRITE instruction) CSN SCLK SDATA (Input) SDATA (Output) R/W A3 A2 A1 A0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D4 D3 D2 D1 D0 Hi-Z Read (READ instruction) CSN SCLK SDATA (Input) SDATA (Output) R/W Hi-Z Hi-Z D7 D6 D5 D0 R/W: This bit indicates whether an access to a register is a write access or read access. If this bit is Low, a write is performed; if the bit is High, a read is performed. A3 to A0: These bits indicate the address of the register to be accessed. D7 to D0: Data to be written to or read from the register. <1> CSN (chip select) is normally set to the high level. When CSN is set to the low level, the serial interface becomes active. <2> When a write operation is performed, an identification bit, an address, and data are input from SDATA in synchronization with the rising edges of 14 SCLK clock pulses while CSN is low. During the time between address A0 and data D7, SDATA must be held low. When a read operation is performed, an identification bit and an address are input from SDATA in synchronization with the rising edges of the first five clock pulses of SCLK, and data at a specified address is output in synchronization with the falling edges of the following nine clock pulses while CSN is low. Note that data between address A0 and data D7 is undefined. During the data output period in the latter nine clock pulses of SCLK, the input to SDATA must be Hi-Z. <3> Write and read settings are made on the assumption that 14 clock pulses are input from SCLK while CSN is low. Note that if clock pulses more than or less than 14 clock pulses are input, data cannot be set correctly. MS0583-E-01 2008/06 - 11 - ASAHI KASEI [AK2363] 2) Detail timing WRITE instruction tCSLH tCSS tCSHH CSN tWH tWL SCLK tDS SDATA (Input) R/W SDATA (Output) High-Z tDH A3 A2 A1 A0 D7 D6 D1 D0 READ instruction tCSLH tCSS tCD CSN tSD tDD SCLK High-Z SDATA (Input) R/W SDATA (Output) High-Z A3 A2 A1 A0 D7 D6 D1 D0 Rising and falling times tR tF SCLK VIH VIL Parameter CSN setup time SDATA setup time SDATA hold time SCLK high time SCLK low time CSN low hold time CSN high hold time SDATA Hi-Z setup time SCLK to SDATA output delay time CSN to SDATA input delay time SCLK rising time SCLK falling time Note Symbol tCSS tDS tDH tWH tWL tCSLH tCSHH tSD tDD tCD Condition Loaded by 20pF Loaded by 20pF tR tF Min. 100 100 100 500 500 100 100 500 Typ. Max. Unit ns ns ns ns ns ns ns ns 400 ns 200 ns 100 100 ns ns Digital input timing measurements are made at 0.5VDD for rising edges and falling edges. Digital output timing measurements are made at 0.5VDD for rising edges and falling edges. MS0583-E-01 2008/06 - 12 - ASAHI KASEI [AK2363] 3) MSK Modulator timing Parameter CSN rising to TCLK falling Symbol Min. Typ. Max. Unit MSKSL = 0 MSKSL = 1 T1 208 417 ms MSKSL = 0 MSKSL = 1 T2 417 833 ms TCLK period TDATA set up time TDATA hold time TDATA hold time2 tS tH tH2 1 1 2 ms CSN SCLK SDATA (Input) Mode 2,4,6 T1 MSKTX=0 T2 TCLK tS TDATA MOD 1 tH2 0 1 1 MSKSL=”0” 2400bit/s MOD tH 1200Hz 2400Hz 1200Hz 1800Hz MSKSL=”1” 1200bit/s Note Register setting is synchronized with the rising edge on the CSN pin. When the data is maintained for 2ms or longer specified by TDATA hold time2 (tH2), the signal from MOD pin is ended in zero cross point. 4) MSK Demodulator timing Parameter RCLK period and FD pulse width Symbol MSKSL = 0 MSKSL = 1 T MS0583-E-01 Condition Min. Typ. 417 833 Max. Unit ms 2008/06 - 13 - ASAHI KASEI [AK2363] CSN SCLK SDATA (Input) FSL Mode 3,4,6 FSL=FCLN=0 A[3:0]=0110 Data Read FSL=1 Mode 1,2,5 (Internal Register) FCLN FCLN=1 automatically (Internal Register) RCLK_n (Internal Node) RDATA_n MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MD7 MD6 MD5 MD4 (Internal Node) T FD_n (Internal Node) RDF_n (Internal Node) SDATA (Output) MS0583-E-01 2008/06 - 14 - MD3 MD2 MD1 MD0 MD7 MD6 ASAHI KASEI 5) DTMF Receiver timing Parameter [AK2363] Symbol Tone present detection time(reference value) tDP Tone absent detection time (reference value) tDA Tone duration accept time *1) Tone duration reject time*1) Interdigit pause accept time *1) Interdigit pause reject time *1) GT (internal counter) to STD propagation delay STD rising to LOADN falling time ACK low period ACK high period LOADN setup time SD output delay time SD output disable time ACK rising time ACK falling time tREC Condition Min. Typ. Max. Unit AGC Disable AGC Enable 5 5 0.5 11 20 4 16.8 44 8.5 ms ms ms AGC Disable GTP[3:0]=0100 AGC Enable GTP[3:0]=0001 tREJ tID tDO 54.5 ms 54 ms 32.2 28.4 1.6 tPSTD tDL tCLL tCLH tLS tPD tDF tCLR tCLF ms 21.7 100 500 500 500 Loaded by 20pF Loaded by 20pF ms ms ms 200 200 100 100 ns ns ns ns ns ns ns ns *1) The data shows the values when registers GTPn and GTAn (n = 0 to 3) contain their initial values. This data can be adjusted by setting registers GTPn and GTAn (n = 0 to 3) (refer to pages 26 and 27). *2) Digital input timing measurements are made at 0.5VDD for rising edges and falling edges. Digital output timing measurements are made at 0.5VDD for rising edges and falling edges. MS0583-E-01 2008/06 - 15 - ASAHI KASEI [AK2363] tREJ RXIN TONE #n tDP DTMFIN TONE #n+1 tID tREC tDA tDO Value in Register GTP Internal Counter values tGTP ,tGTA Internal data tGTP tGTA Value in Register GTA DECODED TONE #n-1 DECODED TONE #n DECODED TONE #n+1 tPSTD STD tDL LOADN ACK SD SD #n MSB SD #n+1 LSB ( MSB First ) Note Internal data of the LSI device is changed by DTMF data immediately before STD goes high. tLS LOADN tCLH tCLL ACK tDF tPD SD SD3 SD2 (MSB) ACK tCLR SD1 SD0 (LSB) tCLF VIH VIL MS0583-E-01 2008/06 - 16 - ASAHI KASEI [AK2363] Register Functions 1) Register configuration Address Data Function D7 D6 D5 D4 D3 D2 D1 D0 Control register 1 BS2 BS1 BS0 MSKSL MSKTX MSKRCLK FSL FCLN 1 Control register 2 MCKSL1 MCKSL0 TXRXA VR4 VR3 VR2 VR1 VR0 1 0 DTMF register 1 GTP3 GTP2 GTP1 GTP0 GTA3 GTA2 GTA1 GTA0 0 1 1 DTMF register 2 - STDPGA1 STDPGA0 DTMFSL AGCSW1 AGCSW0 PGA1 PGA0 0 1 0 0 Modem frame pattern 1 Lower 8 bits of MSK modem frame pattern 0 1 0 1 Modem frame pattern 2 Upper 8 bits of MSK modem frame pattern 0 1 1 0 Modem receive data register 0 1 1 1 Software reset 1 0 0 0 Revision register 1 0 0 1 Test register 1 Test register 1 for LSI test operation (not accessible) 1 0 1 0 Test register 2 Test register 2 for LSI test operation (not accessible) 1 0 1 1 Not used - - - - - - - - ¯ ¯ ¯ ¯ Not used - - - - - - - - 1 1 1 1 Not used - - - - - - - - A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 Note 1 Note 2 Note 3 MSK receive data (RDATA) SRST[7:0] - - - - REVNUM[3:0] An access to data indicated by "-" does not have any effect on the LSI operation, and always reads 0. The SRST[7:0] register at address 0111 is write-only. The MSK receive data register at address 0110 and the REVNUM[3:0] register at address 1000 are read-only. Test registers are located at addresses 1001 and 1010 and cannot be accessed. If an access is made to these addresses inadvertently, the LSI operation is not guaranteed. 2) Descriptions of registers 2.1) Control register 1 Address Data A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 BS2 BS1 BS0 MSKSL MSKTX MSKRCLK FSL FCLN 0 0 0 1 1 0 0 1 Initial value MS0583-E-01 2008/06 - 17 - ASAHI KASEI 2.1.1) [AK2363] Operation mode setting Mode name BS2 BS1 BS0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 Mode 0 (power down) Mode1 (standby) Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 OSC and AGND OFF MSK modem TX OFF MSK modem RX OFF DTMF Receiver OFF ON ON ON ON ON ON OFF ON OFF ON OFF ON OFF OFF ON ON OFF ON OFF OFF OFF OFF ON ON Note: After setting the system reset(Mode 0), select Mode 2 to 6 via setting Mode 1. 2.1.2) MSK modem setting Data MSKSL MSKTX MSKRCLK MSK modem transmission speed MSK transmit output RCLK output switching RDF/FD output switching Frame Detect FSL FCLN 2.2) Function Item Remarks 0 1 2400 bit/s 1200 bit/s OFF (Mute) ON (Active) RCLK pin High output RDFFD/RDATA pin Active (RDFFD signal output) Frame detection signal (FD) output ON (Enable) RCLK pin Active RDFFD/RDATA pin Active (RDATA signal output) Receive flag signal (RDF) output OFF (Disable) Control register 2 Address Data A3 A2 A1 A0 0 0 0 1 Initial value D7 D6 MCKSL1 MCKSL0 0 0 MCKSL1 MCKSL0 D5 D4 D3 D2 D1 D0 TXRXA 0 VR4 0 VR3 1 VR2 1 VR1 0 VR0 0 Remarks Function 0 0 Master clock: 3.6864MHz 0 1 Master clock: 7.3728MHz External input only 1 0 Master clock: 11.0592MHz External input only 1 1 Master clock: 14.7456MHz External input only Data TXRXA Item TXA and RXA amplifier operation Function 0 1 OFF (Power OFF) MS0583-E-01 ON (Power ON) Remarks ORed with operation mode setting; valid in modes 1 to 6 2008/06 - 18 - ASAHI KASEI 2.3) A3 0 [AK2363] VR4 VR3 VR2 VR1 VR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 VR gain (dB) -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 VR4 0 0 0 1 1 1 1 1 1 1 1 1 VR3 1 1 1 0 0 0 0 0 0 0 0 1 VR2 1 1 1 0 0 0 0 1 1 1 1 0 VR1 0 1 1 0 0 1 1 0 0 1 1 0 VR0 1 0 1 0 1 0 1 0 1 0 1 0 VR gain (dB) +0.5 +1.0 +1.5 +2.0 +2.5 +3.0 +3.5 +4.0 +4.5 +5.0 +5.5 +6.0 DTMF register 1 Address A2 A1 A0 0 1 Initial value Data GTP3 to GTP0 GTA3 to GTA0 0 Data D7 D6 D5 D4 D3 D2 D1 D0 GTP3 GTP2 GTP1 GTP0 GTA3 GTA2 GTA1 GTA0 0 1 0 0 0 0 1 0 Function Register for setting DTMF Receiver guard time tGTP. For details, refer to "DTMF Receiver Operation". Register for setting DTMF Receiver guard time tGTA. For details, refer to "DTMF Receiver Operation". MS0583-E-01 Remarks 2008/06 - 19 - ASAHI KASEI 2.4) A3 [AK2363] DTMF register 2 Address A2 A1 A0 0 0 1 1 Initial value Data D7 D6 D5 D4 D3 D2 D1 D0 - STDPGA1 STDPGA0 DTMFSL AGCSW1 AGCSW0 PGA1 PGA0 - 0 0 1 0 1 0 0 PGA gain (dB) 0 0 0 0 1 +4 1 0 +8 1 1 +12 Note When AGC circuit is enable, automatic set PGA gain can be monitored by STDPGA[1:0] register. This register is read-only and synchronized with the rising edge on the DTMF signal detection pin: STD. STDPGA1 Data STDPGA0 Function Item DTMFSL DTMF input switching AGCSW1 AGCSW0 0 0 0 1 1 0 1 1 0 1 DTMFIN pin input RXIN pin input Note Remarks Function AGC circuit Off (Disable) PGA gain can be set with PGA[1:0] register. AGC circuit On (Enable) PGA gain can be monitored by STDPGA[1:0] register. The register data is renewal at every DTMF detection. PGA gain may be set with the latest STDPGA[1:0] register, then AGC is off. PGA gain can not be set with PGA[1:0]. AGC circuit Off (Disable) Remarks Initial value Not used PGA1 PGA0 0 0 1 1 0 1 0 1 PGA gain (dB) 0 +4 +8 +12 When the AGC circuit is disabled, the gain of the PGA circuit can be set manually with PGA[1:0]. MS0583-E-01 2008/06 - 20 - ASAHI KASEI 2.5) [AK2363] Modem frame pattern register (at power-down: specific low-power radio) Address Data A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 F07 F06 F05 F04 F03 F02 F01 F00 1 0 1 0 1 0 0 0 F15 F14 F13 F12 F11 F10 F09 F08 0 0 0 1 1 0 1 1 Initial value 0 1 0 1 Initial value 2.6) Modem receive data register Address Data A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Data Item RD7 to RD0 MSK receive data Remarks 0 1 MSKSL=0 2.4kHz 1.2kHz MSKSL=1 1.8kHz 1.2kHz Data received first is RD7. This register is read-only, and no data can be written to the register. 2.7) Software reset register Address Data A3 A2 A1 A0 0 1 1 1 D7 D5 D4 D3 D2 D1 D0 0 0 0 SRST[7:0] 0 Initial value D6 0 0 0 0 When data 0xAA:10101010 is written to the SRST[7:0] register, a software reset is performed. This sets BS[2:0] to mode 1 (standby) and the registers other than BS[2:0] to their initial values to place the system in the standby state. This register is write-only, and after completion of software reset, the register is set to 0. 2.8) Revision register Address Data A3 A2 A1 A0 D7 D6 D5 D4 1 0 0 0 - - - - - - - - Initial value D3 D2 D1 D0 REVNUM[3:0] 0 0 0 0 When the D3 to D0 data is accessed, the revision number for management can be read. This register is read-only, and no data can be written to the register. MS0583-E-01 2008/06 - 21 - ASAHI KASEI [AK2363] MSK Modem Operation 1) MSK Modulator The TX section of the modem interfaces with the Modulator by using the TCLK, TDATA, and MOD pins and register data BS2, BS1, BS0 (referred to as BS[2:0]), and MSKTX as follows: (1) Set MSKTX to 1 and BS[2:0] to mode 2, 4, or 6 to start MSK transmission. (2) A 1200Hz or 2400Hz clock is output on the TCLK pin. In synchronization with the rising edge of TCLK, the AK2363 reads MSK transmit data from the TDATA pin and outputs the modulated MSK signal on the MOD pin. (3) After as many bits as required have been transmitted, wait for two clock periods until the last bit of the MSK signal has been transmitted. (4) Then, set BS[2:0] to change from mode 2, 4, or 6 to mode 0,1, 3, or 5. Alternatively, set MSKTX to 0 to end signal transmission. MSKTX=1 And [ BS[2:0] = 010 (Mode 2) or BS[2:0] = 100 (Mode 4) or BS[2:0] = 110 (Mode 6)] : Start MSK signal transmission. In synchronization with clock on TCLK pin, read data from TDATA pin and transmit MSK signal on MOD pin : MSK signal transmission in progress No Required bit been transmitted? Yes Wait time 833ms or more (when MSKSL = 0) 1666ms or more (when MSKSL = 1) : MSK data has been transmitted. MSKTX = 0 or [ BS[2:0] = 000 (Mode 0) or BS[2:0] = 001 (Mode 1) or BS[2:0] = 011 (Mode 3) or BS[2:0] = 101 (Mode 5)] : End MSK signal transmission. MS0583-E-01 2008/06 - 22 - ASAHI KASEI [AK2363] 2) MSK Demodulator 2.1) When Frame Detect is not used The modem interfaces with the Demodulator by using the RXIN, RCLK, and RDFFD/RDATA pins, register data BS[2:0], and MSKRCLK as follows: (1) Set BS[2:0] to select mode 3, 4, or 6, and at the same time set MSKRCLK to 1 to start MSK reception. (2) When the MSK signal is received on the RXIN pin, data demodulated via MSK-BPF, Data-Demodulator, and the Digital-PLL circuit is output successively as RDATA on the RDFFD/RDATA pin in synchronization with the falling edge of the 1200Hz or 2400Hz clock signal output on the RCLK pin. (3) Set BS[2:0] to select mode 0, 1, 2, or 5. The MSK signal reception operation then ends. 2.2) When Frame Detect is used The modem interfaces with the Demodulator by using the RXIN, RDFFD/RDATA, SDATA, SCLK, and CSN pins, and register data BS[2:0], MSKRCLK, FSL, and FCLN as follows: (1) Set BS[2:0] to select mode 3, 4, or 6, and at the same time set MSKRCLK to 0, FSL to 0, and FCLN to 0 to start MSK reception. This setting allows the RDFFD/RDATA pin to function as RDFFD frame detection (FD) and output the high level, waiting for a synchronized frame. At this time, the CSN pin is set to the high input level, and the SCLK pin is set to the low input level. (2) When a synchronized frame is detected, the RDFFD/RDATA pin performs a frame detection (FD) operation. The pin is at the low output level during period T, and FCLN data is set to 1 automatically. (3) When the low level on the RDFFD/RDATA pin is monitored, set FSL to 1 so that the MSK receive flag signal (RDF) is output. (4) After 8-bit receive data (MD7 to MD0) is transferred from internal node RDATA_n to the buffer, the RDFFD/RDATA pin is set to the low output level as an RDF operation. (5) When the CPU monitors this change, demodulated data (RD7 to RD0) is read from the modem receive data register (address: A[3:0] = 0110). (6) After the data has been read from the modem receive data register, the RDFFD/RDATA pin is set to the high output level, indicating that data RD7 to RD0 in the buffer has all been read. (7) By repeating steps (4), (5), and (6) above, demodulated data can be read from the receive data register. (8) After completing read of necessary data, set FCLN to 0. Then, internal nodes RCLK and RDATA are initialized, and the system waits for another synchronized frame. (9) Set BS[2:0] to select mode0, 1, 2, or 5. The MSK signal reception operation then ends. This frame detection circuit does not have a reset feature. Therefore, if the above steps (1) to (8) are canceled in the middle, the steps must be restarted from (1). As mentioned in (2), while the RDFFD/RDATA pin is at the low output level as a result of frame detection (FD), the FCLN data is set to 1 automatically. During this period, an attempt to write 0 is ignored. Setting must be made again after the RDFFD/RDATA pin is set to the high output level. MS0583-E-01 2008/06 - 23 - ASAHI KASEI [AK2363] [ BS[2:0] = 011 (Mode 3) or BS[2:0] = 100 (Mode 4) or BS[2:0] = 110 (Mode 6)] : Start MSK signal reception. : Turn on Frame Detect. FCLN = 0 FSL = 0 : Specify output of frame detection signal (FD). Is RDFFD at the low output level? : Wait until synchronized frame is detected. No Yes : Cancel Frame Detect. FCLN = 1 (automatically) : Specify output of receive flag signal (RDF). FSL=1 No Is RDFFD at the low output level? : Wait until 8-bit data is received. Read MSK receive data : RDF is set to high level after MSK receive data is read, and it is set to low level after MSK receive data is updated. : Wait for another synchronized frame. Has all receive data been read? Yes FCLN = 0 [ BS[2:0] = 000 (Mode 0) or BS[2:0] = 001 (Mode 1) or BS[2:0] = 010 (Mode 2) or BS[2:0] = 101 (Mode 5)] : End MSK signal reception. MS0583-E-01 2008/06 - 24 - ASAHI KASEI [AK2363] DTMF Receiver Operation 1) DTMF Receiver The DTMF Receiver detects a received DTMF signal and outputs a 4-bit code. The output 4-bit codes are listed below. Output code table Low tone High tone [Hz] [Hz] 697 770 852 941 697 770 852 941 2) 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 KEY 1 2 3 4 5 6 7 8 9 0 * # A B C D SD3 (MSB) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 SD2 SD1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SD0 (LSB) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Decoding result output The result of DTMF RX signal decoding is output on the SD pin through the internal output buffer. The internal output buffer is controlled with the LOADN pin. LOADN pin input 0 1 SD pin output Decoding result output High level output MS0583-E-01 2008/06 - 25 - ASAHI KASEI 3) [AK2363] Setting the guard time The tone duration accept time (tREC), tone duration reject time (tREJ), interdigit pause accept time (tID), and interdigit pause reject time (tDO) can be set to desired values by adjusting the guard time as shown below. The guard time is set in registers GTPn and GTAn (n = 0 to 3). Tone duration accept time (tREC) = Tone present detection time (tDP) + Guard time (tGTP) Tone duration accept time (tREC) = Tone present detection time (tDP) + Guard time (tGTP) - Tone absent detection time (tDA) Interdigit pause accept time (tID) = Tone absent detection time (tDA) + Guard time (tGTA) Interdigit pause reject time (tDO) = Tone absent detection time (tDA) + Guard time (tGTA) - Tone present detection time (tDP) Guard time (tGTP) setting range Guard time (tGTP) setting step 10ms to 134ms 9ms Guard time (tGTA) setting range Guard time (tGTA) setting step 19ms to 134ms 9ms For the relationships between settings in registers GTPn and GTAn (n = 0 to 3) and guard time values, refer to the tables given below. The tables also show the relationships with the tone duration accept time (tREC) and interdigit pause accept time (tID). Register GTPn (n = 0 to 3) vs. guard time tGTP vs. tone duration accept time tREC (AGC Disable) Min. 5 3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tDP (ms) Typ. 11 GTP register 2 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Max. 16.8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tGTP (ms) Typ. 10 19 28 37 46 54 63 72 81 90 99 108 117 126 134 MS0583-E-01 Min. 15 24 33 42 51 60 68 77 86 95 104 113 122 131 139 tREC(ms) = tGTP + tDP Typ. Max. 21 27 30 36 39 45 48 54 57 63 65 71 74 80 83 89 92 98 101 107 110 116 119 125 128 134 137 143 145 151 2008/06 - 26 - ASAHI KASEI [AK2363] Register GTAn (n = 0 to 3) vs. guard time tGTA vs. interdigit pause accept time tID Min. 0.5 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 tDA (ms) Typ. 4 GTA register 2 1 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Max. 8.5 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tGTA (ms) Typ. 19 28 37 46 54 63 72 81 90 99 108 117 126 134 Min. 19 28 37 46 55 64 73 82 91 99 108 117 126 135 tID(ms) = tGTA + tDA Typ. 23 32 41 50 58 67 76 85 94 103 112 121 130 138 Max. 27 36 45 54 63 72 81 90 99 107 116 125 134 143 Cautions 1) tGTP and tGTA in the tables are typical values. A variation of ±1ms should be considered. 2) If guard time GTPn (n = 0 to 3) is set to 0000, a wrong decoding result may be output. Therefore, avoid such setting. 3) If guard time GTAn (n = 0 to 3) is set to 0000 and 0001, the interdigit pause reject time cannot be acquired. Therefore, avoid such settings. MS0583-E-01 2008/06 - 27 - ASAHI KASEI 4) [AK2363] AGC circuit operation When AGCSW [1:0] register is set to 01, AGC circuit is enable to operate as shown below table. RXINO or DTMFIN pin Input level (dBx) -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 PGA setting Gain (dB) PGA=0dB Internal level (dBx) PGA=+4dB Internal level (dBx) PGA=+8dB Internal level (dBx) PGA=+12dB Internal level (dBx) 0 0 0 0 0 0 0 +4 +4 +4 +4 +8 +8 +8 +8 +12 +12 +12 +12 -21 -22 -23 -24 -25 -26 -27 - -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 - -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 - -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 MS0583-E-01 2008/06 - 28 - ASAHI KASEI [AK2363] Recommended External Circuit Examples 1) TXA amplifier This amplifier is used to adjust the gain of the TX signal and to form a smoothing filter. Because the MSKOUT pin output includes a 115.2kHz sampling clock, it is recommended that this amplifier be used for smoothing. The following gives a sample configuration of a first order LPF with a gain of 0dB and cut-off frequency of 13kHz: 24 MSKOUT 23 MODIN C _ + 22 R1 C=220pF R2 R1=R2=56kW MOD TXA LSI 2) RXA amplifier This amplifier is used for adjusting the gain of the RX signal. Set the gain to 20dB or less. For high frequency noise over 100kHz, form an anti-aliasing filter. The following gives a sample configuration of a second order LPF with a gain of 20dB and cut-off frequency of 39kHz: 19 C1=0.47mF RXINO C2=33pF R3 C2 _ + 20 RXIN R1 C1 R2 C3 RXA 21 C3=560pF R1=10kW R2=9.1kW AGND R3=100kW LSI MS0583-E-01 2008/06 - 29 - ASAHI KASEI [AK2363] 3) External DTMFIN capacitor Connect a capacitor to the DTMFIN pin to adjust the DC offset of the input signal and the internal operation point in the LSI device. This forms a high-pass filter with fc being about 3Hz. 18 DTMFIN C C = 0 . 1m LSI 4) Power supply stabilizing capacitors Connect capacitors between the VDD and VSS pins to eliminate ripple and noise included in power supply as shown below. For maximum effect, the capacitors should be placed at a shortest distance between the pins. 6 VDD VDD C1=0.1mF (Ceramic cap) C2 C1 C2=4.7mF (Electrolytic cap) 14 VSS VSS LSI 5) AGND stabilizing capacitor It is recommended that a capacitor with 0.1mF be connected between VSS and the AGND pin to stabilize the AGND signal. The capacitor should be placed as close to the pin as possible. 21 AGND C C=0.1mF (Electrolytic cap) LSI MS0583-E-01 2008/06 - 30 - ASAHI KASEI [AK2363] 6) Oscillator circuit When the built-in oscillator circuit is to be used, connect a 3.6864MHz crystal oscillator, a resistor, and capacitors as shown in Fig. 1. The internal buffer is designed to allow stable oscillation of a crystal oscillator for the electrical equivalent circuitry with a resonance resistance of 150Ω (Max.) and a shunt capacitance of 5pF (Max.). It is recommended that 22pF capacitors be connected externally so that the total load capacitance is 16pF (5pF + 22pF//22pF) or less. Place the oscillator, resistor, and capacitors as close to the XIN and XOUT pins as possible. When a clock signal is supplied externally, not only 3.6864MHz but also 7.3728MHz (twice higher than 3.6864MHz), 11.0592MHz (three times higher than 3.6864MHz), and 14.7456MHz (four times higher than 3.6864MHz) are supported. However, the internal frequency must always be set to 3.6864MHz by selecting division by 2, 3, or 4 for the divider in the subsequent stage. Connect the clock signal as shown in Fig. 2 or Fig. 3 according to the clock amplitude level. The circuit in the first stage of the XIN pin has a constant threshold voltage (0.8V). Therefore, if the high level of the input clock is 1.5V or higher and the low level is 0.4V or lower, connect the clock signal as shown in Fig. 2. If the input clock amplitude (p-p value) is 0.2V or higher and 1.0V or lower, connect the clock signal as shown in Fig. 3. When the clock is to be shared with peripheral ICs, the clock must be input and output on the XIN pin. The clock amplitude must not exceed the absolute maximum rating. 22pF XIN External Clock IN 15 XIN 3.6864MHz 1MW XOUT 7.3728MHz XOUT 16 22pF LSI Fig. 1 11.0592MHz 14.7456MHz LSI XIN 3.6864MHz Fig. 2 0.01uF External Clock IN 3.6864MHz 1MW 7.3728MHz XOUT 11.0592MHz LSI 14.7456MHz Fig. 3 MS0583-E-01 2008/06 - 31 - ASAHI KASEI [AK2363] Package 1) Marking 2363 XYYZ Parts number Date code 2) Dimensions Package type: 24-pin QFNJ 2363 X: Date of production Ones digit of the calendar year Y: Date of production Week Z: Production lot Identification code (4.0 x 4.0 x 0.75mm, 0.5mm pitch) 2.4±0.15 4.0±0.1 18 13 12 19 Exposed Pad 24 7 6 B 1 0.10 M 0.5 0.2 0.08 PIN♯1 I,D （0.35×45゜） 0.75±0.05 0.23±0.05 0.40±0.1 4.0±0.1 2.4±0.15 A Cautions: The central backside of the package called Exposes Pad should be connected to VSS or no connects. MS0583-E-01 2008/06 - 32 - ASAHI KASEI [AK2363] Important Notice IMPORTANT NOTICE · These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. · AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. · Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. · AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. · It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0583-E-01 2008/06 - 33 -