Fairchild FAN3224 Dual 4a high-speed, low-side gate driver Datasheet

FAN3223 / FAN3224 / FAN3225
Dual 4A High-Speed, Low-Side Gate Drivers
Features
Description
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The FAN3223-25 family of dual 4A gate drivers is
designed to drive N-channel enhancement-mode
MOSFETs in low-side switching applications by
providing high peak current pulses during the short
switching intervals. The driver is available with either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output LOW until the supply voltage is within the
operating range. In addition, the drivers feature
matched internal propagation delays between A and B
channels for applications requiring dual gate drives with
critical timing, such as synchronous rectifiers. This also
enables connecting two drivers in parallel to effectively
double the current capability driving a single MOSFET.
Industry-Standard Pinouts
4.5 to 18V Operating Range
5A Peak Sink/Source at VDD = 12V
4.3A Sink / 2.8A Source at VOUT = 6V
Choice of TTL or CMOS Input Thresholds
Three Versions of Dual Independent Drivers:
-
Dual Inverting + Enable (FAN3223)
Dual Non-Inverting + Enable (FAN3224)
Dual-Inputs (FAN3225)
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Internal Resistors Turn Driver Off If No Inputs
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Double Current Capability by Paralleling Channels
MillerDrive™ Technology
12ns / 9ns Typical Rise/Fall Times with 2.2nF Load
Typical Propagation Delay Under 20ns Matched
within 1ns to the Other Channel
8-Lead 3x3mm MLP or 8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
Applications
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Switch-Mode Power Supplies
High-Efficiency MOSFET Switching
Synchronous Rectifier Circuits
DC-to-DC Converters
The FAN322X drivers incorporate MillerDrive™
architecture for the final output stage. This bipolarMOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability.
The FAN3223 offers two inverting drivers and the
FAN3224 offers two non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FAN3225, each channel has dual
inputs of opposite polarity, which allows configuration
as non-inverting or inverting with an optional enable
function using the second input. If one or both inputs
are left unconnected, internal resistors bias the inputs
such that the output is pulled LOW to hold the power
MOSFET OFF.
Motor Control
FAN3223
FAN3224
FAN3225
Figure 1. Pin Configurations
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
May 2008
Part Number
Logic
Input
Threshold
FAN3223CMPX
FAN3223CMX
FAN3223TMPX
CMOS
Dual Inverting Channels + Dual Enable
TTL
FAN3223TMX
FAN3224CMPX
CMOS
FAN3224CMX
Dual Non-Inverting Channels + Dual
FAN3224TMPX Enable
TTL
FAN3224TMX
FAN3225CMPX
CMOS
FAN3225CMX
Dual Channels of Two-Input / OneFAN3225TMPX Output Drivers
TTL
FAN3225TMX
Package
Packing
Method
Quantity
per Reel
3x3mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
3x3mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
3x3mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
3x3mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
3x3mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
3x3mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s
definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Package Outlines
Figure 2. 3x3mm MLP-8 (Top View)
Figure 3. SOIC-8 (Top View)
Thermal Characteristics(1)
ΘJL
Package
(2)
(3)
(4)
ΘJT
ΘJA
ΨJB
(5)
(6)
ΨJT
Units
8-Lead 3x3mm Molded Leadless Package (MLP)
1.2
64
42
2.8
0.7
°C/W
8-Pin Small Outline Integrated Circuit (SOIC)
38
29
87
41
2.3
°C/W
Notes:
1.
2.
3.
4.
5.
6.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and
JESD51-7, as appropriate.
Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
2
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Ordering Information
FAN3224
FAN3225
Figure 4. Pin Assignments (Repeated)
Pin Definitions
Name
Pin Description
ENA
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENB
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
GND
Ground. Common ground reference for input and output circuits.
INA
Input to Channel A.
INA+
Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA-
Inverting Input to Channel A. Connect to GND to enable output.
INB
Input to Channel B.
INB+
Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB-
Inverting Input to Channel B. Connect to GND to enable output.
OUTA
Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTB
Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
P1
VDD
Supply Voltage. Provides power to the IC.
Output Logic
FAN3223 (x=A or B)
ENx
0
0
INx
FAN3224 (x=A or B)
OUTx
ENx
INx
OUTx
INx+
INx−
OUTx
0
0
(7)
0
1
0
1
1
(7)
0
0
0
0
0
0
(7)
(7)
0
0
1
0
0
(7)
1
1
(7)
(7)
0
1
(7)
1
1
(7)
0
1
(7)
(7)
1
0
0
0
(7)
FAN3225 (x=A or B)
1
1
1
1
Note:
7. Default input signal if no external connection is made.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
3
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
FAN3223
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Block Diagrams
Figure 5. FAN3223 Block Diagram
Figure 6. FAN3224 Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
4
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Block Diagrams
Figure 7. FAN3225 Block Diagram
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
20.0
V
VDD
VDD to PGND
VEN
ENA and ENB to GND
GND - 0.3 VDD + 0.3
V
VIN
INA, INA+, INA–, INB, INB+ and INB– to GND
GND - 0.3 VDD + 0.3
V
OUTA and OUTB to GND
GND - 0.3 VDD + 0.3
V
VOUT
TL
Lead Soldering Temperature (10 Seconds)
TJ
Junction Temperature
TSTG
Storage Temperature
ESD
Electrostatic Discharge
Protection Level
+260
ºC
-55
+150
ºC
-65
+150
ºC
Human Body Model, JEDEC JESD22-A114
4
kV
Charged Device Model, JEDEC JESD22-C101
1
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
4.5
18.0
V
VDD
Supply Voltage Range
VEN
Enable Voltage ENA and ENB
0
VDD
V
VIN
Input Voltage INA, INA+, INA–, INB, INB+ and INB–
0
VDD
V
TA
Operating Ambient Temperature
-40
+125
ºC
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
6
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Absolute Maximum Ratings
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ. Max.
Unit
Supply
VDD
Operating Range
4.5
IDD
Supply Current,
Inputs / EN Not Connected
All except FAN3225C
VON
Turn-On Voltage
INA=ENA=VDD, INB=ENB=0V
VOFF
Turn-Off Voltage
INA=ENA=VDD, INB=ENB=0V
18.0
V
0.70
0.95
mA
0.21
0.35
mA
3.5
3.9
4.3
V
3.3
3.7
4.1
V
0.8
1.2
(8)
FAN3225C
(9)
Inputs (FAN322xT)
VIL_T
INx Logic Low Threshold
VIH_T
INx Logic High Threshold
1.6
V
2.0
V
IIN+
Non-inverting Input
IN from 0 to VDD
-1.5
175.0
µA
IIN-
Inverting Input
IN from 0 to VDD
-175.0
1.5
µA
0.8
V
VHYS_T
TTL Logic Hysteresis Voltage
0.2
0.4
30
38
(9)
Inputs (FAN322xC)
VIL_C
INx Logic Low Threshold
VIH_C
INx Logic High Threshold
55
%VDD
70
%VDD
IINL
IN Current, Low
IN from 0 to VDD
-1
175
µA
IINH
IN Current, High
IN from 0 to VDD
-175
1
µA
VHYS_C
CMOS Logic Hysteresis Voltage
17
%VDD
1.2
V
ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)
VENL
Enable Logic Low Threshold
VENH
Enable Logic High Threshold
VHYS_T
RPU
tD1, tD2
tD1, tD2
TTL Logic Hysteresis Voltage
Enable Pull-up Resistance
EN from 5V to 0V
0.8
EN from 0V to 5V
1.6
(10)
(10)
Propagation Delay, EN Rising
2.0
V
0.4
V
100
kΩ
(11)
0 - 5VIN, 1V/ns Slew Rate
9
17
26
ns
(11)
0 - 5VIN, 1V/ns Slew Rate
11
18
28
ns
Propagation Delay, EN Falling
Continued on the following page…
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
7
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Output
ISINK
OUT Current, Mid-Voltage, Sinking
(10)
ISOURCE
OUT Current, Mid-Voltage, Sourcing
IPK_SINK
OUT Current, Peak, Sinking
IPK_SOURCE
tRISE
tFALL
(10)
OUT Current, Peak, Sourcing
Output Rise Time
Output Fall Time
(10)
(10)
(11)
(11)
tD1, tD2
Output Propagation Delay, CMOS
(11)
Inputs
tD1, tD2
Output Propagation Delay, TTL Inputs
Propagation Matching Between
Channels
IRVS
Output Reverse Current Withstand
(11)
OUT at VDD/2,
CLOAD=0.22µF, f=1kHz
4.3
A
OUT at VDD/2,
CLOAD=0.22µF, f=1kHz
-2.8
A
CLOAD=0.22µF, f=1kHz
5
A
CLOAD=0.22µF, f=1kHz
-5
A
CLOAD=2200pF
12
20
ns
CLOAD=2200pF
9
17
ns
0 - 12VIN, 1V/ns Slew Rate
10
18
29
ns
0 - 5VIN, 1V/ns Slew Rate
9
17
29
ns
2
4
ns
INA=INB, OUTA and OUTB
at 50% point
(10)
500
mA
Notes:
8. Lower supply current due to inactive TTL circuitry.
9. EN inputs have TTL thresholds; refer to the ENABLE section
10. Not tested in production.
11. See Timing Diagrams of Figure 8 and Figure 9.
Timing Diagrams
Figure 8. Non-inverting
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
Figure 9. Inverting
www.fairchildsemi.com
8
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Electrical Characteristics (Continued)
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
(12)
(12)
Figure 10. IDD (Static) vs. Supply Voltage
Figure 11. IDD (Static) vs. Supply Voltage
(12)
Figure 12. IDD (Static) vs. Supply Voltage
Figure 13. IDD (No-Load) vs. Frequency
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
Figure 14. IDD (No-Load) vs. Frequency
www.fairchildsemi.com
9
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 15. IDD (2.2nF Load) vs. Frequency
Figure 17. IDD (Static) vs. Temperature
Figure 16. IDD (2.2nF Load) vs. Frequency
(12)
Figure 18. IDD (Static) vs. Temperature
Figure 19. IDD (Static) vs. Temperature
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
(12)
(12)
www.fairchildsemi.com
10
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 20. Input Thresholds vs. Supply Voltage
Figure 21. Input Thresholds vs. Supply Voltage
Figure 22. Input Threshold % vs. Supply Voltage
Figure 23. Input Thresholds vs. Temperature
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
Figure 24. Input Thresholds vs. Temperature
www.fairchildsemi.com
11
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 25. UVLO Thresholds vs. Temperature
Figure 26. UVLO Threshold vs. Temperature
Figure 27. Propagation Delay vs. Supply Voltage
Figure 28. Propagation Delay vs. Supply Voltage
Figure 29. Propagation Delay vs. Supply Voltage
Figure 30. Propagation Delay vs. Supply Voltage
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
12
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 31. Propagation Delays vs. Temperature
Figure 32. Propagation Delays vs. Temperature
Figure 33. Propagation Delays vs. Temperature
Figure 34. Propagation Delays vs. Temperature
Figure 35. Fall Time vs. Supply Voltage
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
Figure 36.
Rise Time vs. Supply Voltage
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13
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 37.
Rise and Fall Times vs. Temperature
Figure 38. Rise/Fall Waveforms with 2.2nF Load
Figure 39. Rise/Fall Waveforms with 10nF Load
Figure 40. Quasi-Static Source Current
(13)
with VDD=12V
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
(13)
Figure 41. Quasi-Static Sink Current with VDD=12V
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14
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 42. Quasi-Static Source Current
(13)
with VDD=8V
(13)
Figure 43. Quasi-Static Sink Current with VDD=8V
Notes:
12. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases
by the current flowing through the corresponding pull-up/down resistor shown in the block diagram.
13. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the
current-measurement loop.
Test Circuit
Figure 44. Quasi-Static IOUT / VOUT Test Circuit
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
15
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Input Thresholds
MillerDrive™ Gate Drive Technology
Each member of the FAN322x driver family consists of
two identical channels that may be used independently
at rated current or connected in parallel to double the
individual current capacity. In the FAN3223 and
FAN3224, channels A and B can be enabled or
disabled independently using ENA or ENB, respectively.
The EN pin has TTL thresholds for parts with either
CMOS or TTL input thresholds. If ENA and ENB are not
connected, an internal pull-up resistor enables the
driver channels by default. ENA and ENB have TTL
thresholds in parts with either TTL or CMOS INx
threshold. If the channel A and channel B inputs and
outputs are connected in parallel to increase the driver
current capacity, ENA and ENB should be connected
and driven together.
FAN322x gate drivers incorporate the MillerDrive™
architecture shown in Figure 45. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between 1/3 to 2/3
VDD and the MOS devices pull the output to the HIGH or
LOW rail.
The purpose of the MillerDrive™ architecture is to
speed up switching by providing high current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications that have zero voltage switching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast switching even
though the Miller plateau is not present. This situation
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is switched ON.
The FAN322x family offers versions in either TTL or
CMOS input thresholds. In the FAN322xT, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the VDD voltage, and there is a
hysteresis voltage of approximately 0.4V. These levels
permit the inputs to be driven from a range of input logic
signal levels for which a voltage over 2V is considered
logic HIGH. The driving signal for the TTL inputs should
have fast rising and falling edges with a slew rate of
6V/µs or faster, so a rise time from 0 to 3.3V should be
550ns or less. With reduced slew rate, circuit noise
could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the driver input,
causing erratic operation.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall
time at the MOSFET gate is needed.
In the FAN322xC, the logic input thresholds are
dependent on the VDD level and, with VDD of 12V, the
logic rising edge threshold is approximately 55% of VDD
and the input falling edge threshold is approximately
38% of VDD. The CMOS input configuration offers a
hysteresis voltage of approximately 17% of VDD. The
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
window. This allows setting precise timing intervals by
fitting an R-C circuit between the controlling signal and
the IN pin of the driver. The slow rising edge at the IN
pin of the driver introduces a delay between the
controlling signal and the OUT pin of the driver.
Figure 45. MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN322x start-up logic is optimized to drive
ground-referenced N-channel MOSFETs with an undervoltage lockout (UVLO) function to ensure that the IC
starts up in an orderly fashion. When VDD is rising, yet
below the 3.9V operational level, this circuit holds the
output LOW, regardless of the status of the input pins.
After the part is active, the supply voltage must drop
0.2V before the part shuts down. This hysteresis helps
prevent chatter when low VDD supply voltages have
noise from the power switching. This configuration is not
suitable for driving high-side P-channel MOSFETs
because the low output voltage of the driver would turn
the P-channel MOSFET ON with VDD below 3.9V.
Static Supply Current
In the IDD (static) typical performance characteristics
(Figure 10 - Figure 12 and Figure 17 - Figure 19), the
curve is produced with all inputs/enables floating (OUT
is low) and indicates the lowest static IDD current for the
tested configuration. For other states, additional current
flows through the 100kΩ resistors on the inputs and
outputs shown in the block diagram of each part (see
Figure 5 - Figure 7). In these cases, the actual static IDD
current is the value obtained from the curves plus this
additional current.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
16
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Applications Information
To enable this IC to turn a device ON quickly, a local
high-frequency bypass capacitor CBYP with low ESR and
ESL should be connected between the VDD and GND
pins with minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10µF to 47µF
commonly found on driver and controller bias circuits.
ƒ
The FAN322x is compatible with many other
industry-standard drivers. In single input parts with
enable pins, there is an internal 100kΩ resistor tied
to VDD to enable the driver by default; this should
be considered in the PCB layout.
ƒ
The turn-on and turn-off current paths should be
minimized, as discussed in the following section.
Figure 46 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn
the MOSFET ON. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance
in the path should be minimized. The localized CBYP
acts to contain the high peak current pulses within this
driver-MOSFET circuit, preventing them from disturbing
the sensitive analog circuitry in the PWM controller.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤5%. This
is often achieved with a value ≥20 times the equivalent
load capacitance CEQV, defined here as QGATE/VDD.
Ceramic capacitors of 0.1µF to 1µF or larger are
common choices, as are dielectrics, such as X5R and
X7R with good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
switching simultaneously, the combined peak current
sourced from the CBYP would be twice as large as when
a single channel is switching.
Layout and Connection Guidelines
The FAN3223-25 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays,
and powerful output stages capable of delivering
current peaks over 4A to facilitate voltage transition
times from under 10ns to over 150ns. The following
layout and connection guidelines are strongly
recommended:
ƒ
Keep high-current output and power ground paths
separate logic and enable input signals and signal
ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.
ƒ
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve highspeed switching, while reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
ƒ
If the inputs to a channel are not externally
connected, the internal 100kΩ resistors indicated
on block diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to VDD or GND using short
traces to prevent noise from causing spurious
output switching.
ƒ
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output retriggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads. For
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
Figure 46. Current Path for MOSFET Turn-on
Figure 47 shows the current path when the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Figure 47. Current Path for MOSFET Turn-off
www.fairchildsemi.com
17
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
best results, make connections to all pins as short
and direct as possible.
VDD Bypass Capacitor Guidelines
Operational Waveforms
The FAN3225 truth table indicates the operational states
using the dual-input configuration. In a non-inverting
driver configuration, the IN- pin should be a logic LOW
signal. If the IN- pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN+ pin.
At power-up, the driver output remains LOW until the
VDD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises with VDD until
steady-state VDD is reached. The non-inverting
operation illustrated in Figure 50 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase with the input.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
In the non-inverting driver configuration in Figure 48,
the IN- pin is tied to ground and the input signal (PWM)
is applied to IN+ pin. The IN- pin can be connected to
logic HIGH to disable the driver and the output remains
LOW, regardless of the state of the IN+ pin.
VDD
PWM
IN+
IN-
FAN3225
OUT
GND
Figure 50. Non-Inverting Start-Up Waveforms
For the inverting configuration of Figure 49, start-up
waveforms are shown in Figure 51. With IN+ tied to
VDD and the input signal applied to IN–, the OUT
pulses are inverted with respect to the input. At powerup, the inverted output remains LOW until the VDD
voltage reaches the turn-on threshold, then it follows
the input with inverted phase.
Figure 48. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application in Figure 49, the IN+
pin is tied HIGH. Pulling the IN+ pin to GND forces the
output LOW, regardless of the state of the IN- pin.
VDD
VDD
IN+
PWM
IN-
FAN3225
Turn-on threshold
IN-
OUT
IN+
(VDD)
GND
Figure 49. Dual-Input Driver Enabled,
Inverting Configuration
OUT
Figure 51. Inverting Start-Up Waveforms
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
18
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Truth Table of Logic Operation
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
To give a numerical example, if the synchronous
rectifier switches in the forward converter of Figure 52
are FDMS8660S, the datasheet gives a total gate
charge of 60nC at VGS = 7V, so two devices in parallel
would have 120nC gate charge. At a switching
frequency of 300kHz, the total power dissipation is:
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC
(1)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET ON and OFF at
the switching frequency. The power dissipation that
results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at
switching frequency, FSW , is determined by:
PGATE = QG • VGS • FSW • n
(2)
Dynamic Pre-drive / Shoot-through Current: A
power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-down resistors, can be
obtained using the “IDD (No-Load) vs. Frequency”
graphs in Typical Performance Characteristics to
determine the current IDYNAMIC drawn from VDD
under actual operating conditions:
= PTOTAL • ψ JB + TB
PDYNAMIC = 1.5mA • 7V • 2 = 0.021W
(6)
PTOTAL = 0.52W
(7)
TB,MAX = TJ - PTOTAL • ψ JB
(8)
TB,MAX = 120°C – 0.52W • 42°C/W = 98°C
(9)
For comparison, replace the SOIC-8 used in the
previous example with the 3x3mm MLP package with
ψ JB = 2.8°C/W. The 3x3mm MLP package could
operate at a PCB temperature of 118°C, while
maintaining the junction temperature below 120°C. This
illustrates that the physically smaller MLP package with
thermal pad offers a more conductive path to remove
the heat from the driver. Consider tradeoffs between
reducing overall circuit size with junction temperature
reduction for increased reliability.
(3)
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
assuming ψ JB was determined for a similar thermal
design (heat sinking and air flow):
TJ
(5)
The SOIC-8 has a junction-to-board thermal
characterization parameter of ψ JB = 42°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along with airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; with 80%
derating, TJ would be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
n is the number of driver channels in use (1 or 2).
PDYNAMIC = IDYNAMIC • VDD • n
PGATE = 120nC • 7V • 300kHz • 2 = 0.5W
(4)
where:
= driver junction temperature
TJ
ψ JB = (psi) thermal characterization parameter relating
temperature rise to total power dissipation
TB = board temperature in location as defined in
the Thermal Characteristics table.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
19
Figure 52. High Current Forward Converter
with Synchronous Rectification
Vin
Figure 53.
QC
QA
QD
QB
Center-tapped Bridge Output with
Synchronous Rectifiers
FAN3224
PWM-A
FAN3227
SR-1
PWM-B
Secondary
Phase Shift
Controller
SR-2
PWM-C
FAN3227
PWM-D
Figure 54. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous Rectifiers
(Simplified)
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
20
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Typical Application Diagrams
Related Products
Gate
(14)
Drive
(Sink/Src)
Input
Threshold
Part
Number
Type
FAN3100C
Single 2A
+2.5A / -1.8A
CMOS
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
FAN3100T
Single 2A
+2.5A / -1.8A
TTL
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
FAN3226C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3226T
Dual 2A
+2.4A / -1.6A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227T
Dual 2A
+2.4A / -1.6A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3228C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3228T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3229C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3229T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3223C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3223T
Dual 4A
+4.3A / -2.8A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224T
Dual 4A
+4.3A / -2.8A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3225C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3225T
Dual 4A
+4.3A / -2.8A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
Logic
Package
Note:
14. Typical currents with OUT at 6V and VDD = 12V.
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
21
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Table 1.
2X
2X
0.8 MAX
RECOMMENDED LAND PATTERN
0.05
0.00
SEATING
PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION VEEC, DATED 11/2001
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. FILENAME: MKT-MLP08Drev2
Figure 55. 3x3mm, 8-Lead Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
22
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Physical Dimensions
5.00
4.80
A
0.65
3.81
5
8
6.20
5.80
PIN ONE
INDICATOR
B
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 56. 8-Lead SOIC
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
23
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
Physical Dimensions (Continued)
FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
www.fairchildsemi.com
24