Samsung K6X8008C2B 1mx8 bit low power and low voltage cmos static ram Datasheet

K6X8008C2B Family
CMOS SRAM
Document Title
1Mx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft
October 31, 2002
Preliminary
0.1
Revised
- Deleted 44-TSOP2-400R package type.
- Added Commercial product.
December 11, 2002
Preliminary
1.0
Finalized
- Changed ICC from 10mA to 6mA
- Changed ICC1 from 10mA to 7mA
- Changed ICC2 from 50mA to 35mA
- Changed ISB from 3mA to 0.4mA
- Changed ISB1(Commercial) from 40µA to 25µA
- Changed ISB1(industrial) from 40µA to 25µA
- Changed ISB1(Automotive) from 50µA to 40µA
- Changed IDR(Commercial) from 30µA to 15µA
- Changed IDR(industrial) from 30µA to 15µA
- Changed IDR(Automotive) from 40µA to 30µA
September 16, 2003 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
1Mx8 bit Low Power full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 1M x8
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2.0V(Min)
• Three state output and TTL Compatible
• Package Type: 44-TSOP2-400F
The K6X8008C2B families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support various operating temperature range for user flexibility of
system design. The families also support low data retention
voltage for battery back-up operation with low data retention
current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
K6X8008C2B-B
Commercial(0~70°C)
K6X8008C2B-F
Industrial(-40~85°C)
K6X8008C2B-Q
Automotive(-40~125°C)
Vcc Range
Speed
4.5~5.5V
551)/70ns
Standby
(ISB1, Max)
Operating
(ICC2, Max)
PKG Type
25µA
35mA
25µA
44-TSOP2-400F
40µA
1. The parameter is measured with 50pF test load.
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Clk gen.
A4
A3
A2
A1
A0
CS1
NC
NC
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
NC
NC
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-TSOP2
Forward
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CS2
A8
NC
NC
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
NC
NC
A9
A10
A11
A12
A13
A14
Precharge circuit.
Vcc
Vss
Row
Addresses
I/O1~I/O8
Row
select
Data
cont
Memory array
I/O Circuit
Column select
Data
cont
Column Addresses
Name
CS1, CS2
Function
Name
Function
Chip Select Inputs
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
I/O1~I/O8
Data Inputs/Outputs
A0~A19 Address Inputs
NC
No Connect
CS1
CS2
OE
Control Logic
WE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°C)
Industrial Products(-40~85°C)
Automotive Products(-40~125°C)
Part Name
Function
Part Name
Function
Part Name
Function
K6X8008C2B-TB55
K6X8008C2B-TB70
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
K6X8008C2B-TF55
K6X8008C2B-TF70
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
K6X8008C2B-TQ55
K6X8008C2B-TQ70
44-TSOP2-F, 55ns, L
44-TSOP2-F, 70ns, L
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O1~8
Mode
Power
H
X
X
X
High-Z
Deselected
Standby
X
L
X
X
High-Z
Deselected
Standby
L
H
H
H
High-Z
Output Disabled
Active
L
H
L
H
Dout
Read
Active
L
H
X
L
Din
Write
Active
Note: X means don′t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
Remark
VIN, VOUT
-0.5 to VCC+0.5V(max.7.0V)
V
-
Voltage on Vcc supply relative to Vss
VCC
-0.3 to 7.0
V
-
Power Dissipation
PD
1.0
W
-
TSTG
-65 to 150
°C
-
0 to 70
°C
K6X8008C2B-B
-40 to 85
°C
K6X8008C2B-F
-40 to 125
°C
K6X8008C2B-Q
Voltage on any pin relative to Vss
Storage temperature
Operating Temperature
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Symbol
Product
Min
Typ
Max
Unit
Supply voltage
Item
Vcc
K6X8008C2B Family
4.5
5.0
5.5
V
Ground
Vss
All Family
0
0
0
V
Input high voltage
VIH
K6X8008C2B Family
2.2
-
Vcc+0.52)
V
Input low voltage
VIL
K6X8008C2B Family
-0.53)
-
0.8
V
Note:
1. Commercial Product: TA=0 to 70°C, otherwise specified.
Industrial Product: TA=-40 to 85°C, otherwise specified.
Automotive Product: TA=-40 to 125°C, otherwise specified.
2. Overshoot: VCC+3.0V in case of pulse width ≤30ns.
3. Undershoot: -3.0V in case of pulse width ≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Symbol
Test Condition
Min
Max
Unit
Input capacitance
Item
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Symbol
Test Conditions
Min Typ Max Unit
µA
ILI
VIN=Vss to Vcc
-1
-
1
Output leakage current
ILO
CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
Operating power supply current
ICC
IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIH or VIL
-
-
6
mA
ICC1
Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V,
CS2≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
-
-
7
mA
ICC2
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH,
VIN=VIL or VIH
-
-
35
mA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.4
-
-
V
Standby Current(TTL)
ISB
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
0.4
mA
K6X8008C2B-B
-
-
25
ISB1
Other input =0~Vcc,
1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V (CS1 controlled) or 2) 0V≤CS2≤0.2V(CS2 controlled)
K6X8008C2B-F
-
-
25
K6X8008C2B-Q
-
-
40
Average operating current
Standby Current(CMOS)
4
µA
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1.Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C)
Speed Bins
Parameter List
Symbol
Write
Units
70ns
Min
Max
Min
Max
tRC
55
-
70
-
ns
Address Access Time
tAA
-
55
-
70
ns
Chip Select to Output
tCO
-
55
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
35
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
20
0
25
ns
Output Disable to High-Z Output
tOHZ
0
20
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write Cycle Time
tWC
55
-
70
-
ns
Chip Select to End of Write
tCW
45
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Read Cycle Time
Read
55ns
Address Valid to End of Write
tAW
45
-
60
-
ns
Write Pulse Width
tWP
40
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
20
ns
Data to Write Time Overlap
tDW
25
-
30
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
VDR
Test Condition
CS1≥Vcc-0.2V
1)
Min
Typ
Max
Unit
2.0
-
5.5
V
K6X8008C2B-B
Data retention current
IDR
Vcc=3.0V, CS1≥Vcc-0.2V1)
K6X8008C2B-F
15
-
-
K6X8008C2B-Q
Data retention set-up time
tSDR
Recovery time
tRDR
See data retention waveform
15
µA
30
0
-
-
5
-
-
ms
1. CS1≥Vcc-0.2V,CS2≥Vcc-0.2V(CS1 controlled) or CS2≥Vcc-0.2V(CS2 controlled).
5
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
Data out
High-Z
tOHZ
tOLZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
7
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC
tSDR
Data Retention Mode
tRDR
4.5V
2.2V
VDR
CS1≥VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
4.5V
CS2
tSDR
tRDR
VDR
0.4V
CS2≤0.2V
GND
8
Revision 1.0
September 2003
K6X8008C2B Family
CMOS SRAM
PACKAGE DIMENSIONS
Unit: millimeters(inches)
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
(
)
0.010
#44
#23
10.16
0.400
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
( 0.50 )
0.020
#1
#22
1.00±0.10
0.039±0.004
1.20
MAX.
0.047
( 0.805 )
0.032
0.35± 0.10
0.014±0.004
0.80
0.0315
0.05
MIN.
0.002
18.81
MAX.
0.741
18.41±0.10
0.725±0.004
9
0
+ 0.1
5
- 0.0
04
.0
+0
02
.006 - 0.0
0.15
0
0.10
0.004 MAX
Revision 1.0
September 2003
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