ON MC34262DR2G Power factor controller Datasheet

MC34262, MC33262
Power Factor Controllers
The MC34262/MC33262 are active power factor controllers
specifically designed for use as a preconverter in electronic ballast
and in off−line power converter applications. These integrated
circuits feature an internal startup timer for stand−alone applications,
a one quadrant multiplier for near unity power factor, zero current
detector to ensure critical conduction operation, transconductance
error amplifier, quickstart circuit for enhanced startup, trimmed
internal bandgap reference, current sensing comparator, and a totem
pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of an overvoltage
comparator to eliminate runaway output voltage due to load removal,
input undervoltage lockout with hysteresis, cycle−by−cycle current
limiting, multiplier output clamp that limits maximum peak switch
current, an RS latch for single pulse metering, and a drive output high
state clamp for MOSFET gate protection. These devices are
available in dual−in−line and surface mount plastic packages.
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POWER FACTOR
CONTROLLERS
MARKING
DIAGRAMS
8
Features
•
•
•
•
•
•
•
•
•
•
Overvoltage Comparator Eliminates Runaway Output Voltage
Internal Startup Timer
One Quadrant Multiplier
Zero Current Detector
Trimmed 2% Internal Bandgap Reference
Totem Pole Output with High State Clamp
Undervoltage Lockout with 6.0 V of Hysteresis
Low Startup and Operating Current
Supersedes Functionality of SG3561 and TDA4817
Pb−Free Packages are Available
Zero Current Detector
5
2.5V
Reference
Undervoltage
Lockout
Zero Current
Detect Input
VCC
PDIP−8
P SUFFIX
CASE 626
MC3x262P
AWL
YYWWG
8
1
1
8
3x262
ALYW
G
SOIC−8
D SUFFIX
CASE 751
8
1
1
x
A
WL, L
YY, Y
WW, W
G
G
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
8
PIN CONNECTIONS
Drive Output
7
Multiplier,
Latch,
PWM,
Timer,
&
Logic
Overvoltage
Comparator
+
4
Current Sense
Input
Voltage Feedback
Input
Compensation
Multiplier Input
Current Sense
Input
1
8 VCC
2
7 Drive Output
6 GND
5 Zero Current
Detect Input
3
4
(Top View)
1.08 Vref
ORDERING INFORMATION
Error Amp
Multiplier
Input 3
+
Multiplier
Vref
Quickstart
GND
6
Compensation
Voltage
Feedback
1 Input
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
2
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 9
1
Publication Order Number:
MC34262/D
MC34262, MC33262
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
(ICC + IZ)
30
mA
Output Current, Source or Sink (Note 1)
IO
500
mA
Current Sense, Multiplier, and Voltage Feedback Inputs
Vin
−1.0 to +10
V
Zero Current Detect Input
High State Forward Current
Low State Reverse Current
Iin
Total Power Supply and Zener Current
mA
50
−10
Power Dissipation and Thermal Characteristics
P Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance, Junction−to−Air
D Suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance, Junction−to−Air
PD
RqJA
800
100
mW
°C/W
PD
RqJA
450
178
mW
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature (Note 3)
MC34262
MC33262
TA
Storage Temperature
Tstg
°C
0 to + 85
− 40 to +105
− 65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (VCC = 12 V (Note 2), for typical values TA = 25°C, for min/max values TA is the operating
ambient temperature range that applies (Note 3), unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
2.465
2.44
2.5
−
2.535
2.54
Regline
−
1.0
10
mV
Input Bias Current (VFB = 0 V)
IIB
−
− 0.1
− 0.5
mA
Transconductance (TA = 25°C)
gm
80
100
130
mmho
Output Current
Source (VFB = 2.3 V)
Sink (VFB = 2.7 V)
IO
−
−
10
10
−
−
VOH(ea)
VOL(ea)
5.8
−
6.4
1.7
−
2.4
VFB(OV)
1.065 VFB
1.08 VFB
1.095 VFB
V
IIB
−
− 0.1
− 0.5
mA
Vth(M)
1.05 VOL(EA)
1.2 VOL(EA)
−
V
ERROR AMPLIFIER
Voltage Feedback Input Threshold
TA = 25°C
TA = Tlow to Thigh (VCC = 12 V to 28 V)
VFB
Line Regulation (VCC = 12 V to 28 V, TA = 25°C)
Output Voltage Swing
High State (VFB = 2.3 V)
Low State (VFB = 2.7 V)
V
mA
V
OVERVOLTAGE COMPARATOR
Voltage Feedback Input Threshold
MULTIPLIER
Input Bias Current, Pin 3 (VFB = 0 V)
Input Threshold, Pin 2
1. Maximum package power dissipation limits must be observed.
2. Adjust VCC above the startup threshold before setting to 12 V.
3. Tlow = 0°C for MC34262
Thigh = +85°C for MC34262
= −40°C for MC33262
= +105°C for MC33262.
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MC34262, MC33262
ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V (Note 5), for typical values TA = 25°C, for min/max values TA is the
operating ambient temperature range that applies (Note 6), unless otherwise noted.)
Symbol
Min
Typ
Max
VPin 3
VPin 2
0 to 2.5
Vth(M) to
(Vth(M) + 1.0)
0 to 3.5
Vth(M) to
(Vth(M) + 1.5)
−
−
K
0.43
0.65
0.87
1/V
Input Threshold Voltage (Vin Increasing)
Vth
1.33
1.6
1.87
V
Hysteresis (Vin Decreasing)
VH
100
200
300
mV
Input Clamp Voltage
High State (IDET = + 3.0 mA)
Low State (IDET = − 3.0 mA)
VIH
VIL
6.1
0.3
6.7
0.7
−
1.0
Input Bias Current (VPin 4 = 0 V)
IIB
−
− 0.15
−1.0
mA
Input Offset Voltage (VPin 2 = 1.1 V, VPin 3 = 0 V)
VIO
−
9.0
25
mV
Vth(max)
1.3
1.5
1.8
V
tPHL(in/out)
−
200
400
ns
VOL
−
−
9.8
7.8
0.3
2.4
10.3
8.4
0.8
3.3
−
−
14
16
18
Characteristic
Unit
MULTIPLIER
Dynamic Input Voltage Range
Multiplier Input (Pin 3)
Compensation (Pin 2)
V
Multiplier Gain (VPin 3 = 0.5 V, VPin 2 = Vth(M) + 1.0 V) (Note 7)
ZERO CURRENT DETECTOR
V
CURRENT SENSE COMPARATOR
Maximum Current Sense Input Threshold (Note 8)
Delay to Output
DRIVE OUTPUT
Output Voltage (VCC = 12 V)
Low State
(ISink = 20 mA)
Low State
(ISink = 200 mA)
High State (ISource = 20 mA)
High State (ISource = 200 mA)
V
VOH
Output Voltage (VCC = 30 V)
High State (ISource = 20 mA, CL = 15 pF)
VO(max)
Output Voltage Rise Time (CL = 1.0 nF)
tr
−
50
120
ns
Output Voltage Fall Time (CL = 1.0 nF)
tf
−
50
120
ns
VO(UVLO)
−
0.1
0.5
V
tDLY
200
620
−
ms
Vth(on)
11.5
13
14.5
V
VShutdown
7.0
8.0
9.0
V
VH
3.8
5.0
6.2
V
−
−
−
0.25
6.5
9.0
0.4
12
20
30
36
−
Output Voltage with UVLO Activated
(VCC = 7.0 V, ISink = 1.0 mA)
V
RESTART TIMER
Restart Time Delay
UNDERVOLTAGE LOCKOUT
Startup Threshold (VCC Increasing)
Minimum Operating Voltage After Turn−On (VCC Decreasing)
Hysteresis
TOTAL DEVICE
Power Supply Current
Startup (VCC = 7.0 V)
Operating
Dynamic Operating (50 kHz, CL = 1.0 nF)
ICC
Power Supply Zener Voltage (ICC = 25 mA)
VZ
4. Maximum package power dissipation limits must be observed.
5. Adjust VCC above the startup threshold before setting to 12 V.
6. Tlow = 0°C for MC34262
Thigh = +85°C for MC34262
= −40°C for MC33262
= +105°C for MC33262.
Pin 4 Threshold
7. K +
VPin 3 (VPin2 * Vth(M))
8. This parameter is measured with VFB = 0 V, and VPin 3 = 3.0 V.
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3
mA
V
VCS, CURRENT SENSE PIN 4 THRESHOLD (V)
1.6
VCC = 12 V
TA = 25°C
1.4
1.2
VPin 2 = 3.75 V
VPin 2 = 3.5 V
1.0
VPin 2 = 2.75 V
VPin 2 = 3.25 V
0.8
VPin 2 = 2.5 V
VPin 2 = 3.0 V
0.6
VPin 2 = 2.25 V
0.4
0.2
VPin 2 = 2.0 V
0
−0.2
0.6
1.4
2.2
3.0
3.8
0.08
VPin 2 = 3.75 V
VPin 2 = 3.5 V
VPin 2 = 3.25 V
0.06 VPin 2 = 3.0 V
0.05 VPin 2 = 2.75 V
0.07
0.02
DVFB(OV), OVERVOLTAGE INPUT THRESHOLD (%VFB)
DVFB, VOLTAGE FEEDBACK THRESHOLD CHANGE (mV)
VCC = 12 V
Pins 1 to 2
0
−4.0
−8.0
−12
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
0
−0.12
0.24
VCC = 12 V
109
108
107
106
−55
−25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Overvoltage Comparator Input
Threshold versus Temperature
0
Transconductance
80
VCC = 12 V
VO = 2.5 V to 3.5 V
RL = 100 k to 3.0 V
CL = 2.0 pF
TA = 25°C
4.00 V
30
60
60
90
40
120
20
150
0
3.0 k
10 k
30 k
100 k 300 k
f, FREQUENCY (Hz)
3.25 V
2.50 V
180
3.0 M
1.0 M
VCC = 12 V
RL = 100 k
CL = 2.0 pF
TA = 25°C
0
Phase
q, EXCESS PHASE (DEGREES)
120
gm, TRANSCONDUCTANCE (mmho)
−0.06
0
0.06
0.12
0.18
VM, MULTIPLIER PIN 3 INPUT VOLTAGE (V)
110
Figure 4. Voltage Feedback Input Threshold
Change versus Temperature
100
VPin 2 = 2.0 V
0.01
Figure 3. Current Sense Input Threshold
versus Multiplier Input, Expanded View
4.0
0
VPin 2 = 2.25 V
0.03
Figure 2. Current Sense Input Threshold
versus Multiplier Input
−25
VPin 2 = 2.5 V
0.04
VM, MULTIPLIER PIN 3 INPUT VOLTAGE (V)
−16
−55
VCC = 12 V
TA = 25°C
V/DIV
VCS, CURRENT SENSE PIN 4 THRESHOLD (V)
MC34262, MC33262
Figure 6. Error Amp Transconductance and
Phase versus Frequency
5.0 ms/DIV
Figure 7. Error Amp Transient Response
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4
1.76
800
1.72
700
Voltage
Current
600
1.68
1.64
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
500
125
100
800
VCC = 12 V
700
600
500
400
−55
Figure 8. Quickstart Charge Current
versus Temperature
Vsat, OUTPUT SATURATION VOLTAGE (V)
Vth, THRESHOLD VOLTAGE (V)
VCC = 12 V
1.6
1.5
1.4
Lower Threshold
(Vin, Decreasing)
1.3
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
0
VCC
100
125
VCC = 12 V
80 ms Pulsed Load
120 Hz Rate
−2.0
Source Saturation
(Load to Ground)
−4.0
−6.0
4.0
Sink Saturation
(Load to VCC)
2.0
0
GND
0
80
160
240
320
IO, OUTPUT LOAD CURRENT (mA)
Figure 11. Output Saturation Voltage
versus Load Current
VO , OUTPUT VOLTAGE
Figure 10. Zero Current Detector Input
Threshold Voltage versus Temperature
VCC = 12 V
CL = 15 pF
TA = 25°C
10%
100 ns/DIV
Figure 12. Drive Output Waveform
100 mA/DIV
I CC , SUPPLY CURRENT
VCC = 12 V
CL = 1.0 nF
TA = 25°C
90%
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Restart Timer Delay
versus Temperature
1.7
Upper Threshold
(Vin, Increasing)
−25
100 ns/DIV
Figure 13. Drive Output Cross Conduction
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5
5.0 V/DIV
Vchg, QUICKSTART CHARGE VOLTAGE (V)
VCC = 12 V
tDLY, RESTART TIME DELAY (ms)
900
1.80
Ichg, QUICKSTART CHARGE CURRENT (mA)
MC34262, MC33262
MC34262, MC33262
14
VCC , SUPPLY VOLTAGE (V)
I CC , SUPPLY CURRENT (mA)
16
12
8.0
VFB = 0 V
Current Sense = 0 V
Multiplier = 0 V
CL = 1.0 nF
f = 50 kHz
TA = 25°C
4.0
0
0
10
20
30
VCC, SUPPLY VOLTAGE (V)
13
Startup Threshold
(VCC Increasing)
12
11
10
9.0
Minimum Operating Threshold
(VCC Decreasing)
8.0
7.0
−55
40
Figure 14. Supply Current
versus Supply Voltage
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 15. Undervoltage Lockout Thresholds
versus Temperature
FUNCTIONAL DESCRIPTION
Introduction
frequency switching converter for the power processing,
with the boost converter being the most popular topology,
Figure 17. Since active input circuits operate at a frequency
much higher than that of the ac line, they are smaller,
lighter in weight, and more efficient than a passive circuit
that yields similar results. With proper control of the
preconverter, almost any complex load can be made to
appear resistive to the ac line, thus significantly reducing
the harmonic current content.
With the goal of exceeding the requirements of
legislation on line−current harmonic content, there is an
ever increasing demand for an economical method of
obtaining a unity power factor. This data sheet describes a
monolithic control IC that was specifically designed for
power factor control with minimal external components. It
offers the designer a simple, cost−effective solution to
obtain the benefits of active power factor correction.
Most electronic ballasts and switching power supplies
use a bridge rectifier and a bulk storage capacitor to derive
raw dc voltage from the utility ac line, Figure 15.
Rectifiers
Vpk
Rectified
DC
Converter
AC
Line
0
+
Bulk
Storage
Capacitor
Line Sag
Load
AC Line
Voltage
Figure 16. Uncorrected Power Factor Circuit
0
AC Line
Current
This simple rectifying circuit draws power from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and results
in a high charge current spike, Figure 16. Since power is
only taken near the line voltage peaks, the resulting spikes
of current are extremely nonsinusoidal with a high content
of harmonics. This results in a poor power factor condition
where the apparent input power is much higher than the real
power. Power factor ratios of 0.5 to 0.7 are common.
Power factor correction can be achieved with the use of
either a passive or an active input circuit. Passive circuits
usually contain a combination of large capacitors,
inductors, and rectifiers that operate at the ac line
frequency. Active circuits incorporate some form of a high
Figure 17. Uncorrected Power Factor
Input Waveforms
The MC34262, MC33262 are high performance, critical
conduction, current−mode power factor controllers
specifically designed for use in off−line active
preconverters. These devices provide the necessary
features required to significantly enhance poor power
factor loads by keeping the ac line current sinusoidal and
in phase with the line voltage.
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6
MC34262, MC33262
Operating Description
UC3842 series. Referring to the block diagram in
Figure 19, note that a multiplier has been added to the
current sense loop and that this device does not contain an
oscillator. The reasons for these differences will become
apparent in the following discussion. A description of each
of the functional blocks is given below.
The MC34262, MC33262 contain many of the building
blocks and protection features that are employed in modern
high performance current mode power supply controllers.
There are, however, two areas where there is a major
difference when compared to popular devices such as the
Rectifiers
PFC Preconverter
AC
Line
+
High
Frequency
Bypass
Capacitor
Converter
+
MC34362
Bulk
Storage
Capacitor
Load
Figure 18. Active Power Factor Correction Preconverter
Error Amplifier
can occur during initial startup, sudden load removal, or
during output arcing and is the result of the low bandwidth
that must be used in the Error Amplifier control loop. The
Overvoltage Comparator monitors the peak output voltage
of the converter, and when exceeded, immediately
terminates MOSFET switching. The comparator threshold
is internally set to 1.08 Vref. In order to prevent false
tripping during normal operation, the value of the output
filter capacitor C3 must be large enough to keep the
peak−to−peak ripple less than 16% of the average dc
output. The Overvoltage Comparator input to Drive Output
turn−off propagation delay is typically 400 ns. A
comparison of startup overshoot without and with the
Overvoltage Comparator circuit is shown in Figure 23.
An Error Amplifier with access to the inverting input and
output is provided. The amplifier is a transconductance
type, meaning that it has high output impedance with
controlled voltage−to−current gain. The amplifier features
a typical gm of 100 mmhos (Figure 5). The noninverting
input is internally biased at 2.5 V ± 2.0% and is not pinned
out. The output voltage of the power factor converter is
typically divided down and monitored by the inverting
input. The maximum input bias current is − 0.5 mA, which
can cause an output voltage error that is equal to the product
of the input bias current and the value of the upper divider
resistor R2. The Error Amp output is internally connected
to the Multiplier and is pinned out (Pin 2) for external loop
compensation. Typically, the bandwidth is set below 20 Hz,
so that the amplifier’s output voltage is relatively constant
over a given ac line cycle. In effect, the error amp monitors
the average output voltage of the converter over several
line cycles. The Error Amp output stage was designed to
have a relatively constant transconductance over
temperature. This allows the designer to define the
compensated bandwidth over the intended operating
temperature range. The output stage can sink and source
10 mA of current and is capable of swinging from 1.7 V to
6.4 V, assuring that the Multiplier can be driven over its
entire dynamic range.
A key feature to using a transconductance type amplifier,
is that the input is allowed to move independently with
respect to the output, since the compensation capacitor is
connected to ground. This allows dual usage of of the
Voltage Feedback Input pin by the Error Amplifier and by
the Overvoltage Comparator.
Multiplier
A single quadrant, two input multiplier is the critical
element that enables this device to control power factor.
The ac full wave rectified haversines are monitored at Pin 3
with respect to ground while the Error Amp output at Pin 2
is monitored with respect to the Voltage Feedback Input
threshold. The Multiplier is designed to have an extremely
linear transfer curve over a wide dynamic range, 0 V to
3.2 V for Pin 3, and 2.0 V to 3.75 V for Pin 2, Figure 1. The
Multiplier output controls the Current Sense Comparator
threshold as the ac voltage traverses sinusoidally from zero
to peak line, Figure 18. This has the effect of forcing the
MOSFET on−time to track the input line voltage, resulting
in a fixed Drive Output on−time, thus making the
preconverter load appear to be resistive to the ac line. An
approximation of the Current Sense Comparator threshold
can be calculated from the following equation. This
equation is accurate only under the given test condition
stated in the electrical table.
Overvoltage Comparator
An Overvoltage Comparator is incorporated to eliminate
the possibility of runaway output voltage. This condition
VCS, Pin 4 Threshold ≈ 0.65 (VPin 2 − Vth(M)) VPin 3
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MC34262, MC33262
Current Sense Comparator and RS Latch
A significant reduction in line current distortion can be
attained by forcing the preconverter to switch as the ac line
voltage crosses through zero. The forced switching is
achieved by adding a controlled amount of offset to the
Multiplier and Current Sense Comparator circuits. The
equation shown below accounts for the built−in offsets and
is accurate to within ten percent. Let Vth(M) = 1.991 V
The Current Sense Comparator RS Latch configuration
used ensures that only a single pulse appears at the Drive
Output during a given cycle. The inductor current is
converted to a voltage by inserting a ground−referenced
sense resistor R7 in series with the source of output switch
Q1. This voltage is monitored by the Current Sense Input
and compared to a level derived from the Multiplier output.
The peak inductor current under normal operating
conditions is controlled by the threshold voltage of Pin 4
where:
VCS, Pin 4 Threshold = 0.544 (VPin 2 − Vth(M)) VPin 3
+ 0.0417 (VPin 2 − Vth(M))
Zero Current Detector
The MC34262 operates as a critical conduction current
mode controller, whereby output switch conduction is
initiated by the Zero Current Detector and terminated when
the peak inductor current reaches the threshold level
established by the Multiplier output. The Zero Current
Detector initiates the next on−time by setting the RS Latch
at the instant the inductor current reaches zero. This critical
conduction mode of operation has two significant benefits.
First, since the MOSFET cannot turn−on until the inductor
current reaches zero, the output rectifier reverse recovery
time becomes less critical, allowing the use of an
inexpensive rectifier. Second, since there are no deadtime
gaps between cycles, the ac line current is continuous, thus
limiting the peak switch to twice the average input current.
The Zero Current Detector indirectly senses the inductor
current by monitoring when the auxiliary winding voltage
falls below 1.4 V. To prevent false tripping, 200 mV of
hysteresis is provided. Figure 9 shows that the thresholds
are well−defined over temperature. The Zero Current
Detector input is internally protected by two clamps. The
upper 6.7 V clamp prevents input overvoltage breakdown
while the lower 0.7 V clamp prevents substrate injection.
Current limit protection of the lower clamp transistor is
provided in the event that the input pin is accidentally
shorted to ground. The Zero Current Detector input to
Drive Output turn−on propagation delay is typically 320 ns.
IL(pk ) =
Pin 4 Threshold
R7
Abnormal operating conditions occur during
preconverter startup at extremely high line or if output
voltage sensing is lost. Under these conditions, the
Multiplier output and Current Sense threshold will be
internally clamped to 1.5 V. Therefore, the maximum peak
switch current is limited to:
Ipk(max) =
1.5 V
R7
An internal RC filter has been included to attenuate any
high frequency noise that may be present on the current
waveform. This filter helps reduce the ac line current
distortion especially near the zero crossings. With the
component values shown in Figure 20, the Current Sense
Comparator threshold, at the peak of the haversine varies
from 1.1 V at 90 Vac to 100 mV at 268 Vac. The Current
Sense Input to Drive Output turn−off propagation delay is
typically less than 200 ns.
Timer
A watchdog timer function was added to the IC to
eliminate the need for an external oscillator when used in
stand−alone applications. The Timer provides a means to
automatically start or restart the preconverter if the Drive
Output has been off for more than 620 ms after the inductor
current reaches zero. The restart time delay versus
temperature is shown in Figure 8.
Peak
Undervoltage Lockout and Quickstart
Inductor Current
An Undervoltage Lockout comparator has been
incorporated to guarantee that the IC is fully functional
before enabling the output stage. The positive power
supply terminal (VCC) is monitored by the UVLO
comparator with the upper threshold set at 13 V and the
lower threshold at 8.0 V. In the stand−by mode, with VCC
at 7.0 V, the required supply current is less than 0.4 mA.
This large hysteresis and low startup current allow the
implementation of efficient bootstrap startup techniques,
making these devices ideally suited for wide input range
off−line preconverter applications. An internal 36 V
clamp has been added from VCC to ground to protect the IC
and capacitor C4 from an overvoltage condition. This
feature is desirable if external circuitry is used to delay the
startup of the preconverter. The supply current, startup, and
operating voltage characteristics are shown in Figures 13
and 14.
Average
0
On
MOSFET
Q1
Off
Figure 19. Inductor Current and MOSFET
Gate Voltage Waveforms
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MC34262, MC33262
MOSFETs. The Drive Output is capable of up to ±500 mA
peak current with a typical rise and fall time of 50 ns with
a 1.0 nF load. Additional internal circuitry has been added
to keep the Drive Output in a sinking mode whenever the
Undervoltage Lockout is active. This characteristic
eliminates the need for an external gate pulldown resistor.
The totem−pole output has been optimized to minimize
cross−conduction current during high speed operation. The
addition of two 10 W resistors, one in series with the source
output transistor and one in series with the sink output
transistor, helps to reduce the cross−conduction current and
radiated noise by limiting the output rise and fall time. A
16 V clamp has been incorporated into the output stage to
limit the high state VOH. This prevents rupture of the
MOSFET gate when VCC exceeds 20 V.
A Quickstart circuit has been incorporated to optimize
converter startup. During initial startup, compensation
capacitor C1 will be discharged, holding the error amp
output below the Multiplier threshold. This will prevent
Drive Output switching and delay bootstrapping of
capacitor C4 by diode D6. If Pin 2 does not reach the
multiplier threshold before C4 discharges below the lower
UVLO threshold, the converter will “hiccup” and
experience a significant startup delay. The Quickstart
circuit is designed to precharge C1 to 1.7 V, Figure 7. This
level is slightly below the Pin 2 Multiplier threshold,
allowing immediate Drive Output switching and bootstrap
operation when C4 crosses the upper UVLO threshold.
Drive Output
The MC34262/MC33262 contain a single totem−pole
output stage specifically designed for direct drive of power
APPLICATIONS INFORMATION
0.998 at nominal line. Figures 20 and 21 are universal input
preconverter examples that operate over a continuous input
voltage range of 90 Vac to 268 Vac. Figure 20 provides an
output power of 175 W (400 V at 440 mA) while Figure 21
provides 450 W (400 V at 1.125 A). Both circuits have an
observed worst−case power factor of approximately 0.989.
The input current and voltage waveforms of Figure 20 are
shown in Figure 22 with operation at 115 Vac and 230 Vac.
The data for each of the applications was generated with the
test set−up shown in Figure 24.
The application circuits shown in Figures 19, 20 and 21
reveal that few external components are required for a
complete power factor preconverter. Each circuit is a peak
detecting current−mode boost converter that operates in
critical conduction mode with a fixed on−time and variable
off−time. A major benefit of critical conduction operation
is that the current loop is inherently stable, thus eliminating
the need for ramp compensation. The application in
Figure 19 operates over an input voltage range of 90 Vac to
138 Vac and provides an output power of 80 W (230 V at
350 mA) with an associated power factor of approximately
http://onsemi.com
9
MC34262, MC33262
Table 1. Design Equations
Calculation
Formula
Calculate the maximum required output power.
Notes
Required Converter Output Power
PO = VO IO
Calculated at the minimum required ac line voltage
for output regulation. Let the efficiency h = 0.92 for
low line operation.
Peak Inductor Current
Let the switching cycle t = 40 ms for universal input
(85 to 265 Vac) operation and 20 ms for fixed input
(92 to 138 Vac, or 184 to 276 Vac) operation.
Inductance
2
IL(pk) =
t
ǒ
LP =
2 PO
hVac(LL)
Ǔ
VO
h Vac(LL)2
− Vac(LL)
2
2 VO PO
In theory the on−time ton is constant. In practice ton
tends to increase at the ac line zero crossings due
to the charge on capacitor C5. Let Vac = Vac(LL) for initial
ton and toff calculations.
Switch On−Time
The off−time toff is greatest at the peak of the ac line
voltage and approaches zero at the ac line zero
crossings. Theta (q) represents the angle of the ac
line voltage.
Switch Off−Time
The minimum switching frequency occurs at the peak
of the ac line voltage. As the ac line voltage traverses
from peak to zero, toff approaches zero producing an
increase in switching frequency.
Switching Frequency
f=
Set the current sense threshold VCS to 1.0 V for
universal input (85 Vac to 265 Vac) operation and
to 0.5 V for fixed input (92 Vac to 138 Vac, or
184 Vac to 276 Vac) operation. Note that VCS must
be <1.4 V.
Peak Switch Current
R7 =
Set the multiplier input voltage VM to 3.0 V at high
line. Empirically adjust VM for the lowest distortion
over the ac line voltage range while guaranteeing
startup at minimum line.
Multiplier Input Voltage
The IIB R1 error term can be minimized with a divider
current in excess of 50 mA.
2 PO LP
ton =
h Vac2
ton
toff =
VO
2 Vac ⎪Sin q⎜
Converter Output Voltage
The calculated peak−to−peak ripple must be less than
16% of the average dc output voltage to prevent false
tripping of the Overvoltage Comparator. Refer to the
Overvoltage Comparator text. ESR is the equivalent
series resistance of C3.
Converter Output
Peak to Peak
Ripple Voltage
The bandwidth is typically set to 20 Hz. When operating
at high ac line, the value of C1 may need to be
increased. (See Figure 25)
Error Amplifier Bandwidth
The following converter characteristics must be chosen:
VO − Desired output voltage
Vac − AC RMS line voltage
IO − Desired output current
Vac (LL) − AC RMS low line voltage
DVO − Converter output peak−to−peak ripple voltage
http://onsemi.com
10
VM =
VO = Vref
ǒ
−1
1
ton + toff
ǒ
VCS
IL(pk)
Vac
R5
R3
R2
BW =
+1
+1
R1
DVO(pp) = IO
2
ǒ
Ǔ
Ǔ
− IIB R2
1
2pfac C3
gm
2 p C1
Ǔ
2
+ ESR2
MC34262, MC33262
1
D2
92 to RFI
138 Vac Filter
D1
C5
100k
R6
8
D4
Zero Current
Detector
D3
1.2V
+
5
6.7V
1.6V/
1.4V
MUR130
D5
Drive
Output
10
10
220
C3
230V/
0.35A
1.0M
R2
4
0.1
R7
10pF
Overvoltage
Comparator
+
MTP
8N50E
Q1
7
20k
1.5V
VO
+
RS
Latch
1.08 Vref
10mA
7.5k
R3
T
16V
Delay
0.01
C2
22k
R4
+ 13V/
8.0V
Timer R
Current Sense
Comparator
100
C4
UVLO
2.5V
Reference
2.2M
R5
+
36V
+
1N4934
D6
Multiplier
Error Amp
+
Vref
1
3
11k
R1
Quickstart
2
6
0.68
C1
Figure 20. 80 W Power Factor Controller
Power Factor Controller Test Data
AC Line Input
DC Output
Current Harmonic Distortion (% Ifund)
Vrms
Pin
PF
Ifund
THD
2
3
5
7
VO(pp)
VO
IO
PO
h(%)
90
85.9
0.999
0.93
2.6
0.08
1.6
0.84
0.95
4.0
230.7
0.350
80.8
94.0
100
85.3
0.999
0.85
2.3
0.13
1.0
1.2
0.73
4.0
230.7
0.350
80.8
94.7
110
85.1
0.998
0.77
2.2
0.10
0.58
1.5
0.59
4.0
230.7
0.350
80.8
94.9
120
84.7
0.998
0.71
3.0
0.09
0.73
1.9
0.58
4.1
230.7
0.350
80.8
95.3
130
84.4
0.997
0.65
3.9
0.12
1.7
2.2
0.61
4.1
230.7
0.350
80.8
95.7
138
84.1
0.996
0.62
4.6
0.16
2.4
2.3
0.60
4.1
230.7
0.350
80.8
96.0
This data was taken with the test set−up shown in Figure 24.
T = Coilcraft N2881−A
Primary: 62 turns of # 22 AWG
Secondary: 5 turns of # 22 AWG
Core: Coilcraft PT2510, EE 25
Gap: 0.072″ total for a primary inductance (LP) of 320 mH
Heatsink = AAVID Engineering Inc. 590302B03600, or 593002B03400
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11
MC34262, MC33262
C5
1
D2
90 to RFI
268 Vac Filter
D1
100k
R6
8
D4
Zero Current
Detector
D3
1.2V
+
+
36V
+
Drive
Output
10
7
400V/
330 0.44A
C3
1.6M
R2
4
0.1
R7
10pF
Overvoltage
Comparator
+
MTP
14N50E
Q1
10
20k
1.5V
VO
+
RS
Latch
1.08 Vref
10mA
12k
R3
MUR460
D5
16V
Delay
0.01
C2
T
+ 13V/
8.0V
Timer R
Current Sense
Comparator
22k
R4
UVLO
2.5V
Reference
1.3M
R5
100
C4
5
6.7V
1.6V/
1.4V
1N4934
D6
Multiplier
Error Amp
+
Vref
1
3
10k
R1
Quickstart
2
6
0.68
C1
Figure 21. 175 W Universal Input Power Factor Controller
Power Factor Controller Test Data
AC Line Input
DC Output
Current Harmonic Distortion (% Ifund)
Vrms
Pin
PF
Ifund
THD
2
3
5
7
VO(pp)
VO
IO
PO
h(%)
90
193.3
0.991
2.15
2.8
0.18
2.6
0.55
1.0
3.3
402.1
0.44
176.9
91.5
120
190.1
0.998
1.59
1.6
0.10
1.4
0.23
0.72
3.3
402.1
0.44
176.9
93.1
138
188.2
0.999
1.36
1.2
0.12
1.3
0.65
0.80
3.3
402.1
0.44
176.9
94.0
180
184.9
0.998
1.03
2.0
0.10
0.49
1.2
0.82
3.4
402.1
0.44
176.9
95.7
240
182.0
0.993
0.76
4.4
0.09
1.6
2.3
0.51
3.4
402.1
0.44
176.9
97.2
268
180.9
0.989
0.69
5.9
0.10
2.3
2.9
0.46
3.4
402.1
0.44
176.9
97.8
This data was taken with the test set−up shown in Figure 24.
T = Coilcraft N2880−A
Primary: 78 turns of # 16 AWG
Secondary: 6 turns of # 18 AWG
Core: Coilcraft PT4215, EE 42−15
Gap: 0.104″ total for a primary inductance (LP) of 870 mH
Heatsink = AAVID Engineering Inc. 590302B03600
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12
MC34262, MC33262
2
D2
90 to RFI
268 Vac Filter
D1
C5
100k
R6
8
D4
Zero Current
Detector
D3
1.2V
+
5
6.7V
1.6V/
1.4V
MUR460
D5
Drive
Output
10
+
4
10pF
Overvoltage
Comparator
MTW
20N50E
Q1
7
10
20k
1.5V
VO
+
RS
Latch
330
C3
400V/
1.125A
1.6M
R2
330
0.05
R7
0.001
1.08 Vref
10mA
12k
R3
T
16V
Delay
0.01
C2
22k
R4
+ 13V/
8.0V
Timer R
Current Sense
Comparator
100
C4
UVLO
2.5V
Reference
1.3M
R5
+
36V
+
1N4934
D6
Multiplier
Error Amp
+
Vref
3
1
10k
R1
Quickstart
2
6
0.68
C1
Figure 22. 450 W Universal Input Power Factor Controller
Power Factor Controller Test Data
DC Output
AC Line Input
Current Harmonic Distortion (% Ifund)
Vrms
Pin
PF
Ifund
THD
2
3
5
7
VO(pp)
VO
IO
PO
h(%)
90
489.5
0.990
5.53
2.2
0.10
1.5
0.25
0.83
8.8
395.5
1.14
450.9
92.1
120
475.1
0.998
3.94
2.5
0.12
0.29
0.62
0.52
8.8
395.5
1.14
450.9
94.9
138
470.6
0.998
3.38
2.1
0.06
0.70
1.1
0.41
8.8
395.5
1.14
450.9
95.8
180
463.4
0.998
2.57
4.1
0.21
2.0
1.6
0.71
8.9
395.5
1.14
450.9
97.3
240
460.1
0.996
1.91
4.8
0.14
4.3
2.2
0.63
8.9
395.5
1.14
450.9
98.0
268
459.1
0.995
1.72
5.8
0.10
5.0
2.5
0.61
8.9
395.5
1.14
450.9
98.2
This data was taken with the test set−up shown in Figure 24.
T = Coilcraft P3657−A
Primary: 38 turns Litz wire, 1300 strands of #48 AWG, Kerrigan−Lewis, Chicago, IL
Secondary: 3 turns of # 20 AWG
Core: Coilcraft PT4220, EE 42−20
Gap: 0.180″ total for a primary inductance (LP) of 190 mH
Heatsink = AAVID Engineering Inc. 604953B04000 Extrusion
http://onsemi.com
13
MC34262, MC33262
Current = 1.0 A/DIV
Current = 1.0 A/DIV
Voltage = 100 V/DIV
Input = 230 VAC, Output = 175 W
Voltage = 100 V/DIV
Input = 115 VAC, Output = 175 W
2.0 ms/DIV
2.0 ms/DIV
Figure 23. Power Factor Corrected Input Waveforms
(Figure 20 Circuit)
With Overvoltage Comparator
Without Overvoltage Comparator
500 V
8%
432 V
400 V
26%
80 V/DIV
80 V/DIV
400 V
0V
0V
200 ms/DIV
200 ms/DIV
Figure 24. Output Voltage Startup Overshoot
(Figure 20 Circuit)
Line
115 Vac
Input
Neutral
2X Step−Up
Isolation
Transformer
RFI Test Filter
HI
AC POWER ANALYZER
PM 1000
W
Autoformer
0
I
O
Vcf
7
VA
1
PF Vrms Arms
2
3
11
A
T
V
5
0.1
0.005
1.0
0.005
Acf Ainst FREQ HARM
9
HI
LO
13
LO
Voltech
Earth
Figure 25. Power Factor Test Set−Up
An RFI filter is required for best performance when connecting the preconverter directly to the ac line. The filter attenuates
the level of high frequency switching that appears on the ac line current waveform. Figures 19 and 20 work well with
commercially available two stage filters such as the Delta Electronics 03DPCG5. Shown above is a single stage test filter
that can easily be constructed with four ac line rated capacitors and a common−mode transformer. Coilcraft CMT3−28−2
was used to test Figures 19 and 20. It has a minimum inductance of 28 mH and a maximum current rating of 2.0 A. Coilcraft
CMT4−17−9 was used to test Figure 21. It has a minimum inductance of 17 mH and a maximum current rating of 9.0 A. Circuit
conversion efficiency h (%) was calculated without the power loss of the RFI filter.
http://onsemi.com
14
0 to 270 Vac
Output to Power
Factor
Controller Circuit
MC34262, MC33262
10mA
R2
Error Amp
+
1
R1
2
6
C1
Figure 26. Error Amp Compensation
The Error Amp output is a high impedance node and is susceptible to noise pickup. To minimize pickup, compensation
capacitor C1 must be connected as close to Pin 2 as possible with a short, heavy ground returning directly to Pin 6. When
operating at high ac line, the voltage at Pin 2 may approach the lower threshold of the Multiplier, ≈ 2.0 V. If there is
excessive ripple on Pin 2, the Multiplier will be driven into cut−off causing circuit instability, high distortion and poor power
factor. This problem can be eliminated by increasing the value of C1.
7
7
22k
10pF
4
22k
R
C
10pF
R7
4
D1
R7
Current
Sense
Comparator
Current
Sense
Comparator
Figure 27. Current Waveform Spike Suppression
Figure 28. Negative Current Waveform
Spike Suppression
A narrow turn−on spike is usually present on the leading edge of
the current waveform and can cause circuit instability. The
MC34262 provides an internal RC filter with a time constant of
220 ns. An additional external RC filter may be required in
universal input applications that are above 200 W. It is
suggested that the external filter be placed directly at the Current
Sense Input and have a time constant that approximates the
spike duration.
A negative turn−off spike can be observed on the trailing edge of
the current waveform. This spike is due to the parasitic
inductance of resistor R7, and if it is excessive, it can cause
circuit instability. The addition of Schottky diode D1 can
effectively clamp the negative spike. The addition of the external
RC filter shown in Figure 26 may provide sufficient spike
attenuation.
http://onsemi.com
15
MC34262, MC33262
(Top View)
3.0″
4.5″
(Bottom View)
NOTE:
Use 2 oz. copper laminate for optimum circuit performance.
Figure 29. Printed Circuit Board and Component Layout
(Circuits of Figures 20 and 21)
http://onsemi.com
16
MC34262, MC33262
DEVICE ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
SOIC−8
(Pb−Free)
98 Units / Rail
SOIC−8
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
98 Units / Rail
MC33262DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33262DR2
SOIC−8
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
Device
Operating Temperature Range
MC34262D
MC34262DG
MC34262DR2
TA = 0°C to +85°C
MC34262DR2G
MC34262P
MC34262PG
TA = 0°C to +85°C
MC33262D
MC33262DR2G
MC33262P
TA = −40°C to +105°C
MC33262PG
MC33262CDR2
MC33262CDR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
MC34262, MC33262
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
PLASTIC PACKAGE
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
http://onsemi.com
18
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
MC34262, MC33262
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
PLASTIC PACKAGE
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0 _
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (MC34262, MC33262), may be covered by the following U.S. patent: 5,073,850. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
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Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
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19
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