LINER LT3741EFE-TRPBF High power, constant current, constant voltage, step-down controller Datasheet

LT3741
High Power, Constant
Current, Constant Voltage,
Step-Down Controller
Features
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Description
Control Pin Provides Accurate Control of Regulated
Output Current
1.5% Voltage Regulation Accuracy
±6% Current Regulation Accuracy
6V to 36V Input Voltage Range
Wide Output Voltage Range Up to (VIN – 2V)
Average Current Mode Control
<1µA Shutdown Current
Up to 94% Efficiency
Additional Pin for Thermal Control of Load Current
Thermally Enhanced 4mm × 4mm QFN and 20-Pin
FE Package
Applications
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General Purpose Industrial
Super-Cap Charging
Applications Needing Extreme Short-Circuit
Protection and/or Accurate Output Current Limit
Constant Current or Constant Voltage Source
The LT®3741 is a fixed frequency synchronous step-down
DC/DC controller designed to accurately regulate the output
current at up to 20A. The average current-mode controller
will maintain inductor current regulation over a wide output
voltage range of 0V to (VIN – 2V). The regulated current is
set by an analog voltage on the CTRL pins and an external
sense resistor. Due to its unique topology, the LT3741 is
capable of sourcing and sinking current. The regulated
voltage and overvoltage protection are set with a voltage
divider from the output to the FB pin. Soft-Start is provided
to allow a gradual increase in the regulated current during
startup. The switching frequency is programmable from
200kHz to 1MHz through an external resistor on the RT
pin or through the use of the SYNC pin and an external
clock signal.
Additional Features include an accurate external reference
voltage for use with the CTRL pins, an accurate UVLO/EN
pin that allows for programmable UVLO hysteresis, and
thermal shutdown.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7199560, 7321203 and others pending.
Typical Application
10V/20A Constant Current, Constant Voltage Step-Down Converter
EN/UVLO
82.5k
RT
SYNC
VIN
1µF
LT3741
VREF
10nF
HG
100µF
10
CBOOT
2.2µH
VOUT
10V
20A
2.5mΩ
CTRL1
RHOT
45.3k
39.2k
10nF
22µF
150µF
s2
GND
CTRL2
RNTC
VCC_INT
LG
5.6nF
SS
12
220nF
SW
VC
VOUT vs IOUT
VIN
14V TO 36V
SENSE+
SENSE–
8
VOUT (V)
EN/UVLO
6
4
2 VIN = 18V
VOUT = 10V
ILIMIT = 20A
0
0 2 4 6
88.7k
FB
12.1k
8 10 12 14 16 18 20 22
IOUT (A)
3741 TA01b
3741 TA01a
3741f
LT3741
Absolute Maximum Ratings (Note 1)
VIN Voltage.................................................................40V
EN/UVLO Voltage.........................................................6V
VREF Voltage.................................................................3V
CTRL1 and CTRL2 Voltage...........................................3V
SENSE+ Voltage.........................................................40V
SENSE– Voltage.........................................................40V
VC Voltage...................................................................3V
SW Voltage................................................................40V
CBOOT.......................................................................46V
CBOOT – SW Voltage...................................................6V
RT Voltage...................................................................3V
FB Voltage....................................................................3V
SS Voltage...................................................................6V
VCC_INT Voltage............................................................6V
SYNC Voltage...............................................................6V
Storage Temperature Range.................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSSOP............................................................... 300°C
Pin Configuration
TOP VIEW
1
20 LG
20 19 18 17 16
GND
2
19 CBOOT
LG
VCC_INT
VIN
SW
CBOOT
VCC_INT
TOP VIEW
EN/UVLO 1
15 HG
VREF 2
14 GND
21
GND
CTRL2 3
GND 4
13 SYNC
12 RT
CTRL1 5
11 GND
VC
9 10
SENSE–
8
SENSE+
7
FB
SS
6
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
VIN
3
18 SW
EN/UVLO
4
17 HG
VREF
5
CTRL2
6
21
GND
16 GND
15 SYNC
GND
7
14 RT
CTRL1
8
13 VC
SS
9
12 SENSE–
FB 10
11 SENSE+
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3741EUF#PBF
LT3741EUF#TRPBF
3741
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LT3741IUF#PBF
LT3741IUF#TRPBF
3741
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LT3741EFE#PBF
LT3741EFE#TRPBF
LT3741FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3741IFE#PBF
LT3741IFE#TRPBF
LT3741FE
20-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3741f
LT3741
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
Input Voltage Range
VIN Pin Quiescent Current (Note 2)
Non-Switching Operation
Shutdown Mode
MIN
l
Not Switching
VEN/UVLO = 0V
6
l
EN/UVLO Pin Falling Threshold
1.49
EN/UVLO Hysteresis
EN/UVLO Pin Current
VIN = 6V, EN/UVLO = 1.45V
SYNC Pin Threshold
MAX
V
1.8
0.1
2.5
1
mA
µA
1.55
1.61
V
130
mV
5.5
µA
0
CTRL1 = 1.5V
UNITS
36
1.0
CTRL1 Pin Control Range
CTRL1 Pin Current
TYP
V
1.5
100
V
nA
Reference
Reference Voltage (VREF Pin)
l
1.94
2
2.06
l
48
51
54
V
Inductor Current Sensing
Full Range SENSE+ to SENSE–
VCTRL1 = 1.5V
SENSE+ Pin Current
SENSE– Pin Current
With VOUT ~ 4V, VCTRL1 = 0V
mV
50
nA
10
µA
Internal VCC Regulator (VCC_INT Pin)
Regulation Voltage
l
4.7
5
5.2
V
NMOS FET Driver
Non-Overlap time HG to LG
100
Non-Overlap time LG to HG
ns
60
ns
Minimum On-Time LG
(Note 3)
50
ns
Minimum On-Time HG
(Note 3)
80
ns
65
ns
2.3
1.3
Ω
Ω
2.3
1.0
Ω
Ω
Minimum Off-Time LG
(Note 3)
High Side Driver Switch On-Resistance
Gate Pull Up
Gate Pull Down
VCBOOT – VSW = 5V
Low Side Driver Switch On-Resistance
Gate Pull Up
Gate Pull Down
VCC_INT = 5V
Switching Frequency
fSW
RT = 40kΩ
RT = 200kΩ
l
900
190
1000
218
1070
233
kHz
kHz
Soft-Start
Charging Current
11
µA
850
nA
Voltage Regulation Amplifier
Input Bias Current
FB = 1.3V
800
gm
Feedback Regulation Voltage
CTRL1 = 1.5V, ISENSE– = 23µA
l
1.192
1.21
µA/V
1.228
V
3741f
LT3741
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
–3
0
3
UNITS
Current Control Loop gm Amp
Offset Voltage
Input Common Mode Range
VCM(LOW)
VCM(HIGH)
l
0
2
VCM(HIGH) Measured from VIN to VCM
Output Impedance
gm
Differential Gain
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3741E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
V
V
3.5
375
475
1.7
mV
MΩ
625
µA/V
mV/V
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3741I is guaranteed to meet performance specifications over the –40°C
to 125°C operating junction temperature range.
Note 3: The minimum on and off times are guaranteed by design and are
not tested.
3741f
LT3741
Typical Performance Characteristics
EN/UVLO Pin Current
0.5
1.64
8
0.4
6
0.3
1.58
–50°C
1.52
130°C
1.46
1.40
6
12
18
24
VIN (V)
30
4
2
0
36
IQ (µA)
10
EN/UVLO PIN CURRENT (µA)
EN/UVLO THRESHOLD (V)
EN/UVLO Threshold (Falling)
1.70
12
18
3741 G01
Quiescent Current (Non-Switching)
24
VIN (V)
30
25°C
0
36
0
8
16
3741 G02
VREF Pin Voltage
2.0
130°C
0.2
0.1
25°C
130°C
–50°C
6
IQ in Shutdown
24
VIN (V)
32
40
3741 G03
VREF Current Limit
1.6
2.06
2.04
1.2
0.8
0.4
0
12
18
24
VIN (V)
30
2.03
VIN = 6V
2.02
2.01
1.98
–50
36
–15
3741 G04
RT Pin Current Limit
TA = –50°C
55
20
TEMPERATURE (°C)
90
125
0.8
24
VIN (V)
30
36
3741 G06
5
12
VIN = 36V
4
VCC_INT (V)
11
ISS (µA)
18
6
13
60
12
VCC_INT Current Limit
Soft-Start Pin Current
70
6
3741 G05
14
80
ILIMIT (µA)
TA = 130°C
1.2
1.99
90
VIN = 6V
10
9
3
2
8
50
1
7
40
–50
TA = 25°C
1.0
2.00
TA = 25°C
TA = 130°C
TA = –50°C
6
1.4
VIN = 36V
ILIMIT (mA)
VREF VOLTAGE (V)
QUIESCENT CURRENT (mA)
2.05
1.6
–15
55
20
TEMPERATURE (°C)
90
125
3741 G08
6
–50
–15
55
20
TEMPERATURE (°C)
90
125
3741 G09
0
VIN = 12V
TA = 25°C
0
10
20
30
40
ILOAD (mA)
50
60
3741 G07
3741f
LT3741
Typical Performance Characteristics
CBOOT-SW UVLO Voltage
Internal UVLO
5.0
VCC_INT UVLO
3.00
4.00
2.75
3.75
2.50
3.50
4.0
UVLO (V)
VOLTAGE (V)
VIN (V)
4.5
2.25
3.25
2.00
3.00
1.75
2.75
3.5
3.0
–50
–15
55
20
TEMPERATURE (°C)
90
1.50
–50
125
–15
20
55
TEMPERATURE (°C)
50
0
–50
–100
–50°C
–150
10
20
30
40
ILOAD (mA)
50
60
1.15
1.20
1.25
VFB (V)
1.30
1.45
1.35
1.35
1.25
–50
Regulated Sense Voltage
50
VSENSE+ – VSENSE– (mV)
15
13
11
55
20
TEMPERATURE (°C)
90
125
40
30
20
3741 G16
0
100
125
3741 G15
MEASURED VIN – VOUT
2.0
VIN = 6V
1.5
VIN = 36V
1.0
0.5
10
–15
0
25
75
50
TEMPERATURE (°C)
Common Mode Lockout
2.5
60
17
–25
3741 G14
3741 G13
19
9
–50
1.55
130°C
–200
1.10
Overvoltage Timeout
1.65
CM LOCKOUT (V)
0
OVERVOLTAGE THRESHOLD (V)
CONTROL CURRENT (%)
VCC_INT (V)
25°C
4.4
OVERVOLTAGE TIMEOUT (µs)
1.75
100
4.8
125
90
Overvoltage Threshold
150
5.2
20
55
TEMPERATURE (°C)
3741 G12
Regulated Current vs VFB
VCC_INT Load Reg at 12V
6.0
5.6
–15
3741 G11
3741 G10
4.0
2.50
–50
125
90
0
0.5
1.0
VCTRL (V)
1.5
2.0
3741 G17
0
–50
–15
55
20
TEMPERATURE (°C)
90
125
3741 G18
3741f
LT3741
Typical Performance Characteristics
4
4
3
PULL-UP
2
LG Driver RDS(ON)
3
PULL-UP
2
PULL-DOWN
PULL-DOWN
1
1
0
–50
–15
55
20
TEMPERATURE (°C)
90
0
–50
125
Minimum Off-Time
300
MINIMUM OFF-TIME (ns)
5
RDS(ON) (Ω)
RDS(ON) (Ω)
HG Driver RDS(ON)
5
–15
55
20
TEMPERATURE (°C)
180
120
LG
90
0
–50
125
–15
3741 G21
55
20
TEMPERATURE (°C)
90
125
3741 G25
Minimum On-Time
150
HG
60
3741 G20
Non-Overlap Time
240
Oscillator Frequency
150
1.5
120
90
LG TO HG
60
30
1.2
90
HG
60
LG
30
0
–50
–15
55
20
TEMPERATURE (°C)
90
0
–50
125
0.6
–15
55
20
TEMPERATURE (°C)
90
0
–50
125
100
2
4
80
1
2
ACCURACY (%)
6
ACCURACY (%)
3
0
0
25°C
–1
0.75
1.5
CTRL_H (V)
2.25
3.0
3741 G28
–3
90
125
0
25°C
–2
–4
–2
0
55
20
TEMPERATURE (°C)
Current Regulation Accuracy
CTRL1 = 0.75V, VIN = 12V
120
20
–15
3741 G36
Current Regulation Accuracy
CTRL1 = 1.5V, VIN = 12V
40
220kHz
3741 G24
Overcurrent Threshold
60
900kHz
0.9
0.3
3741 G23
VSENSE+ – VSENSE– (mV)
FREQUENCY (MHz)
HG TO LG
MINIMUM ON-TIME (ns)
NON-OVERLAP TIME (ns)
1.2MHz
120
0
2.5
5.0
7.5
OUTPUT VOLTAGE (V)
10
3741 G26
–6
0
2.5
5.0
7.5
OUTPUT VOLTAGE (V)
10
3741 G27
3741f
LT3741
Typical Performance Characteristics
VOUT vs IOUT
VOUT vs IOUT
6
25
5
20
VOUT (V)
VOUT (V)
4
3
2
15
10
5 V = 25V
IN
VOUT = 20V
ILIMIT = 9.5A
0
0 1 2 3
1 VIN = 20V
VOUT = 5V
ILIMIT = 24A
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
IOUT (A)
3741 G19
5 6
IOUT (A)
7
8
9
10
3741 G22
Efficiency and Power Loss
vs Load Current
VOUT vs IOUT
100
10
95
8
90
20
85
15
EFFICIENCY (%)
12
6
4
30
25
EFFICIENCY
80
10
POWER LOSS (W)
VOUT (V)
4
POWER LOSS
2 VIN = 24V
VOUT = 10V
ILIMIT = 18A
0
0 2 4 6
75
8
70
10 12 14 16 18 20
IOUT (A)
VIN = 20V
VOUT = 5V
0
5
10
15
LOAD CURRENT (A)
20
3741 G33
0
3741 G29
Efficiency and Power Loss
vs Load Current
Efficiency and Power Loss
vs Load Current
100
4.8
100
12
95
EFFICIENCY
95
25
5
4.0
EFFICIENCY
90
10
85
2.4
80
75
70
1.6
POWER LOSS
2
4
6
LOAD CURRENT (A)
80
8
75
70
6
POWER LOSS
65
60
4
55
VIN = 25V
VOUT = 20V
0
EFFICIENCY (%)
3.2
POWER LOSS (W)
90
POWER LOSS (W)
EFFICIENCY (%)
85
8
10
3741 G30
0.8
50
VIN = 24V
VOUT = 10V
45
0
40
0
5
10
15
LOAD CURRENT (A)
20
2
0
3741 G37
3741f
LT3741
Typical Performance Characteristics
Voltage Regulation with 10A
Regulated Inductor Current
5A Load Step Recovery
VOUT
20mV/DIV
AC-COUPLED
VOUT
2V/DIV
IL
2A/DIV
IL
5A/DIV
COUT = 470µF
20ms/DIV
3741 G31
100µs/DIV
3741 G34
Shutdown and Recovery
1.5nF Soft-Start Capacitor
Common Mode Lockout
EN/UVLO
5V/DIV
VOUT
2V/DIV
IL
5A/DIV
IL
200mA/DIV
VOUT
2V/DIV
VIN = 7V
1ms/DIV
3741 G35
100µs/DIV
COUT = 1mF
VOUT = 5V
10A LOAD
18A CURRENT LIMIT
3741 G32
3741f
LT3741
Pin Functions
(QFN/TSSOP)
EN/UVLO (Pin 1/Pin 4): Enable Pin. The EN/UVLO pin
acts as an enable pin and turns on the internal current
bias core and subregulators at 1.55V. The pin does
not have any pull-up or pull-down, requiring a voltage
bias for normal part operation. Full shutdown occurs at
approximately 0.5V.
VREF (Pin 2/Pin 5): Buffered 2V reference capable of
0.5mA drive.
CTRL2 (Pin 3/Pin 6): Thermal control input used to reduce
the regulated current level.
GND (Pins 4,11,14, Exposed Pad Pin 21/Pins 2,7,16,
Exposed Pad Pin 21): Ground. The exposed pad must be
soldered to the PCB
CTRL1 (Pin 5/Pin 8): The CTRL1 pin sets the high level
regulated output current and overcurrent. The maximum
input voltage is internally clamped to 1.5V. The overcurrent
set point is equal to the high level regulated current level set
by the CTRL1 pin with an additional 23mV offset between
the SENSE+ and SENSE– pins.
SS (Pin 6/Pin 9): The Soft-Start Pin. Place an external
capacitor to ground to limit the regulated current during
start-up conditions. The soft-start pin has a 11µA charging current. This pin controls regulated output current
determined by CTRL1.
FB (Pin 7/Pin 10): Feedback Pin for Voltage Regulation
and Overvoltage Protection. The feedback voltage is 1.21V.
Overvoltage is also sensed through the FB pin. When the
feedback voltage exceeds 1.5V, the overvoltage lockout
prevents switching for 13μs to allow the inductor current
to discharge.
SENSE+ (Pin 8/Pin 11): SENSE+ is the inverting input of
the average current mode loop error amplifier. This pin is
connected to the external current sense resistor, RS. The
voltage drop between SENSE+ and SENSE– referenced to
the voltage drop across an internal resistor produces the
input voltages to the current regulation loop.
SENSE– (Pin 9/Pin 12): SENSE– is the non-inverting input
of the average current mode loop error amplifier. The reference current, based on CTRL1 or CTRL2 flows out of the
pin to the output side of the sense resistor, RS.
VC (Pin 10/Pin 13): VC provides the necessary compensation for the average current loop stability. Typical
compensation values are 20k to 50k for the resistor and
2nF to 5nF for the capacitor.
RT (Pin 12/Pin 14): A resistor to ground sets the switching
frequency between 200kHz and 1MHz. When using the
SYNC function, set the frequency to be 20% lower than
the SYNC pulse frequency. This pin is current limited to
60µA. Do not leave this pin open.
SYNC (Pin 13/Pin 15): Frequency Synchronization Pin.
This pin allows the switching frequency to be synchronized
to an external clock. The RT resistor should be chosen to
operate the internal clock at 20% slower than the SYNC
pulse frequency. This pin should be grounded when not
in use. When laying out board, avoid noise coupling to
or from SYNC trace.
HG (Pin 15/Pin 17): HG is the top-FET gate drive signal
that controls the state of the high-side external power FET.
The driver impedance is approximately 1.8Ω.
SW (Pin 16/Pin 18): The SW pin is used internally as the
lower-rail for the floating high-side driver. Externally, this
node connects the two power-FETs and the inductor.
CBOOT (Pin 17/Pin 19): The CBOOT pin provides a floating 5V regulated supply for the high-side FET driver. An
external Schottky diode is required from the VCC_INT pin
to the CBOOT pin to charge the CBOOT capacitor when
the switch-pin is near ground.
LG (Pin 18/Pin 20): LG is the bottom-FET gate drive signal
that controls the state of the low-side external power-FET.
The driver impedance is approximately 1.8Ω.
VCC_INT (Pin 19/Pin 1): A regulated 5V output for charging
the CBOOT capacitor. VCC_INT also provides the power for
the digital and switching subcircuits. Below 6V VIN, tie this
pin to the rail. VCC_INT is current limited to 50mA. Shutdown
operation disables the output voltage drive.
VIN (Pin 20/Pin 3): Input Supply Pin. Must be locally
bypassed with a 4.7μF low-ESR capacitor to ground.
3741f
10
LT3741
Block Diagram
(QFN Package)
VIN
VIN
402k
1
INTERNAL
REGULATOR
AND
UVLO
133k
100nF
SYNC
2
13
12
VREF
2V REFERENCE
SYNC
OSCILLATOR
RT
82.5k
–
R
+
S
Q
PWM
COMPARATOR
11µA
gm AMP
gm = 450µA/V
RO = 4M
IOUT = 40µA
+
CTRL1
CURRENT
MIRROR
+
+
LOW SIDE
DRIVER
3k
–
3
10
SENSE–
CTRL2
VC
47µF
19
VIN
10µF
0.1µF
2.4µH
8
RS
5mΩ
VOUT
150µF
s2
9
40.2k
7
10k
SS
90k
VOLTAGE
REGULATOR
AMP
gm = 850µA/V
+
100nF
6
SENSE+
FB
–
CTRL BUFFER
VCC_INT
1µF
HIGH SIDE
CBOOT
DRIVER
17
HG
15
SW
SYNCRONOUS
16
CONTROLLER
LG
18
–
1.5V
5
20
EN/UVLO
1.21V
40.2k
5.6µF
3741 F01
Figure 1. Block Diagram
3741f
11
LT3741
Operation
The LT3741 utilizes fixed-frequency, average current mode
control to accurately regulate the inductor current, independently from the output voltage. This is an ideal solution for applications requiring a regulated current source.
The control loop will regulate the current in the inductor
at an accuracy of ±6%. Once the output has reached the
regulation voltage determined by the resistor divider from
the output to the FB pin and ground, the inductor current
will be reduced by the voltage regulation loop. In voltage
regulation, the output voltage has an accuracy of ±1.5%.
For additional operation information, refer to the Block
Diagram in Figure 1.
The current control loop has two reference inputs, determined by the voltage at the analog control pins, CTRL1 and
CTRL2. The lower of the two analog voltages on CTRL1
and CTRL2 determines the regulated output current. The
analog voltage at the CTRL1 pin is buffered and produces
a reference voltage across an internal resistor. The internal
buffer has a 1.5V clamp on the output, limiting the analog
control range of the CTRL1 and CTRL2 pins from 0V to
1.5V – corresponding to a 0mV to 51mV range on the
sense resistor, RS. The average current-mode control
loop uses the internal reference voltage to regulate the
inductor current, as a voltage drop across the external
sense resistor, RS.
A 2V reference voltage is provided on the VREF pin to allow the use of a resistor voltage divider to the CTRL1 and
CTRL2 pins. The VREF pin can supply up to 500μA and is
current limited to 1mA.
The error amplifier for the average current-mode control
loop has a common mode lockout that regulates the inductor current so that the error amplifier is never operated out
of the common mode range. The common mode range is
from 0V to 2V below the VIN supply rail.
The overcurrent set point is equal to the regulated current
level set by the CTRL1 pin with an additional 23mV offset
between the SENSE+ and SENSE– pins. The overcurrent
is limited on a cycle-by-cycle basis; shutting switching
down once the overcurrent level is reached. Overcurrent
is not soft-started.
The regulated output voltage is set with a resistor divider
from the output back to the FB pin. The reference at the
FB pin is 1.21V. If the output voltage level is high enough
to engage the voltage loop, the regulated inductor current
will be reduced to support the load at the output. If the
voltage at the FB pin reaches 1.5V (~25% higher than the
regulation level), an internal overvoltage flag is set, shutting down switching for 13μs.
The EN/UVLO pin functions as a precision shutdown
pin. When the voltage at the EN/UVLO pin is lower than
1.55V, the internal reset flag is asserted and switching is
terminated. Full shutdown occurs at approximately 0.5V
with a quiescent current of less than 1μA in full shutdown.
The EN/UVLO pin has 130mV of built-in hysteresis. In
addition, a 5.5µA current source is connected to this pin
that allows any amount of hysteresis to be added with a
series resistor or resistor divider from VIN.
During startup, the SS pin is held low until the internal
reset goes low. Once reset goes low, the capacitor at the
soft-start pin is charged with an 11μA current source.
The internal buffers for the CTRL1 and CTRL2 signals are
limited by the voltage at the soft-start pin, slowly ramping
the regulated inductor current to the current determined
by the voltage at the CTRL1 or CTRL2 pins.
The thermal shutdown is set at 163°C with 8°C hysteresis.
During thermal shutdown, all switching is terminated and
the part is in reset (forcing the SS pin low).
The switching frequency is determined by a resistor at
the RT pin. The RT pin is also limited to 60µA, while not
recommended, this limits the switching frequency to 2MHz
when the RT pin is shorted to ground. The LT3741 may
also be synchronized to an external clock through the use
of the SYNC pin.
3741f
12
LT3741
Applications Information
Programming Inductor Current
Inductor Selection
The analog voltage at the CTRL1 pin is buffered and
produces a reference voltage, VCTRL, across an internal
resistor. The regulated average inductor current is determined by:
Size the inductor to have no less than 30% peak-to-peak
ripple. The overcurrent set point is equal to the high
level regulated current level set by the CTRL1 pin with
an additional 23mV offset between the SENSE+ and
SENSE– pins. The saturation current for the inductor
should be at least 20% higher than the maximum regulated current. The following equation sizes the inductor
for best performance:
IO =
VCTRL1
30 • RS
where RS is the external sense resistor and IO is the average inductor current, which is equal to the output current.
Figure 2 shows the maximum output current vs RS. The
maximum power dissipation in the resistor will be:
PRS
2
0.05V )
(
=
RS
Table 1 contains several resistors values, the corresponding
maximum current and power dissipation in the sense resistor. Susumu, Panasonic and Vishay offer accurate sense
resistors. Figure 3 shows the power dissipation in RS.
 V •V –V 2 
L =  IN O O 
 0.3 • fS • IO • VIN 
where VO is the output voltage, IO is the maximum regulated
current in the inductor and fS is the switching frequency.
Using this equation, the inductor will have approximately
15% ripple at maximum regulated current.
Table 2. Recommended Inductor Manufacturers
Table 1. Sense Resistor Values
MAXIMUM OUTPUT
CURRENT (A)
RESISTOR, RS (mΩ)
WEBSITE
Coilcraft
www.coilcraft.com
Sumida
www.sumida.com
Vishay
www.vishay.com
POWER DISSIPATION (W)
Würth Electronics
www.we-online.com
NEC-Tokin
www.nec-tokin.com
50
0.05
5
10
0.25
10
5
0.5
25
2
1.25
1.4
1.2
POWER DISSIPATION (W)
1
30
MAXIMUM OUTPUT CURRENT (A)
VENDOR
25
20
15
1.0
0.8
0.6
0.4
0.2
10
0
5
0
2
4
6
8 10 12
RS (mΩ)
14 16 18 20
3741 F03
0
0
2
4
6
8 10 12 14 16 18 20
RS (mΩ)
Figure 3. Power Dissipation in RS
3741 F02
Figure 2. RS Value Selection for Regulated Output Current
3741f
13
LT3741
Applications Information
Switching MOSFET Selection
When selecting switching MOSFETs, the following parameters are critical in determining the best devices for
a given application: total gate charge (QG), on-resistance
(RDS(ON)), gate to drain charge (QGD), gate-to-source
charge (QGS), gate resistance (RG), breakdown voltages
(maximum VGS and VDS) and drain current (maximum ID).
The following guidelines provide information to make the
selection process easier.
Both of the switching MOSFETs need to have their maximum
rated drain currents greater than the maximum inductor
current. The following equation calculates the peak inductor current:
 V •V –V 2
IMAX = IO +  IN O O 
 2 • fS • L • VIN 
where VIN is the input voltage, L is the inductance value,
VO is the output voltage, IO is the regulated output current
and fS is the switching frequency. During MOSFET selection, notice that the maximum drain current is temperature
dependant. Most data sheets include a table or graph of
the maximum rated drain current vs temperature.
The maximum VDS should be selected to be higher than
the maximum input supply voltage (including transient)
for both MOSFETs. The signals driving the gates of the
switching MOSFETs have a maximum voltage of 5V with
respect to the source. During start-up and recovery conditions, the gate drive signals may be as low as 3V. To
ensure that the LT3741 recovers properly, the maximum
threshold should be less than 2V. For a robust design,
select the maximum VGS greater than 7V.
Power losses in the switching MOSFETs are related to
the on-resistance, RDS(ON); the transitional loss related
to the gate resistance, RG; gate-to-drain capacitance, QGD
and gate-to-source capacitance, QGS. Power loss to the
on-resistance is an Ohmic loss, I2 RDS(ON), and usually
dominates for input voltages less than ~15V. Power losses
to the gate capacitance dominate for voltages greater than
~12V. When operating at higher input voltages, efficiency
can be optimized by selecting a high side MOSFET with
higher RDS(ON) and lower CGD. The power loss in the high
side MOSFET can be approximated by:
PLOSS = (ohmic loss) + (transition loss)
 (V +R I )

PLOSS ≈  F D O • IO2 RDS(ON) • ρT  +
VIN


  VIN • IOUT 

  5V  • (QGD + QGS ) • ( 2 • RG + RPU + RPD ) • fS 
(
)
where ρT is a temperature-dependant term of the MOSFET’s
on-resistance. Using 70°C as the maximum ambient operating temperature, ρT is roughly equal to 1.3. RPD and RPU
are the LT3741 high side gate driver output impedance,
1.3Ω and 2.3Ω respectively.
A good approach to MOSFET sizing is to select a high
side MOSFET, then select the low side MOSFET. The tradeoff between RDS(ON), QG, QGD and QGS for the high side
MOSFET is shown in the following example. VO is equal
to 4V. Comparing two N-channel MOSFETs, with a rated
VDS of 40V and in the same package, but with 8× different
RDS(ON) and 4.5× different QG and QGD:
M1: RDS(ON) = 2.3mΩ, QG = 45.5nF,
QGS = 13.8nF, QGD = 14.4nF , RG = 1Ω
M2: RDS(ON) = 18mΩ, QG = 10nF,
QGS = 4.5nF, QGD = 3.1nF , RG = 3.5Ω
Power loss for both MOSFETs is shown in Figure 4. Observe
that while the RDS(ON) of M1 is eight times lower, the power
loss at low input voltages is equal, but four times higher
at high input voltages than the power loss for M2.
Another power loss related to switching MOSFET selection
is the power lost to driving the gates. The total gate charge,
QG, must be charged and discharged each switching cycle.
The power is lost to the internal LDO within the LT3741.
The power lost to the charging of the gates is:
PLOSS_LDO ≈ (VIN – 5V) • (QGLG + QGHG) • fS
where QGLG is the low side gate charge and QGHG is the
high side gate charge.
Whenever possible, utilize a switching MOSFET that
minimizes the total gate charge to limit the internal power
dissipation of the LT3741.
3741f
14
LT3741
Applications Information
2.5
7
MOSFET POWER LOSS (W)
MOSFET POWER LOSS (W)
6
5
TOTAL
4
TRANSITIONAL
3
2
1
0
2.0
1.5
TOTAL
1.0
TRANSITIONAL
0.5
OHMIC
OHMIC
0
10
20
30
0
40
0
20
10
30
40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3741 F04a
3741 F04b
Figure 4a. Power Loss Example for M1
Figure 4b. Power Loss Example for M2
Figure 4
Table 3. Recommended Switching FETs
VIN VOUT IOUT
(V) (V) (A)
TOP FET
8
4
24
4
24
2-4
20
RJK0365DPA
12
2-4
10
FDMS8680
36
4
20
Si7884BDP
24
4
40
PSMN4R030YL
BOTTOM FET MANUFACTURER
5-10 RJK0365DPA RJK0330DPB Renesas
5 RJK0368DPA RJK0332DPB www.renesas.com
RJK0346DPA
FDMS8672AS Fairchild
www.fairchildsemi.com
SiR470DP
Vishay
www.vishay.com
RJK0346DPA NXP/Philips
www.nxp.com
Input Capacitor Selection
The input capacitor should be sized at 4µF for every 1A
of output current and placed very close to the high side
MOSFET. A small 1µF ceramic capacitor should be placed
near the VIN and ground pins of the LT3741 for optimal
noise immunity. The input capacitor should have a ripple
current rating equal to half of the maximum output current.
It is recommended that several low ESR ceramic capacitors
be used as the input capacitance. Use only type X5R or
X7R capacitors as they maintain their capacitance over a
wide range of operating voltages and temperatures.
Output Capacitor Selection
The output capacitors need to have very low ESR (equivalent
series resistance) to reduce output ripple. A minimum of
20µF/A of load current should be used in most designs.
The capacitors also need to be surge rated to the maximum
output current. To achieve the lowest possible ESR, several
low ESR capacitors should be used in parallel. Many applications benefit from the use of high density POSCAP
capacitors, which are easily destroyed when exposed to
overvoltage conditions. To prevent this, select POSCAP
capacitors that have a voltage rating that is at least 50%
higher than the regulated voltage
CBOOT Capacitor Selection
The CBOOT capacitor must be sized less than 220nF and
more than 50nF to ensure proper operation of the LT3741.
Use 220nF for high current switching MOSFETs with high
gate charge.
VCC_INT Capacitor Selection
The bypass capacitor for the VCC_INT pin should be larger
than 5µF for stability and has no ESR requirement. It
is recommended that the ESR be lower than 50mΩ to
reduce noise within the LT3741. For driving MOSFETs
with gate charges larger than 10nC, use 0.5µF/nC of total
gate charge.
Soft-Start
Unlike conventional voltage regulators, the LT3741 utilizes
the soft-start function to control the regulated inductor current. The charging current is 11µA and reduces the regulated
current when the SS pin voltage is lower than CTRL1.
3741f
15
LT3741
Applications Information
Output Current Regulation
VREF
To adjust the regulated load current, an analog voltage is
applied to the CTRL1 pin. Figure 5 shows the regulated
voltage across the sense resistor for control voltages up
to 2V. Figure 6 shows the CTRL1 voltage created by a voltage divider from VREF to ground. When sizing the resistor
divider, please be aware that the VREF pin is current limited
to 500µA. Above 1.5V, the control voltage has no effect on
the regulated inductor current.
LT3741
CTRL1
R1
3741 F06
Figure 6. Analog Control of Inductor Current
VOUT
60
LT3741
R2
FB
50
VSENSE+ – VSENSE– (mV)
R2
R1
40
3741 F07
Figure 7. Output Voltage Regulation and Overvoltage Protection
Feedback Connections
30
20
10
0
0
0.5
1.0
VCTRL (V)
1.5
2.0
3741 F05
Figure 5. Sense Voltage vs CTRL Voltage
not leave this pin open under any condition. The RT pin
is also current limited to 60µA. See Table 4 and Figure 8
for resistor values and the corresponding switching
frequencies.
Table 4. Switching Frequency
SWITCHING FREQUENCY (MHz)
RT (kΩ)
Voltage Regulation and Overvoltage Protection
 R2 
VOUT = 1.21V  1+ 
 R1
Programming Switching Frequency
The LT3741 has an operational switching frequency range
between 200kHz and 1MHz. This frequency is programmed
with an external resistor from the RT pin to ground. Do
40.2
53.6
0.5
82.5
0.3
143
0.2
221
0.1
453
1.2
1.0
FREQUENCY (MHz)
The LT3741 uses the FB pin to regulate the output voltage
and to provide a high speed overvoltage lockout to avoid
high voltage conditions. The regulated output voltage
is programmed using a resistor divider from the output
and ground (Figure 7). When the output voltage exceeds
125% of the regulated voltage level (1.5V at the FB pin),
the internal overvoltage flag is set, terminating switching.
The regulated output voltage must be greater than 1.5V
and is set by the equation:
1
0.750
0.8
0.6
0.4
0.2
0
0
50 100 150 200 250 300 350 400 450 500
RT (kΩ)
3743 F08
Figure 8. Frequency vs RT Resistance
3741f
16
LT3741
Applications Information
Thermal Shutdown
VIN
The internal thermal shutdown within the LT3741 engages
at 163°C and terminates switching and resets soft-start.
When the part has cooled to 155°C, the internal reset is
cleared and soft-start is allowed to charge.
VIN
LT3741
R2
EN/UVLO
R1
3741 F09
Switching Frequency Synchronization
The nominal switching frequency of the LT3741 is determined by the resistor from the RT pin to ground and may
be set from 200kHz to 1MHz. The internal oscillator may
also be synchronized to an external clock through the SYNC
pin. The external clock applied to the SYNC pin must have
a logic low below 0.3V and a logic high higher than 1.25V.
The input frequency must be 20% higher than the frequency
determined by the resistor at the RT pin. The duty cycle of
the input signal needs to be greater than 10% and less than
90%. Input signals outside of these specified parameters
will cause erratic switching behavior and subharmonic
oscillations. When synchronizing to an external clock,
please be aware that there will be a fixed delay from the input
clock edge to the edge of switch. The SYNC pin must be
grounded if the synchronization to an external clock is not
required. When SYNC is grounded, the switching frequency
is determined by the resistor at the RT pin.
Shutdown and UVLO
The LT3741 has an internal UVLO that terminates switching,
resets all synchronous logic, and discharges the soft-start
capacitor for input voltages below 4.2V. The LT3741 also
has a precision shutdown at 1.55V on the EN/UVLO pin.
Partial shutdown occurs at 1.55V and full shutdown is
guaranteed below 0.5V with <1µA IQ in the full shutdown
state. Below 1.55V, an internal current source provides
5.5µA of pull-down current to allow for programmable
UVLO hysteresis. The following equations determine the
voltage divider resistors for programming the UVLO voltage and hysteresis as configured in Figure 9.
R2 =
VHYST
5.5µA
Figure 9. UVLO Configuration
The EN/UVLO pin has an absolute maximum voltage of
6V. To accommodate the largest range of applications,
there is an internal Zener diode that clamps this pin. For
applications where the supply range is greater than 4:1,
size R2 greater than 375k.
Load Current Derating Using the CTRL2 Pin
The LT3741 is designed specifically for driving high power
loads. In high current applications, derating the maximum
current based on operating temperature prevents damage
to the load. In addition, many applications have thermal
limitations that will require the regulated current to be reduced based on load and/or board temperature. To achieve
this, the LT3741 uses the CTRL2 pin to reduce the effective
regulated current in the load. While CTRL1 programs the
regulated current in the load, CTRL2 can be configured to
reduce this regulated current based on the analog voltage
at the CTRL2 pin. The load/board temperature derating is
programmed using a resistor divider with a temperature
dependant resistance (Figure 10). When the board/load
temperature rises, the CTRL2 voltage will decrease. To
reduce the regulated current, the CTRL2 voltage must be
lower than voltage at the CTRL1 pin.
RV
RV
VREF
R2
LT3741
RNTC
RNTC
RX
RNTC
RNTC
RX
CTRL2
R1
(OPTION A TO D)
3741 F10
A
B
C
D
Figure 10. Load Current Derating vs Temperature
Using NTC Resistor
 1.55V • R2 
R1= 
 VUVLO – 1.55V 
3741f
17
LT3741
Applications Information
Average Current Mode Control Compensation
The use of average current mode control allows for precise
regulation of the inductor and load currents. Figure 11
shows the average current mode control loop used in the
LT3741, where the regulation current is programmed by
a current source and a 3k resistor.
MODULATOR
VCTRL • 11µA/V
3k
L
RS
gm
ERROR AMP
fS • L • 1000 V
0.002
[Ω], CC =
[F ]
VO • RS
fS
Board Layout Considerations
–
RC
RC =
where fS is the switching frequency, L is the inductance
value, VO is the output voltage and RS is the sense resistor.
For most applications, a 4.7nF compensation capacitor
is adequate and provides excellent phase margin with
optimized bandwidth. Please refer to Table 6 for recommended compensation values.
LOAD
+
the error amplifier will be the compensation resistor, RC.
Use the following equation as a good starting point for
compensation component sizing:
3741 F11
CC
Figure 11. LT3741 Average Current Mode Control Scheme
To design the compensation network, the maximum compensation resistor needs to be calculated. In current mode
controllers, the ratio of the sensed inductor current ramp
to the slope compensation ramp determines the stability
of the current regulation loop above 50% duty cycle. In
the same way, average current mode controllers require
the slope of the error voltage to not exceed the PWM ramp
slope during the switch off-time.
Average current mode control is relatively immune to the
switching noise associated with other types of control
schemes. Placing the sense resistor as close as possible
to the SENSE+ and SENSE– pins avoids noise issues. Due
to sense resistor ESL (equivalent series inductance), a
10Ω resistor in series with the SENSE+ and SENSE– pins
with a 33nF capacitor placed between the SENSE pins is
recommended. Utilizing a good ground plane underneath
the switching components will minimize interplane noise
coupling. To dissipate the heat from the switching components, use a large area for the switching mode while
keeping in mind that this negatively affects the radiated
noise.
Since the closed-loop gain at the switching frequency
produces the error signal slope, the output impedance of
Table 6. Recommended Compensation Values
VIN (V)
VO (V)
IL (A)
fSW (MHz)
L (µH)
RS (mΩ)
RC (kΩ)
CC (nF)
12
4
5
0.5
1.5
5
47.5
4.7
12
4
10
0.5
1.5
5
47.5
4.7
12
5
20
0.25
1.8
2.5
38.3
8.2
24
4
2
0.5
1.0
2.5
52.3
4.7
24
4
20
0.5
1.0
2.5
52.3
4.7
3741f
18
LT3741
Typical Applications
20A Super Capacitor Charger with 5V Regulated Output
EN/UVLO
EN/UVLO
VIN
1µF
RT
SYNC
82.5k
HG
100nF
CBOOT
VREF
2.2µF
RHOT
45.3k
50k
100µF
M1
L1
1.0µH
SW
LT3741
VCC_INT
CTRL1
LG
CTRL2
SENSE+
SS
SENSE–
FB
22µF
10nF
VC
10Ω
VOUT
20A MAXIMUM
150µF
s2
10Ω
M2
33nF
38.3k
12.1k
47.5k
4.7nF
L1: IHLP4040DZER1R0M01
M1: RJK0365DPA
M2: RJK0346DPA
R1: VISHAY WSL25122L500FEA
Efficiency and Power Loss
vs Load Current
3741 TA02
VOUT vs IOUT
6
25
5
90
20
4
85
15
EFFICIENCY
80
10
POWER LOSS (W)
30
VOUT (V)
100
EFFICIENCY (%)
R1
2.5mΩ
GND
RNTC
470k
95
VIN
10V TO 36V
3
2
POWER LOSS
75
70
VIN = 20V
VOUT = 5V
0
5
10
15
LOAD CURRENT (A)
20
25
3741 TA02b
5
0
1 VIN = 20V
VOUT = 5V
ILIMIT = 20A
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
IOUT (A)
3741 TA02c
3741f
19
LT3741
Typical Applications
20A LED Driver
EN/UVLO
VIN
EN/UVLO
1µF
RT
SYNC
82.5k
HG
100µF
M1
150nF
L1
1.1µH
CBOOT
VREF
2.2µF
RHOT CONTROL
INPUT
45.3k
SW
LT3741
VCC_INT
LG
CTRL1
CTRL2
SENSE
10nF
VOUT
6V, 20A MAXIMUM
680µF
22µF
M2
10Ω
10Ω
+
SENSE–
SS
2.5mΩ
D1
GND
RNTC
470k
VIN
12V TO 36V
33nF
47.5k
FB
VCH
12.1k
82.5k
3741 TA03
4.7nF
LED Current Waveforms 10A to
20A Current Step
CTRL1
1V/DIV
1.5V
0.75V
20A
ILED
5A/DIV
10A
1ms/DIV
3741 TA03b
3741f
20
LT3741
Typical Applications
10A Single-Cell Lithium-Ion Battery Charger
VIN
EN/UVLO
1µF
µCONTROLLER
CTRL1
HG
RT
SYNC
82.5k
220nF
CBOOT
LT3741
2.2µH
SW
1%
5mΩ
VIN
24V
VOUT
4.2V, 10A MAXIMUM
+
3.6V
VCC_INT
VREF
2.2µF
LG
RHOT
45.3k
22µF
10Ω
GND
CTRL2
SENSE+
SS
SENSE–
FB
RNTC
470k
1nF
33µF
VC
20nF
10Ω
30.1k
12.1k
82.5k
3741 TA04
8.2nF
3741f
21
LT3741
Package Description
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.00 REF
2.45 ± 0.05
2.45 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
0.75 ± 0.05
R = 0.05
TYP
R = 0.115
TYP
19 20
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
4.00 ± 0.10
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
1
2.00 REF
2.45 ± 0.10
2
2.45 ± 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3741f
22
LT3741
Package Description
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3741f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3741
Typical Application
20V Regulated Output with 5A Current Limit
EN/UVLO
VIN
EN/UVLO
1µF
82.5k
RT
SYNC
HG
100nF
CBOOT
VREF
2.2µF
RHOT
45.3k
RNTC
470k
22µF
M1
L1
8.2µH
SW
LT3741
VCC_INT
CTRL1
LG
CTRL2
SENSE+
SS
SENSE–
FB
VIN
36V
R1
10mΩ
VOUT
5A MAXIMUM
100µF
22µF
10Ω
10Ω
M2
GND
10nF
VC
10nF
187k
12.1k
30.1k
3741 TA05
3.9nF
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LT3743
Synchronous Step-Down LED Driver
92% Efficiency, IOUT to 20A, VIN: 5.5V to 36V, IQ = 2mA, ISD < 1µA, 4mm x 5mm
QFN-28, TSSOP-28E
3741f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LT 0310 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2010
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