LINER LTC1406I Low power, 8-bit, 20msps, sampling a/d converter Datasheet

LTC1406
Low Power, 8-Bit, 20Msps,
Sampling A/D Converter
DESCRIPTION
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FEATURES
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Low Power, 8-Bit, 20Msps ADC
250MHz Internal Sample-and-Hold
7 Effective Bits at 70MHz Input Frequency
±1LSB DNL and INL Max
Single 5V Supply and 150mW Dissipation
Power Down to 1µA
True Differential Inputs Reject Common Mode Noise
Accepts Single-Ended or Differential Input Signals
±1V Differential or 2V Single-Ended Input Span
Analog Inputs Common Mode to VDD and GND
24-Pin Narrow SSOP Package
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APPLICATIONS
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The LTC ®1406 is a 20Msps, 8-bit, sampling A/D converter
which draws only 150mW from a single 5V supply. This
easy-to-use device includes a high dynamic range sampleand-hold with a 250MHz bandwidth.
The LTC1406’s full-scale input range is ±1V. The inputs
can be driven differentially or one input can be tied to a
fixed voltage and the other input driven with a ±1V bipolar
input. Maximum DC specifications include ±1LSB DNL
and INL over temperature. Outstanding AC performance
includes 48.5dB S/(N + D) and 62dB THD with a 1MHz
input; 47.5dB S/(N + D) and 59dB THD at the Nyquist input
frequency of 10MHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 250MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
Telecommunications
Wireless Communications
Digital Cellular Telephones
CCDs and Image Scanners
Video Digitizing and Digital Television
Digital Color Copiers
High Speed Undersampling
Personal Computer Video
High Speed Data Acquisition
The ADC has an 8-bit parallel output port with separate
power supply and ground allowing easy interface to 3V
digital systems. The pipelined architecture has five clock
cycles of data latency.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Effective Bits and Signal-to-Noise + Distortion
vs Input Frequency
Low Power, 20MHz, 8-Bit Sampling ADC
DVDD
12
24
OVDD
11
2
CLOCK
CIRCUITRY
23
22
AIN–
7
8
DIGITAL
DATA
8-BIT
PIPELINE
ADC
TRACK-ANDHOLD AMP
20
OUTPUT
DRIVERS
19
18
17
16
2.2V
2.5k
15
1.95k
9
4
10
3
5
6
1
AVDD
VBIAS
AGND
SHDN
VREF
AGND
OGND
D7
D6
D5
D4
D3
8
50
7
44
6
38
5
32
4
3
D2
2
D1
1
S/(N + D) (dB)
21
AIN+
OF/UF
EFFECTIVE BITS
CLK
DGND
D0
0
100k
1406 BD
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 TA02
1
LTC1406
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
AVDD = OVDD = DVDD = VDD (Notes 1, 2)
ORDER PART
NUMBER
TOP VIEW
Supply Voltage (VDD) ................................................. 6V
Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) .................. – 0.3V to 10V
Digital Output Voltage ................. – 0.3V to (VDD + 0.3V)
Power Dissipation.............................................. 500mW
Ambient Operation Temperature Range
LTC1406C................................................ 0°C to 70°C
LTC1406I............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
OGND
1
24 CLK
OVDD
2
23 OF/UF
SHDN
3
22 D7
VBIAS
4
21 D6
VREF
5
20 D5
AGND
6
19 D4
AIN+
AIN–
7
18 D3
8
17 D2
AVDD
9
16 D1
AGND 10
15 D0
DGND 11
14 NC
DVDD 12
13 NC
LTC1406CGN
LTC1406IGN
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 85°C/ W
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
(Notes 5, 6)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
Integral Linearity Error
MIN
●
(Note 7)
Differential Linearity Error
Offset Error
(Note 8)
Gain Error
With External 2.5V Reference
TYP
MAX
8
UNITS
Bits
●
±0.5
±1
LSB
●
±0.25
±1
LSB
●
±1
±8
LSB
±1
±5
LSB
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A ALOG I PUT
(Note 5)
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
Analog Input Span [(AIN+) – (AIN–)] (Note 9)
Input (AIN+ or AIN–) Range
4.75V ≤ VDD ≤ 5.25V
●
Voltage On Either AIN+ or AIN–
●
IIN
Analog Input Leakage Current
CLK = 0
●
CIN
Analog Input Capacitance
CLK = 1
CLK = 0
VIN
Input Bandwidth
TYP
MAX
UNITS
VDD
V
±5
µA
±1
0
4
2
250
V
pF
pF
MHz
tAP
Sample-and-Hold Aperture Delay Time
3
ns
tjitter
Sample-and-Hold Aperture Delay Time Jitter
5
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
– 2.5V < (AIN– = AIN+) < 2.5V
60
dB
VBIAS
Internal Bias Voltage
No Load
2.2
V
2
LTC1406
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DY A IC ACCURACY
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
1MHz Input Signal
10MHz Input Signal
48.5
47.5
dB
dB
THD
Total Harmonic Distortion
1MHz Input Signal, First 5 Harmonics
10MHz Input Signal, First 5 Harmonics
– 62
– 59
dB
dB
SFDR
Spurious Free Dynamic Range
1MHz Input Signal
10MHz Input Signal
63
60
dB
dB
IMD
Intermodulation Distortion
fIN1 = 3.500977MHz, fIN2 = 3.598633MHz
60
dB
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DIGITAL I PUTS AND OUTPUTS
(Note 5)
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VDD = 4.75V, IO = – 10µA
VDD = 4.75V, IO = – 200µA
●
VDD = 4.75V, IO = 160µA
VDD = 4.75V, IO = 1.6mA
●
TYP
MAX
2.4
UNITS
V
0.8
V
±5
µA
5
pF
4.5
V
V
4.0
0.05
0.10
0.4
V
V
ISOURCE
Output Source Current
VOUT = 0V
– 20
mA
ISINK
Output Sink Current
VOUT = VDD
30
mA
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POWER REQUIRE E TS
(Note 5)
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AVDD
Analog Positive Supply Voltage
(Note 10)
4.75
5.25
V
DVDD
Digital Positive Supply Voltage
(Note 10)
4.75
5.25
V
OVDD
Output Positive Supply Voltage
(Note 10)
2.7
5.25
V
VBIAS
Internal Bias Voltage
When Externally Driven (Note 10)
1.9
2.2
2.5
V
VREF
Reference Voltage
(Note 10)
2
2.5
3
V
OGND
Output Ground
(Note 10)
0
2
V
IDD
Positive Supply Current
AVDD = DVDD = OVDD = 5V, fSMPL = 20MHz (Note 13)
PD
Power Dissipation
●
30
45
mA
●
150
225
mW
Power Down Positive Supply Current
SHDN = 0V, CLK = VDD or 0
1
10
µA
Power Down Power Dissipation
SHDN = 0V, CLK = VDD or 0
5
50
µW
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LTC1406
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
fSMPL(MAX)
Maximum Sampling Frequency
●
20
MHz
t1
Clock Period
(Notes 11, 12)
●
50
ns
t2
Pulse Width High
(Notes 11, 12)
●
25
ns
t3
Pulse Width Low
(Notes 11, 12)
●
25
t4
Output Delay
CL = 15pF
UNITS
t5
Pipeline Delay
5
t6
Aperture Delay
3
ns
Aperture Jitter
5
psRMS
ns
15
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle input currents up to
100mA below ground without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSMPL = 20MHz and tr = tf = 2ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– tied to VREF = 2.5V.
MAX
25
ns
Cycles
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0111 1111 and 1000 0000.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CLK edge starts a conversion.
Note 12: At the maximum conversion rate, deviation from a 50% duty
cycle results in interstage settling times < 25ns and performance may
be affected.
Note 13: VIN = – Full Scale.
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TYPICAL PERFORMANCE CHARACTERISTICS
Signal-to-Noise Ratio vs
Input Frequency
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G01
4
52
48
44
40
36
32
28
24
20
16
12
8
4
0
100k
Distortion vs Input Frequency
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
52
48
44
40
36
32
28
24
20
16
12
8
4
0
100k
SIGNAL-TO-NOISE RATIO (dB)
S/(N + D) (dB)
S/(N + D) vs Input Frequency
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G02
0
–10
–20
–30
–40
–50
THD
–60
–70
3RD HARMONIC
2ND HARMONIC
–80
100k
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G03
LTC1406
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TYPICAL PERFORMANCE CHARACTERISTICS
Spurious-Free Dynamic Range
vs Input Frequency
70
1.0
0
fSAMPLE = 20MHz
fIN1 = 3.500977MHz
fIN2 = 3.598633MHz
–10
60
40
30
20
DNL EOC ERROR (LSB)
–20
50
AMPLITUDE (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
Differential Nonlinearity
vs Output Code
Intermodulation Distortion Plot
–30
–40
–50
–60
–70
–80
10
0.5
0
–0.5
–90
0
100k
1M
10M
INPUT FREQUENCY (Hz)
–100
100M
0
1
2
3 4 5 6 7
FREQUENCY (MHz)
8
9
–1.0
10
0
32
64
96 128 160 192 224 256
OUTPUT CODE
1406 G04
1406 G05
Input Common Mode Rejection
vs Input Frequency
Integral Nonlinearity
vs Output Code
0.5
0
–0.5
0
32
64
96 128 160 192 224 256
OUTPUT CODE
Supply Current vs
Sampling Frequency
70
35
60
30
SUPPLY CURRENT (mA)
COMMON MODE REJECTION (dB)
INL EOC ERROR (LSB)
1.0
–1.0
1406 G06
50
40
30
20
10
0
100k
25
20
15
10
5
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G08
0
100k
1M
10M 20M
SAMPLING FREQUENCY (Hz)
1406 G09
1406 G07
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PIN FUNCTIONS
OGND (Pin 1): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OVDD (Pin 2): Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
SHDN (Pin 3): Power Shutdown Input. Logic low selects
shutdown.
VBIAS (Pin 4): Internal Bias Voltage. Internally set to 2.2V.
Bypass to analog ground plane with 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
VREF (Pin 5): External 2.5V Reference Input. Bypass to
analog ground plane with 10µF tantalum in parallel with
0.1µF or 10µF ceramic.
AGND (Pin 6): Analog Ground. Tie to analog ground plane.
A IN+ (Pin 7): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN+) – (AIN–)] = – 1V.
A IN– (Pin 8): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN+) – (AIN–)] = – 1V. For singleended operation, tie AIN– to a DC voltage (e.g., VREF).
5
LTC1406
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PIN FUNCTIONS
AVDD (Pin 9): Analog 5V Positive Supply. Bypass to analog ground plane with 10µF tantalum in parallel with 0.1µF
or 10µF ceramic.
AGND (Pin 10): Analog Ground. Tie to analog ground plane.
DGND (Pin 11): Digital Ground for Internal Logic. Tie to
analog ground plane.
DVDD (Pin 12): Digital 5V Positive Supply. Bypass to DGND
with 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
NC (Pins 13, 14): No Internal Connection.
D7 to D0 (Pins 15 to 22): Digital Data Outputs. The outputs swing between OVDD and OGND.
OF/UF (Pin 23): Overflow/Underflow Bit. OF/UF high with
D7 to D0 all high indicates an overrange, OF/UF high with
D7 to D0 all low indicates an underrange condition. OF/UF
low indicates a conversion within the normal input range.
The outputs swing between OVDD and OGND.
CLK (Pin 24): Clock Input. Internal sample-and-hold tracks
the input signal when CLK is high and samples the input
signal on the falling edge.
AVDD = DVDD = VDD
NOMINAL (V)
MIN
TYP
2.7
3 or 5
ABSOLUTE MAXIMUM (V)
PIN
NAME
DESCRIPTION
MAX
MIN
MAX
1
OGND
Ground for Output Drivers
2
OVDD
Supply for Output Drivers
– 0.3
VDD + 0.3
5.25
– 0.3
6
3
SHDN
Shutdown Input, Active Low
VDD
– 0.3
10
4
VBIAS
Internal Bias Voltage
5
VREF
External Reference Input
6
AGND
Analog Ground, Clean Ground
7
Positive Analog Input, ±1V Span
0
8
AIN+
AIN–
Negative Analog Input
0
9
AVDD
Analog Supply
10
AGND
Analog Ground, Substrate Ground
0
– 0.3
VDD + 0.3
11
DGND
Digital Ground
0
– 0.3
VDD + 0.3
12
DVDD
Digital Supply
5.25
– 0.3
6
13 to 14
NC
No Connect, No Internal Connection
15 to 22
D7 to D0
Data Outputs
OGND
OVDD
– 0.3
VDD + 0.3
23
OF/UF
Overflow/Underflow Output
OGND
OVDD
– 0.3
VDD + 0.3
24
CLK
Clock Input
0
VDD
– 0.3
10
0
0
1.9
2.2
2.5
– 0.3
VDD + 0.3
2
2.5
3
– 0.3
VDD + 0.3
– 0.3
VDD + 0.3
VDD
– 0.3
VDD + 0.3
VDD
– 0.3
VDD + 0.3
5.25
– 0.3
6
0
4.75
4.75
5
5
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TI I G DIAGRA
t6
N
ANALOG
SIGNAL
N+1
N+2
N–1
N+6
N+3
N+4
t3
N+5
t1
CLOCK
t2
DATA OUT
N–6
N–5
N–4
t4
N–3
t5
6
N–2
N–1
N
1406 TD
LTC1406
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FUNCTIONAL BLOCK DIAGRA
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DVDD
12
CLK
24
DGND
OVDD
11
2
CLOCK
CIRCUITRY
23
22
21
AIN+
AIN–
7
8-BIT
PIPELINE
ADC
TRACK-ANDHOLD AMP
8
DIGITAL
DATA
20
OUTPUT
DRIVERS
19
18
17
16
2.2V
2.5k
15
1.95k
9
4
10
3
5
6
1
AVDD
VBIAS
AGND
SHDN
VREF
AGND
OGND
OF/UF
D7
D6
D5
D4
D3
D2
D1
D0
1406 BD
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APPLICATIONS INFORMATION
Conversion Details
The LTC1406 uses an internal sample-and-hold circuit and
a pipeline quantizing architecture to convert an analog
signal to an 8-bit parallel output. With CLK high the input
switches are closed and the analog input will be acquired
on the input sampling capacitors CS (see Figure 1).
On the falling edge of CLK the input switches open, capturing the input signal. The sampling capacitors are then
shorted together and the charge is transferred to the hold
AIN+
CLK
Dynamic Performance
CH
The LTC1406 has excellent wideband sampling capability.
The sample-and-hold amplifier has a small-signal input
bandwidth of 250MHz allowing the ADC to undersample
input signals with frequencies well beyond the converter’s
Nyquist frequency. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies outside the fundamental. Figure
2 shows a typical LTC1406 FFT plot.
+
CLK
AIN–
CLK
CS
CLK
capacitors CH resulting in a differential DC voltage on the
output of the track-and-hold amplifier that is proportional
to the input signal. This differential voltage is fed into a
comparator that determines the most significant bit and
subtracts the result. The residue is then amplified by two
and passed to the next stage via a similar sample-and-hold
circuit. This continues down the eight pipeline stages. The
comparator outputs are then combined in a digital error
correction circuit. The 8-bit word is available at the output,
five clock cycles after the sampling edge.
CS CLK
TO NEXT STAGE
–
CH
1406 F01
CLK
Figure 1. Input Sample-and-Hold Amplifier
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LTC1406
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APPLICATIONS INFORMATION
0
–20
–30
–40
–50
50
–70
7
44
–80
6
38
5
32
–90
–100
0
1
2
3
4 5 6 7
FREQUENCY (Hz)
8
9
10
1406 F02a
Figure 2a. Nonaveraged, 4096 Point FFT
Input Frequency = 1MHz
3
2
1
0
100k
0
AMPLITUDE (dB)
4
fSAMPLE = 20MHz
–10 f = 28.99902MHz
IN1
–20 SFDR = 54.9dB
SINAD = 47.0dB
–30
S/(N + D) (dB)
8
–60
EFFECTIVE BITS
AMPLITUDE (dB)
where ENOB is the effective number of bits and S/(N + D)
is expressed in dB. At the maximum sampling rate of 20MHz
the LTC1406 maintains near ideal ENOBs up to and beyond the Nyquist input frequency of 10MHz (see Figure 3).
fSAMPLE = 20MHz
fIN1 = 1.000977MHz
SFDR = 64.8dB
SINAD = 48.6dB
–10
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 TA02
Figure 3. Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
–40
–50
Total Harmonic Distortion
–60
–70
–80
–90
–100
0
1
2
3
4 5 6 7
FREQUENCY (Hz)
8
9
10
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
1406 F02b
Figure 2b. Nonaveraged, 4096 Point FFT
Input Frequency = 30MHz
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling frequency. The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related
to the S/(N + D) by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
8
THD = 20 log
V22 + V32 + V42 + . . .Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is
shown in Figure 4. The LTC1406 has good distortion performance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different frequency (see Figure 5).
LTC1406
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AMPLITUDE (dB BELOW THE FUNDAMENTAL)
APPLICATIONS INFORMATION
0
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
–10
–20
–30
–40
–50
THD
–60
–70
3RD HARMONIC
2ND HARMONIC
–80
100k
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G03
(
)
IMD fa ± fb = 20 log
(
)
Amplitude at fa ± fb
Amplitude at f a
Figure 4. Distortion vs Input Frequency
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibel relative to the RMS value of
a full-scale input signal (see Figure 6).
0
fSAMPLE = 20MHz
fIN1 = 3.500977MHz
fIN2 = 3.598633MHz
–10
AMPLITUDE (dB)
–20
–30
–40
Input Bandwidth
–50
–60
–70
–80
–90
–100
0
1
2
3 4 5 6 7
FREQUENCY (MHz)
8
9
10
1406 G05
Figure 5. Intermodulation Distortion Plot
Analog Inputs
SPURIOUS-FREE DYNAMIC RANGE (dB)
70
60
50
40
30
20
10
0
100k
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full-scale input signal. The LTC1406 has been
designed for wide input bandwidth (250MHz), allowing
the ADC to undersample input signals with frequencies
above the converter’s Nyquist frequency. The noise floor
stays very low at high frequencies; S/(N + D) becomes
dominated by distortion at frequencies far beyond Nyquist.
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G04
Figure 6. Spurious-Free Dynamic Range vs
Input Frequency
The LTC1406 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The AIN+ and AIN–
inputs are sampled at the same time and the ADC will
always convert the difference of [(AIN+) – (AIN–)] independent of the common mode voltage. Any unwanted signal
that is common to both inputs will be rejected by the common mode rejection of the sample-and-hold circuit. The
common mode rejection holds up to extremely high frequencies (see Figure 7).
The inputs can be driven differentially or single-ended. In
differential mode, both inputs are driven ±0.5V out of
phase with each other. In single-ended mode, the negative input is tied to a fixed voltage and AIN+ is used as the
9
LTC1406
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APPLICATIONS INFORMATION
COMMON MODE REJECTION (dB)
70
ANALOG INPUT
1.5V TO 3.5V
60
AIN+
LTC1406
LTC1406
AIN–
50
AIN–
40
2.5V
30
VREF
2.5V
VREF
1406 F08a
1406 F08b
20
Figure 8a. DC Coupled
10
0
100k
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G08
Figure 7. Common Mode Rejection
vs Input Frequency
single input providing a ±1V bipolar input range centered
around AIN–. Likewise, AIN+ can be tied to a fixed voltage
and AIN– used as the single input. In any configuration the
maximum output code (1111 1111) occurs when [(AIN+)
– (AIN–)] = 1V and the minimum output code (0000 0000)
occurs when [(AIN+) – (AIN–)] = – 1V.
Each analog input can swing from ground to VDD but not
beyond. Therefore, the input common mode voltage can
range from 0.5V to 4.5V in differential mode and from 1V
to 4V in single-ended mode.
As an example, with AIN– connected to the VREF pin (2.5V)
the input range will be 1.5V to 3.5V (see Figure 8a). To
achieve other ranges the input may be capacitively coupled
to achieve a 2V span with virtually any common mode
voltage (see Figure 8b).
The 2V input span requires a 2.5V external reference be
connected to the VREF pin. The LT1460-2.5 micropower
precision series reference is recommended. To achieve
other input spans, the reference voltage (VREF) can vary
between 2V to 3V. The VREF pin can also be driven with a
DAC or other means. This is useful in applications where
the peak input signal amplitude may vary. The input span
of the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio.
The analog inputs of the LTC1406 are easy to drive. The
inputs draw only one small current spike while charging
the sample-and-hold capacitors following a rising CLK edge.
10
ANALOG INPUT
2V SPAN
AIN+
Figure 8b. AC Coupled
While CLK is low the analog inputs draw only a small leakage current. If the source impedance of the driving circuit
is low, then the LTC1406 inputs can be driven directly. As
source impedance increases, so will acquisition time. For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 25ns for full throughput rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (< 50Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 50Ω. The
second requirement is that the closed-loop bandwidth must
be greater than 70MHz to ensure adequate small-signal
settling for full throughput rate.
The following list is a summary of the op amps that are
suitable for driving the LTC1406. More detailed information is available in the Linear Technology Databooks and
on the LinearViewTM CD-ROM.
LT®1223: 100MHz Video Current Feedback Amplifier. 6mA
supply current. ±5V to ±15V supplies. Low noise.
LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current. ±5V to ±15V supplies. Low distortion.
Low noise.
LinearView is a trademark of Linear Technology Corporation.
LTC1406
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APPLICATIONS INFORMATION
LT1259/LT1260: Dual and Triple 130MHz Current Feedback Amplifiers. ±2V to ±14V supplies. 5mA supply current. Low distortion. Low noise.
LT1363: 70MHz Voltage Feedback Amplifier. ±2.5V to
±15V supplies. 7.5mA supply current. Low distortion.
LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback
Amplifiers. ±2.5V to ±15V supplies. 7.5mA supply current
per amplifier. Low distortion.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1406 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 250MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 9 shows a 220pF
capacitor from AIN+ to AIN– and a 75Ω source resistor to
limit the input bandwidth to 9.6MHz. The 220pF capacitor
also acts as a charge reservoir for the input sample-andhold and isolates the ADC input from sampling glitch sensitive circuitry. Larger value capacitors may be substituted
to further limit the input bandwidth. High quality capacitors and resistors should be used since these components
can add distortion. NPO and silver mica type dielectric
capacitors have excellent linearity. Carbon surface mount
ANALOG INPUT
1.5V TO 3.5V
75Ω
220pF
AIN+
LTC1406
Figure 10 shows the ideal input/output characteristics for
the LTC1406. The code transitions occur midway between
successive integer LSB values (i.e., – FS + 0.5LSB, – FS +
1.5LSB, – FS + 2.5LSB...FS – 1.5LSB, FS – 0.5LSB). The
output is straight binary with 1LSB = FS – (– FS)/256 = 2V/
256 = 7.8125mV. The OF/UF bit indicates that the input has
exceeded full scale and can be used to detect an overrange
or underrange condition. A logic high output on the OF/UF
pin with an output code of 0000 0000 indicates the input
is less than the negative full scale. A logic high output on
the OF/UF pin with an output code of 1111 1111 indicates
that the input is greater than the positive full scale. A logic
low output on the OF/UF pin indicates the input is within
the full-scale range of the converter.
In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Zero offset
is achieved by adjusting the offset applied to the AIN– input.
For zero offset error, apply a voltage equal to the input
OF/UF BIT
1111 1111
1111 1110
1111 1101
1000 0001
1000 0000
0111 1111
0111 1110
0000 0010
0000 0000
VREF
–FS
1406 F09
Figure 9. RC Input Filter
Input/Output Characteristics
0000 0001
AIN–
2.5V
resistors can also generate distortion from self-heating
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible to
both problems.
OUTPUT CODE
LT1229/LT1230: Dual and Quad 100MHz Current Feedback Amplifiers. ±2V to ±15V supplies. Low noise. 6mA
supply current each amplifier.
–1 0 1
LSB
LSB
INPUT VOLTAGE (V)
FS – 1LSB
1406 F10
Figure 10. Transfer Characteristics
11
LTC1406
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Digital Inputs and Outputs
The LTC1406 is designed to easily interface with either 3V
or 5V logic. The digital input pins, SHDN and CLK, have
thresholds of nominally 1.9V and will accept a 3V or 5V
logic input. The data output pins, including OF/UF, are
connected to a separate supply and ground (OVDD and
OGND respectively). OVDD is normally connected to DVDD
but can be connected to an external supply as low as 2.7V.
OGND is normally connected to DGND but can be connected to an external ground or an external voltage source
as high as 2V.
Clock
The LTC1406 requires a 50% duty cycle clock. The duty
cycle should be timed from the nominal threshold of the
CLK input which is 1.9V. At conversion speeds below the
maximum conversion rate of 20MHz, the duty cycle can
deviate from 50% with no degradation in performance as
long as each clock phase is at least 25ns long. At the
maximum conversion rate, deviation from a 50% duty cycle
clock results in interstage settling times of < 25ns and
performance may be affected.
With the CLK pin high, the ADC will track the difference of
the two analog inputs. On the falling edge of CLK the input
is sampled and the conversion begins. At the end of five
clock cycles (on the fifth falling CLK edge following the
start of conversion) the data from the conversion will be
available at the digital outputs until the next falling CLK
edge. Each falling edge of CLK starts a new conversion so
successive conversion results are available on successive
falling CLK edges.
12
While the falling edge starts the conversion, both rising
and falling edges are used internally during the conversion. It is therefore important to provide a clock signal that
has low jitter and fast rise and fall times (< 2ns). Much of
the internal circuitry operates dynamically limiting the minimum conversion rate to 10kHz. To ensure proper operation after power is first applied, or the clock stops for more
than 100µs, typically 20 clock cycles must be performed
at a sample rate above 10kHz before the output data will
be valid.
10
9
fSAMPLE = 20MHz
8
7
DNL (LSBs)
common mode voltage minus 3.90625mV (i.e., – 0.5LSB)
and adjust the offset at the AIN– input until the output code
flickers between 0111 1111 and 1000 0000. For full-scale
adjustment, an input voltage equal to the input common
mode voltage plus 988.28125mV (i.e., FS – 1.5LSBs) is
applied to AIN+ and the VREF input is adjusted until the
output code flickers between 1111 1110 and 1111 1111.
6
5
4
3
2
1
0
28 32 36 40 44 48 52 56 60 64 68 72
DUTY CYCLE (%)
1406 F11
Figure 11. Typical DNL vs Duty Cycle
Power Shutdown
The quiescent power of the LTC1406 can be further
reduced between conversions by taking the SHDN pin low.
This powers down all of the internal amplifiers and bias
circuitry and the part draws only a small quiescent current
of 1µA from the 5V supply. There is a nominally 4k internal
resistor between VREF and AGND that will continue to draw
current during shutdown as long as VREF is driven. It should
also be noted that the data output drivers are not threestate devices and do not go into a high impedance state
during shutdown. If the data output pins will remain connected to a load during shutdown, current may be drawn
through the OVDD supply pin. This can be prevented by
including a FET switch in series with OVDD or OGND controlled by SHDN. If the data bus will remain active during
LTC1406
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APPLICATIONS INFORMATION
shutdown. It may also be desirable to isolate the data output pins from the bus to reduce the load capacitance. To
resume normal operation the SHDN pin must be brought
high and typically 20 clock cycles must be performed at a
sample rate above 10kHz before the output data will be
valid.
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1406, a printed circuit board with
ground plane is required. Layout for the printed circuit
board should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 1 (OGND), Pin 6 (AGND), Pin 10 (AGND) and Pin 11
(DGND) and all other analog grounds should be connected
to this single analog ground point. The VCM, VREF, DVDD
and OVDD bypass capacitors should also be connected to
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. In some applications it may be desirable to connect the OVDD to the logic
system supply and OGND to the logic system ground. In
these cases OVDD should be bypassed to OGND instead of
the analog ground plane.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from
the microprocessor to the comparators. The problem can
be eliminated by forcing the microprocessor into a wait
state during conversion or by using three-state buffers to
isolate the ADC data bus.
The LTC1406 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN– leads will
be rejected by the input CMRR. The LTC1406 will hold and
convert the difference voltage between AIN+ and AIN–. The
leads to AIN+ (Pin 7) and AIN– (Pin 8) should be kept as
short as possible. In applications where this is not possible, the AIN+ and AIN– traces should be run side by side
to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD, VCM and VREF pins
as shown in the Typical Application on the first page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively, 10µF tantalum
capacitors in parallel with 0.1µF ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figures 12a, 12b, 12c and 12d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a 2-layer printed circuit board.
13
JP8
(OPT)
J3
AIN–
C12
0.1µF
J6
(OPT)
R10, 1k
JP10
R7
1k
(OPT)
R9
1k
J5
(OPT)
J2
AIN+
E5
EXT REF
E4
SHDN
JP11
C13
0.1µF
JP9
R5
1k
(OPT)
3
2
3
2
4
+
–
4
7
5V
+
–
7
5V
JP5
JP4
C6
(OPT)
U6
DIP8
(OPT)
6
C15
0.1µF
U5
SO8
(OPT)
6
C10
0.1µF
JP7
R4
50Ω
4
2.5V REF
2
OUT
IN
GND
R8
50Ω
R6
C8
1k
100pF
(OPT)
6
C11
10µF
10V
C5
0.1µF
JP2
+
C14
10µF, 10V
10µF, 10V
C16
C7
10µF
10V
12
11
10
DVDD
DGND
AGND
AVDD
AIN–
8
9
AIN+
AGND
VREF
VBIAS
SHDN
OVDD
C2
10µF
10V
CLK
CLK
4
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
OF/UF
U3
LTC1406
OGND
7
6
5
4
3
2
1
C4
22µF, 10V
R1
10Ω
R2
10Ω
JP1
Figure 12a. Suggested Evaluation Circuit Schematic
NOTE: ALL RESISTORS ARE IN OHMS, 1/8W, 5%, 0805
JP6
JP3
U1
LT1460-2.5 (MS8)
+
JP12
E2
OUTPUT
SUPPLY
3
5
C17
0.1µF
13
14
15
16
17
18
19
20
21
22
23
24
R3
50Ω
2
U7
TC7SH04F
VCC
10
9
8
7
6
5
4
3
2
1
2
3
R18
R17
R16
R15
R14
R13
R12
R11
7
R19
51Ω
J4
(OPT)
11
12
13
14
15
16
17
18
1406 F12a
CK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
19
20
5
4
1
C3, 0.1µF
VCC
U4, 74HC574
(OPT)
GND
D7
D6
D5
D4
D3
D2
D1
D0
OE
U2
74HC74
(OPT)
E3
OUTPUT GND
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OGND
CLK
OGND
OGND
CLK
D0
D1
D2
D3
D4
D5
D6
D7
OF/UF
C9
0.1µF
VCC
J1
CLOCK
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C1
22µF
10V
5V
E6
ANALOG
GROUND
APPLICATIONS INFORMATION
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ANALOG
SUPPLY
LTC1406
LTC1406
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Figure 12b. Suggested Evaluation Circuit
Board—Component Side Silkscreen
Figure 12d. Suggested Evaluation Circuit
Board—Solder Side Layout
Figure 12c. Suggested Evaluation Circuit
Board—Component Side Layout
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
24-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.337 – 0.344*
(8.560 – 8.738)
24 23 22 21 20 19 18 17 16 15 14 13
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
2 3
4
5 6
7
8
9 10 11 12
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.025
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN24 (SSOP) 1197
15
LTC1406
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TYPICAL APPLICATION
Low Power, 20MHz, 8-Bit Sampling ADC
LTC1406
5V
1
2
3
10µF
4
2.5V
REFERENCE
5
10µF
6
7
ANALOG
INPUTS
8
9
10µF
10
11
12
OGND
CLK
OVDD
OF/UF
SHDN
D7
VBIAS
D6
VREF
D5
AGND
D4
AIN+
D3
AIN –
D2
AVDD
D1
AGND
D0
DGND
NC
DVDD
NC
24
23
CLOCK INPUT
OVERFLOW/UNDERFLOW OUTPUT
22
21
20
19
8-BIT
PARALLEL
BUS
18
17
16
15
14
13
NC
NC
1406 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC1196/LTC1198
Single Supply, 8-Bit, 1Msps/750ksps ADCs
Single 3V or 5V Supply, Low Power, Serial Interface, SO-8 Package
LTC1197/LTC1199
Single Supply, 10-Bit, 500ksps/450ksps ADCs
Single 3V or 5V Supply, Low Power, Serial Interface, SO-8 Package
LTC1410
12-Bit, 1.25Msps Sampling ADC with Shutdown
Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist
LTC1415
Single 5V, 12-Bit, 1.25Msps ADC
Single Supply 55mW Dissipation
LTC1419
14-Bit, 800ksps Sampling ADC with Shutdown
81.5dB SINAD, 150mW from ±5V Supplies
LTC1604
16-Bit, 333ksps ADC
90dB SINAD, 100dB THD, 250mW Dissipation
LTC1605
Single 5V, 16-Bit, 100ksps ADC
Low Power, ±10V Inputs
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit Rail-to-Rail Output DAC in SO-8 Package
VCC = 2.7V to 5.5V, Output Swings from GND to REF, REF Input Can Be
Tied to VCC
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs
LTC1458: VCC = 4.5V to 5.5V, VOUT 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
DACs
16
Linear Technology Corporation
1406f LT/TP 0299 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1998
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