AZ Displays AGM3224I-1 Specifications for liquid crystal display Datasheet

AZ DISPLAYS, INC.
COMPLETE LCD SOLUTIONS
SPECIFICATIONS FOR
LIQUID CRYSTAL DISPLAY
PART NUMBER:
REVISED:
AGM3224I-1 Series
MARCH 13, 2007
LCD Module
Main Data
Contents
Unit
(1) Module size
167.0(W) x 109.0(H) x 8.5 (D)
mm
(2) Viewing area
120.0 (W) x 90.0 (H)
mm
x 3 (R.G.B) (W) x 240 (H)
dots
No.
Item
(3) Dot Number
320
(4) Dot Size
0.10(W) x 0.34(H)
mm
(5) Dot pitch
0.12(W) x 0.36(H)
mm
(6) LCD type
•Color-STN (Negative & transmissive type)
• with Anti glare upper polarizer .
(7) Contrast ratio
-
40
-
1/242
-
(9) Viewing direction
6 O‘clock
-
(10) Operating temperature
0
~ +50
°C
-20
~ +60
°C
(8) Duty
(11) Storage temperature
(12) Backlight
(13) Power Supply Voltage
LED x 16
VDD=5.0 V
or 3.3 V
VLCD=22.5 V
(14) Weight
200 (Approx.)
pcs
V
g
Page 1
Interface Pin Connection
CN1
FFC Pitch 1.0mm, width 17.0mm.
Pin No.
Signal
Pin Function
1
FLM
First Line Marker
2
CL1
Input data latch signal ( LOAD )
3
CL2
Data shift clock ( CP )
4
DISP OFF
5
VDD
Power supply for Logic
6
VSS
GND
7
VLCD
8
D0
Display data
9
D1
Display data
10
D2
Display data
11
D3
Display data
12
D4
Display data
13
D5
Display data
14
D6
Display data
15
D7
Display data
16
VSS
Display control signal H:ON
L:OFF
Power supply for LCD
GND
CN2M63-M83-04 (MITSUMI)
Pin No.
Signal
Function
1
LED(+)
2
-
-----------------------
3
-
-----------------------
4
LED(-)
Power supply voltage for LED
LED GND
Page 2
Block Diagram
Timing
Circuit
CL1
CL2
DISP
D0~D7
Driving Circuit
Circuit
Y1
Y960
Column
Row Driving
FLM
VDD
Power
VSS
Supply
VLCD
CN2
X1
COLOR
LCD
PANEL
320×RGB×240 DOTS
X240
Circuit
LED
VLED(+)
VLED(-)
Page 3
Maximum Ratings
Absolute Maximum Ratings. (LCM)
(VSS=0V)
Item
Symbol
Min.
Max.
Unit
Power supply for Logic
VDD-VSS
-0.3
7.0
V
Contrast Adjustment Voltage
VLCD-VSS
0
45
V
Input voltage (Note 1)
Vi
-0.3
VDD+0.3
V
Note 1. FLM,CL1,CL2,DISP,D0~D7.
Note 2. Ta=25°C
Note 3. Make certain you are grounded when handling LCM.
Electrical
Environmental Absolute Maximum Ratings
Operating
Item
MIN.
MAX.
Ambient Temperature
0°C
50°C
Humidity
Note 4
Vibration
-
2.45m/s
Shock
-
29.4m/s
Storage
MIN.
MAX.
-20°C
60°C
Note 4
11.76 m/s
Note 5
490 m/s
Note 5
Remark
Note1,2,3
No Condensation
1h max Note 6
XYZ directions 11ms
Note 1. Ta at -20°C --------<48hours, at 60°C --------<120 hours.
Note 2. Background color changes slightly depending on ambient temperature.
The phenomenon is reversible.
Note 3. Ta<=40°C : 85%RH MAX.
Ta> 40°C : Absolute humidity must be lower than the humidity of 85% RH at 40°C.
Note 4. The module should be operated normally after the test is finished.
Note 5. 5Hz ~ 100Hz (Except resonance frequency).
Page 4
Electrical Characteristics
Electrical Characteristics of LCD
Item
Symbol
Power Supply for Logic
VDD
Input Signal Voltage
VIH
Note (1)
VIL
Power supply current Logic
IDD
Power supply current Lcd
IEE
Recommended LCD
Driving Voltage
Frame Freguency
VLCD -VSS
fFLM
Condition
MIN.
VDD-VSS
3.15
“H” Level
0.8VDD
“L” Level
0
VDD=5.0V
VDD=3.3V
VLCD=22.5V, Note (2)
Ta=0°C
Duty=1/242
Bias=1/15 Ta=25°C
Ta=50°C
Typ.
5.0
2.2
1.0
6.5
Max. Unit
5.5
V
VDD
V
0.2VDD
5.0
mA
5.0
mA
13.0
mA
(23.6)
22.0
22.5
23.0
V
130
(21.4)
150
170
Hz
Note (1) FLM,CL1,CL2,DISP,D0~D7.
Note (2) fFLM=150Hz,Ta=25°C,Display pattern is Black/White cross pattern as below.
Electrical Characteristics of Backlight
Min.
Typ.
Max.
Unit
Item
Symbol
Voltage
VLED
(4.2)
(4.3)
(4.4)
V
Current
ILED
288.0
mA
Number of LED
16
EA
Power Consumption
1.24
W
Note (1): VLED = VLED(+) – VLED(-) .
Note (2): The current of LED is 18 mA for each one.
LED driving in constant current mode is recommended .
Note (3): LED power consumption is around 0.0775W for each one.
Condition
Note 1
Note 2
Note 3
Page 5
Optical Characteristics
Optical Characteristics of LCD
Condition
Item
Symbol
Viewing Angle Range φ1, φ2
θ=0°K 2
Contrast Ratio
K
θ=0° φ=0°
Rise
tr
θ=0°,φ=0°
Response Time
Fall
tf
θ=0°,φ=0°
x
R
y
x
G
y
Color Tone
θ=0°,φ=0°
x
(CIE Coordinate)
B
y
x
W
y
Note 1.
Definition of θ and φ
φ2
Y(θ=180°)
Min.
-
Typ.
(40)
20
40
-
(250)
-
ms
-
(200)
-
ms
(0.44)
(0.26)
(0.26)
(0.49)
(0.10)
(0.07)
(0.21)
(0.25)
(0.49)
(0.31)
(0.31)
(0.54)
(0.15)
(0.12)
(0.26)
(0.30)
(0.54)
(0.36)
(0.36)
(0.59)
(0.20)
(0.17)
(0.31)
(0.35)
-
Note 2
-
Definition of Viewing angle φ1 and φ2
Note 2.
Eye from (θ,φ1)
Ta= 25°C.(Backlight On)
Max.
Unit
Remark
Deg.
Note 1,2
Note 2
CR
Eye from (θ,φ2)
φ1
X
X‘
θ
Y(θ=0°)
2.0
φ1<0°<φ2
φ1
φ2
CR vs Viewing and φ
Page 6
Optical Characteristics of Backlight
Item
Min,
Brightness
100
Brightness Uniformity
-
Typ.
150
-
Max.
±30
Unit
2
cd/m
%
Remark
Note 1,2,3
Note 2,3,4
Note 1. Measurement Condition:
• Display data should be all “ON” (D0~D7=HIGH).
• VDD=5.0V, VLED=4.3V, ILED=288mA,VLCD should be adjusted at the voltage where
the peak contrast is obtained by naked eyes as the “All Q” pattern.
Note 2. Measurement of the following 5 points on the display.
Y=160 Y=480
Y=800
dots
Active area
X=60
X=120
X=180
P1
P4
P3
P2
P5
dots
Note3. The brightness shall be the average of P1~P5 point.
Note 4. Definition of the brightness Uniformity
(
Max brightness or Min brightness – Average brightness
Average brightness
)
x100%
P age 7
Interface Timing Chart
Timing Chart
CL1
(240+n)xT
FLM
X1
D0~D7
X2
X239 X240
Dummy data
T
CL1
CL2
X2
X1
D7
R0
B2
G5
B314
G317
D6
G0
R3
B5
R315
B317
D5
B0
G3
R6
G315
R318
D4
R1
B3
G6
B315
G318
D3
G1
R4
B6
R316
B318
D2
B1
G4
R7
G316
R319
D1
R2
B4
G7
B316
G319
D0
G2
R5
B7
R317
B319
P age 8
Electrical Characteristics
(MODE1)
(VDD=3.0~4.5V , V0= +10.0~ +42.0V, Ta=+0°C~50°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Shift clock period
tWCK
66
ns
Shift clock “H” pulse wide
tWCKH
23
ns
Shift clock “L” pulse wide
tWCKL
23
ns
Data setup time
tDS
10
ns
Data hold time
tDH
25
ns
Latch pulse “H” pulse wide
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
10
ns
Shift clock fall to latch pulse fall time
tSL
30
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Enable setup time
tTS
12
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
Output delay time
tD
44
ns
FLM setup time
tFS
30
ns
FLM hold time
tFH
50
ns
Note 1: (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation
tWLPH
VIH
CL1
tLD
CL2
D0~D7
tR
tLS
VIL
tSL
tLH
tWCKH
tWCKL
VIH
VIL
tF
tWCK
tDS
VIH
VIL
LAST DATA
tDH
TOP DATA
Horizontal retrace period
VIH
VIL
CL1
tDS
tDH
1
2
..
20
CL2
tFS
tFH
FLM
P age 9
(VDD=4.5~5.5V , V0= +10.0~ +42.0V, Ta=+0°C~50°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Shift clock period
tWCK
40
ns
Shift clock “H” pulse wide
tWCKH
12
ns
Shift clock “L” pulse wide
tWCKL
14
ns
Data setup time
tDS
5
ns
Data hold time
tDH
15
ns
Latch pulse “H” pulse wide
tWLPH
15
ns
Shift clock rise to latch pulse rise time
tLD
5
ns
Shift clock fall to latch pulse fall time
tSL
25
ns
Latch pulse rise to shift clock rise time
tLS
25
ns
Latch pulse fall to shift clock fall time
tLH
25
ns
Enable setup time
tTS
5
ns
Input signal rise time (Note 1)
tR
50
ns
Input signal fall time (Note 1)
tF
50
ns
Output delay time
tD
28
ns
FLM setup time
tFS
30
ns
FLM hold time
tFH
50
ns
Note 1: (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation
(MODE2)
P age 10
Power Supply and Signal Sequence
Do not apply DC voltage to the LCD panel because that induces the electrochemical
reaction and reduces its life time. Please follow the power supply ON/OFF sequence
to prevent DC driving of LCD or latch-up of COMS LSI, as shown below.
max 1ms
VDD
VDD
VSS
Sig
VSS
(FRM, CL1, CL2, DATA)
VLCD
VLCD
VSS
VI
VI
min0
min0
VI
VSS
VI
VI
VI
VDD
min0
VSS
min0
VI
VI
VLCD
VI
VI
min0
min 1FRM
VI
DISPOFF VSS
VI
min 1ms
POWER ON
VSS
VSS
POWER OFF
Note 1. Please keep the specified sequence because wrong sequence may cause
permanent damage to the LCD panel.
Note 2. Please use DISPOFF function. Switching by other than the DISPOFF
function may cause display deterioration.
Note 3. VLCD voltage should be set up to adjusted voltage before DISPOFF signal
arises. Otherwise, when DISPOFF signal arises, adjusted contrast image
may not be generated.
Note 4. Please keep the specified sequence of DISPOFF signal because if the
signal is short enough, LCD panel may not be restarted. (min. 1ms)
P age 11
Input Data Allocation Table
D D D D
Data Signal
7 6 5 4
Y
1
2
3
4
D
3
5
D
2
6
D
1
7
D
0
8
D
7
9
D
6
D
5
D
4
D
4
D
3
D
2
D
1
D
0
10 11 12
9
5
6
9
5
7
9
5
8
9
5
9
9
6
0
G
G
G
G
G
G
G
G
G
G
|
|
|
G
G
G
B
B
B
B
B
B
B
B
B
B
|
|
|
B
B
B
R
R
R
R
R
R
R
R
R
R
|
|
|
R
R
R
G
G
G
G
G
G
G
G
G
G
|
|
|
G
G
G
B
B
B
B
B
B
B
B
B
B
|
|
|
B
B
B
X
1
2
3
4
5
6
7
8
9
10
|
|
|
238
239
240
R
R
R
R
R
R
R
R
R
R
|
|
|
R
R
R
G
G
G
G
G
G
G
G
G
G
|
|
|
G
G
G
B
B
B
B
B
B
B
B
B
B
|
|
|
B
B
B
R
R
R
R
R
R
R
R
R
R
|
|
|
R
R
R
G
G
G
G
G
G
G
G
G
G
|
|
|
G
G
G
B
B
B
B
B
B
B
B
B
B
|
|
|
B
B
B
R
R
R
R
R
R
R
R
R
R
|
|
|
R
R
R
G
G
G
G
G
G
G
G
G
G
|
|
|
G
G
G
B
B
B
B
B
B
B
B
B
B
|
|
|
B
B
B
R
R
R
R
R
R
R
R
R
R
|
|
|
R
R
R
G
G
G
G
G
G
G
G
G
G
|
|
|
G
G
G
B
B
B
B
B
B
B
B
B
B
|
|
|
B
B
B
-------
R : RED
G : GREEN
B : BLUE
P age 12
Page 13
G B
G B
R
R
V IE W DIR E C T ION
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