ISSI IS65WV2568EALL Three state output Datasheet

IS62/65WV2568EALL
IS62/65WV2568EBLL
PRELIMINARY INFORMATION
OCTOBER 2014
256Kx8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES







DESCRIPTION
High-speed access time: 45ns, 55ns
CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
TTL compatible interface levels
Single power supply
–1.65V-2.2V VDD (IS62/65WV2568EALL)
– 2.2V-3.6V VDD (IS62/65WV2568EBLL)
Three state outputs
Industrial and Automotive temperature support
Lead-free available
The ISSI IS62/65WV2568EALL/EBLL are high-speed,
2M bit static RAMs organized as 256K words by 8 bits.
It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields highperformance and low power consumption devices.
When
is HIGH (deselected) or when CS2 is
LOW (deselected), the device assumes a standby
mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs. The active LOW
Write Enable
controls both writing and reading
of the memory.
The IS62/65WV2568EALL/EBLL are packaged in the
JEDEC standard 32-pin TSOP (TYPE I), sTSOP
(TYPE I), and 36-pin mini BGA..
FUNCTIONAL BLOCK DIAGRAM
DECODER
A0 – A17
256K x 8
MEMORY
ARRAY
VDD
GND
I/O0 – I/O7
CS2
CS1#
OE#
WE#
I/O
DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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IS62/65WV2568EALL
IS62/65WV2568EBLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
1
A
A0
B
I/O4
C
I/O5
D
GND
D
2
A1
A2
32-Pin TSOP (Type I), STSOP (Type I)
3
4
CS2
WE#
A3
A4
NC
5
A6
A7
A5
I/O6
G
I/O7
H
A9
A8
A11
1
32
OE#
A9
2
A8
3
31
30
CS1#
I/O7
A10
A13
4
29
WE#
5
28
I/O6
I/O0
CS2
6
27
I/O5
A15
7
26
I/O4
I/O1
VDD
A17
8
9
25
24
I/O3
GND
A16
10
23
I/O2
A14
11
22
I/O1
A12
12
21
A7
13
20
I/O0
A0
A6
A5
14
19
14
A4
16
18
17
VDD
VDD
F
6
GND
NC
A17
I/O2
OE#
CS1#
A16
A15
I/O3
A10
A11
A12
A13
A14
A1
A2
A3
PIN DESCRIPTIONS
A0-A17
I/O0-I/O7
, CS2
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
NC
VDD
GND
No Connection
Power
Ground
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IS62/65WV2568EBLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. SRAM has three different modes supported. Each function is described
below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (
HIGH or CS2 LOW ). The input and output pins (I/O0-7) are
placed in a high impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (
LOW and CS2 HIGH) and Write Enable (
) input LOW. The input
and output pins(I/O0-7) are in data input mode. Output buffers are closed during this time even if
is LOW.
READ MODE
Read operation issues with Chip selected (
LOW and CS2 HIGH) and Write Enable (
) input HIGH. When
is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
In the READ mode, output buffers can be turned off by pulling
HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
Not Selected
Output Disabled
Write
Read
CS2
H
X
L
L
L
X
L
H
H
H
I/O0-I/O7
X
X
H
H
L
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X
X
H
L
X
High-Z
High-Z
High-Z
DIN
DOUT
VDD Current
ISB1,ISB2
ICC
ICC
ICC
3
IS62/65WV2568EALL
IS62/65WV2568EBLL
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vter m
tBIAS
VDD
tStg
IOUT
(2)
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
V DD Related to GND
Storage Temperature
Value
–0.2 to +3.9(VDD+0.3V)
–55 to +125
–0.2 to +3.9(VDD+0.3V)
–65 to +150
DC Output Current (LOW)
20
Unit
V
C
V
C
mA
Notes:
1.
2.
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
This condition is not per pin. Total current of all pins must meet this value.
OPERATING RANGE(1)
Range
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Note:
1.
Device Marking
IS62WV2568EALL
IS62WV2568EALL
IS65WV2568EALL
IS62WV2568EBLL
IS62WV2568EBLL
IS65WV2568EBLL
Ambient Temperature
0C to +70C
-40C to +85C
-40C to +125C
0C to +70C
-40C to +85C
-40C to +125C
VDD
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
2.2V-3.6V
2.2V-3.6V
2.2V-3.6V
Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE (1)
Parameter
Input capacitance
DQ capacitance (IO0–IO7)
Symbol
CIN
CI/O
Test Condition
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
Max
10
10
Units
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Thermal resistance from junction to ambient (airflow = 1m/s)
Thermal resistance from junction to pins
Thermal resistance from junction to case
Symbol
RθJA
RθJB
RθJC
Rating
TBD
TBD
TBD
Units
°C/W
°C/W
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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ELECTRICAL CHARACTERISTICS
IS62(5)WV2568EALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
VOL
VIH(1)
VIL(1)
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
IOH = -0.1 mA
IOL = 0.1 mA
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
VDD + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV2568EBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
VIH(1)
Input HIGH Voltage
VIL(1)
Input LOW Voltage
ILI
ILO
Input Leakage
Output Leakage
Test Conditions
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
2.2 ≤ VDD < 2.7
2.7 ≤ VDD ≤ 3.6
2.2 ≤ VDD < 2.7
2.7 ≤ VDD ≤ 3.6
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
2.0
2.4
—
—
1.8
2.2
–0.3
–0.3
–1
–1
Max.
—
—
0.4
0.4
VDD + 0.3
VDD + 0.3
0.6
0.8
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
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IS62/65WV2568EALL
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IS62(5)WV2568EALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
ICC
ICC1
ISB2
Parameter
VDD Dynamic
Operating
Supply Current
VDD Static
Operating
Supply Current
CMOS Standby
Current (CMOS
Inputs)
Test Conditions
VDD=VDD(max), IOUT=0mA, f=fMAX
VDD=VDD(max), IOUT = 0mA, f=0Hz
VDD=VDD(max),
(1) 0V ≤ CS2 ≤ 0.2V
or
(2)
≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
, f= 0Hz
Grade
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Com.
Typ.
12
1
2
Max.
15
18
25
3
3
4
5
Unit
mA
Ind.
-
12
µA
Auto.
-
25
µA
mA
µA
Note:
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25C
IS62(5)WV2568EBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
ICC
ICC1
ISB2
Parameter
VDD Dynamic
Operating
Supply Current
VDD Static
Operating
Supply Current
CMOS Standby
Current (CMOS
Inputs)
Test Conditions
VDD=VDD(max), IOUT=0mA, f=fMAX
VDD=VDD(max), IOUT = 0mA, f=0Hz
VDD=VDD(max),
(1) 0V ≤ CS2 ≤ 0.2V
or
(2)
≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
, f= 0Hz
Grade
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Com.
Typ.
12
1
2
Max.
15
18
25
3
3
4
5
Unit
mA
Ind.
-
12
µA
Auto.
-
25
µA
mA
µA
Note:
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25℃
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IS62/65WV2568EALL
IS62/65WV2568EBLL
AC CHARACTERISTICS(6) (OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
Read Cycle Time
Address Access Time
Output Hold Time
tRC
tAA
tOHA
tACS1/tACS2
tDOE
tHZOE
tLZOE
tHZCS//tHZCS2
tLZCS/tLZCS2
, CS2 Access Time
Access Time
to High-Z Output
to Low-Z Output
, CS2 to High-Z Output
, CS2 to Low-Z Output
45ns
Min
45
8
5
10
55ns
Max
45
45
22
18
18
-
Min
55
8
5
10
Max
55
55
25
18
18
-
unit
notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,5
1
1
1
1
2
2
2
2
unit
notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,3,5
1,3
1,3
1,3
1,3
1,3,4
1,3
1,3
2,3
2,3
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
Write Cycle Time
tWC
tSCS1/tSCS2
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
,CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
Pulse Width
Data Setup to Write End
Data Hold from Write End
LOW to High-Z Output
HIGH to Low-Z Output
45ns
Min
45
35
35
0
0
35
28
0
10
55ns
Max
18
-
Min
55
40
40
0
0
40
28
0
10
Max
18
-
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of
=LOW, CS2=HIGH, and
=LOW. All four conditions must be in valid states to initiate
a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE# is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Input Rise Time
Input Fall Time
Output Timing Reference Level
Output Load Conditions
Symbol
TR
TF
VREF
Conditions
1.0
1.0
½ VTM
Refer to Figure 1 and 2
Units
V/ns
V/ns
V
OUTPUT LOAD CONDITIONS FIGURES
Figure1
Figure2
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30pF,
includin
g jig
and
scope
Parameters
R1
R2
VTM
R2
VDD=1.65~1.98V
13500Ω
10800Ω
VDD
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5pF,
includin
g jig
and
scope
VDD=2.2~2.7V
16667Ω
15385Ω
VDD
R2
VDD=2.7~3.6V
1103Ω
1554Ω
VDD
8
IS62/65WV2568EALL
IS62/65WV2568EBLL
TIMING DIAGRAM
READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED) (
=
=VIL, CS2#=
=VIH)
tRC
ADDRESS
tAA
tOHA
tOHA
I/O0-15
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3) (
, CS2 &
Low-Z
DATA VALID
Low-Z
CONTROLLED)
tRC
ADDRESS
tAA
tOHA
tDOE
OE#
tHZOE
CS1#
tLZOE
tACE1/tACE2
CS2
DOUT
tLZCS1/
tLZCS2
HIGH-Z
Notes:
1.
is HIGH for Read Cycle.
2. The device is continuously selected.
,
3. Address is valid prior to or coincident with
tHZCS1/
tHZCS2
DATA VALID
,.CS2=
=VIH#.
LOW and CS2 HIGH transition.
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WRITE CYCLE NO. 1 (
CONTROLLED,
= HIGH OR LOW)
tWC
ADDRESS
tHA
CS1#
CS2
tAW
tPWE
WE#
tSA
tHZWE
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
tSD
DIN
tHD
DATA IN VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after
goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
goes high before
WRITE CYCLE NO. 2 (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
tWC
ADDRESS
OE#
tSCS1
tHA
CS1#
tSCS2
CS2
tAW
tPWE
WE#
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA -IN VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after
goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
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goes high before
10
IS62/65WV2568EALL
IS62/65WV2568EBLL
WRITE CYCLE NO. 3 (
CONTROLLED:
IS LOW DURING WRITE CYCLE)
tWC
ADDRESS
OE#
tHA
tSCS1
CS1#
tSCS2
CS2
tAW
tPWE
WE#
tSA
DOUT
tHZWE
DATA UNDEFINED
DIN
tLZWE
HIGH-Z
tSD
tHD
DATA-IN VALID
Notes:
1. If
is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous
READ operation will drive IO BUS.
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IS62/65WV2568EALL
IS62/65WV2568EBLL
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
OPTION
Min.
VDR
VDD for Data
Retention
See Data Retention Waveform
IS62(5)WV2568EALL
IS62(5)WV2568EBLL
Data Retention
Current
VDD= VDR(min),
(1) 0V ≤ CS2 ≤ 0.2V, or
(2)
≥ VDD – 0.2V,
CS2 ≥ VDD - 0.2V
IDR
Typ.(2)
Max.
Unit
1.5
-
V
1.5
-
V
uA
Com.
-
2
5
Ind.
-
-
12
Auto
-
-
25
tSDR
Data Retention
Setup Time
See Data Retention Waveform
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
-
ns
Note:
1. If
>VDD–0.2V, all other inputs including CS2 must meet this condition.
2. Typical values are measured at VDD=VDR(min), TA = 25℃ and not 100% tested.
DATA RETENTION WAVEFORM (
tSDR
CONTROLLED)
DATA RETENTION MODE
tRDR
VDD
VDR
> VDD-0.2V
GND
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
DATA RETENTION MODE
VDD
CS2
tSDR
tRDR
VDR
CS2 < 0.2V
GND
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IS62/65WV2568EALL
IS62/65WV2568EBLL
ORDERING INFORMATION
IS62WV2568EALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
55
55
55
55
55
55
Order Part No.
Package
IS62WV2568EALL-55TI
IS62WV2568EALL-55TLI
IS62WV2568EALL-55BI
IS62WV2568EALL-55BLI
IS62WV2568EALL-55HI
IS62WV2568EALL-55HLI
TSOP (Type I)
TSOP (Type I), Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
sTSOP (Type I)
sTSOP (Type I), Lead-free
IS62WV2568EBLL (2.2V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
45
45
45
45
45
45
Order Part No.
Package
IS62WV2568EBLL-45TI
IS62WV2568EBLL-45TLI
IS62WV2568EBLL-45BI
IS62WV2568EBLL-45BLI
IS62WV2568EBLL-45HI
IS62WV2568EBLL-45HLI
TSOP (Type I)
TSOP (Type I), Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
sTSOP (Type I)
sTSOP (Type I), Lead-free
IS65WV2568EBLL (2.2V - 3.6V)
Automotive Range (A3): –40°C to +125°C
Speed (ns)
55
Order Part No.
Package
IS65WV2568EBLL-55CTLA3
IS65WV2568EBLL-55HLA3
TSOP (Type II), Lead-free
sTSOP (Type I), Lead-free
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PACKAGE INFORMATION
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IS62/65WV2568EBLL
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