ICST ICS9248F-163-T Amd - k7 system clock chip Datasheet

ICS9248-163
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
AMD - K7™ System Clock Chip
Pin Configuration
VDDREF
REF0/CPU_STOP*
GND
X1
X2
VDD
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9248-163
Recommended Application:
VIA KX133 style chipset
Output Features:
•
1 - Differential pair open drain CPU clocks
•
1 - CPU clock @ 3.3V
•
13 - SDRAM @ 3.3V
•
6 - PCI @3.3V,
•
1 - 48MHz, @3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
2 - REF @3.3V, 14.318MHz.
Features:
•
Up to 166MHz frequency support
•
Support power management: CPU stop and Power down
Mode from I2C programming.
•
Spread spectrum for EMI control
(± 0.25% center spread).
•
Uses external 14.318MHz crystal
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS2*
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24/48MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Functionality
Block Diagram
PLL2
48MHz
24_48MHz
/2
X1
X2
REF (1:0)
XTAL
OSC
CPUCLK
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLKC0
CPUCLKT0
SEL24_48#
Control
SDATA
SCLK
Logic
FS (3:0)
Config.
PD#
CPU_STOP#
Reg.
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
SDRAM
DRIVER
BUFFER IN
9248-163 Rev A 9/22/00
Third party brands and names are the property of their respective owners.
SDRAM (11:0)
SDRAM_OUT
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
90.00
95.00
101.00
102.00
100.90
103.00
105.00
100.00
107.00
109.00
110.00
111.00
113.00
115.00
117.00
133.30
PCICLK
(MHz)
30.00
31.67
33.67
34.00
33.57
34.33
35.00
33.33
35.67
36.33
36.67
37.00
37.67
38.33
39.00
33.33
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9248-163
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
1
P I N NA M E
VDDREF
REF0
TYPE
PWR
OUT
2
CPU_STOP#1, 2
3,9,16,22,
33,39,45, 47
GND
IN
PWR
4
X1
IN
5
X2
OUT
6
VDD
PWR
PCICLK_F
OUT
7
MODE1, 2
8
10
13, 12, 11
14
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
19,30,36
23
24
25
26
IN
DESCRIPTION
REF, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM
(11:0) at logic "0" level when driven low.
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Supply for internal digital logic
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-up to VDD
PCI clock output
Logic input to select 24 or 48MHz for pin 25 output
PCI clock output.
PCI clock outputs.
Supply for PCICLK_F and PCICLK, nominal 3.3V
Input to Fanout Buffers for SDRAM outputs.
FS31, 2
PCICLK0
SEL24_48#1, 2
PCICLK1
PCICLK (4:2)
VDDPCI
BUFFER IN
IN
OUT
IN
OUT
OUT
PWR
IN
SDRAM (11:0)
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
VDDSDR
SDATA
SCLK
PWR
I/O
IN
Supply for SDRAM 9nominal 3.3V.
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
24_48MHz
OUT
24MHz/48MHz clock output
FS1
1, 2
48MHz
FS01, 2
IN
OUT
IN
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
27
VDD48
PWR
Power for 24 & 48MHz output buffers and fixed PLL core.
40
SDRAM_OUT
OUT
Reference clock for SDRAM buffer
41
PD#
42
VDDA
PWR
43
CPUCLKT0
OUT
44
CPUCLKC0
OUT
46
CPUCLK
REF1
FS21, 2
OUT
OUT
IN
48
IN
Powers down chip, active low
Supply for core, & CPU 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
3.3V CPU clock output powered by VDDA
14.318 MHz reference clock.
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-163
Preliminary Product Preview
General Description
The ICS9248-163 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks
required for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-163
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE, Pin 7
(Latched Input)
Pin 2
0
CPU_STOP#
(Input)
REF0
(Output)
1
Power Groups
VDD48 = 48MHz, PLL2
VDDA = VDD for Core PLL, CPU
VDDREF = REF, Xtal
Third party brands and names are the property of their respective owners.
3
ICS9248-163
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2,
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit Bit Bit Bit Bit
CPUCLK
PCICLK
2
7
6
5
4
(MHz)
(MHz)
0
0
0
0
0
90.00
30.00
0
0
0
0
1
95.00
31.67
0
0
0
1
0
101.00
33.67
0
0
0
1
1
102.00
34.00
0
0
1
0
0
100.90
33.57
0
0
1
0
1
103.00
34.33
0
0
1
1
0
105.00
35.00
0
0
1
1
1
100.00
33.33
0
1
0
0
0
107.00
35.67
0
1
0
0
1
109.00
36.33
0
1
0
1
0
110.00
36.67
0
1
0
1
1
111.00
37.00
0
1
1
0
0
113.00
37.67
0
1
1
0
1
115.00
38.33
0
1
1
1
0
117.00
39.00
0
1
1
1
1
133.30
33.33
1
0
0
0
0
120.00
40.00
1
0
0
0
1
125.00
31.25
1
0
0
1
0
130.00
32.50
1
0
0
1
1
133.73
33.43
1
0
1
0
0
135.00
33.75
1
0
1
0
1
137.00
34.25
1
0
1
1
0
139.00
34.75
1
0
1
1
1
100.00
33.33
1
1
0
0
0
140.00
35.00
1
1
0
0
1
143.00
35.75
1
1
0
1
0
145.00
36.25
1
1
0
1
1
148.00
37.00
1
1
1
0
0
150.00
37.50
1
1
1
0
1
155.00
38.75
1
1
1
1
0
166.66
41.67
1
1
1
1
1
133.33
33.33
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ±0.25% Center Spread
0 - Running
1- Tristate all outputs
PWD
Spread
Precentage
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
4
Reserved
0
1
0
ICS9248-163
Preliminary Product Preview
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
Bit 7
-
X
FS2#
DESCRIPTION
Bit 6
-
1
(Reserved)
Bit 5
Bit 5
-
1
(Reserved)
Bit 4
-
X
FS3#
Bit 3
40
1
SDRAM_OUT
Bit 2
-
X
Bit 1
43,44
1
Bit 0
46
1
BIT
(SEL24_48#)#
CPUCLK0 enable (both
differential pair. "True" and
Complimentary")
CPUCLKT enable
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
PIN#
PWD
DESCRIPTION
Bit 7
-
X
FS0#
Bit 6
7
1
PCICLK_F
-
1
(Reserved)
Bit 4
13
1
PCICLK4
Bit 3
12
1
PCICLK3
Bit 2
11
1
PCICLK2
Bit 1
10
1
PCICLK1
Bit 0
8
1
PCICLK0
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
DESCRIPTION
PIN# PWD
DESCRIPTION
Bit 7
-
1
(Reserved)
Bit 7
28
1
SDRAM 7
Bit 6
-
1
(Reserved)
Bit 6
29
1
SDRAM 6
31
1
SDRAM 5
Bit 5
26
1
48MHz
Bit 5
Bit 4
25
1
24_48MHz
Bit 4
32
1
SDRAM 4
Bit 3
17
1
SDRAM 11
Bit 3
34
1
SDRAM 3
Bit 2
18
1
SDRAM 10
Bit 2
35
1
SDRAM 2
Bit 1
20
1
SDRAM 9
Bit 1
37
1
SDRAM 1
Bit 0
21
1
SDRAM 8
Bit 0
38
1
SDRAM 0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN# PWD
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DESCRIPTION
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
X
MODE#
Bit 3
-
X
FS1#
Bit 2
-
1
(Reserved)
Bit 1
48
1
REF1
Bit 0
2
1
REF0
PWD
0
0
0
0
0
1
1
0
DESCRIPTION
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
PIN#
-
5
ICS9248-163
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP66
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66MHz
Supply Current
IDD3.3OP100
CL = 0 pF; Select @ 100MHz
IDD3.3OP133
CL = 0 pF; Select @ 133MHz
Power Down
Input frequency
Input Capacitance1
Clk Stabilization
1
Skew
1
1
CONDITIONS
PD
Fi
CIN
CINX
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
TSTAB
From VDD = 3.3 V to 1% target Freq.
Guaranteed by design, not 100% tested in production.
6
TYP
-5
-200
12
tCP U-SDRAM
tCP U-P CI VT = 50%
tCP U-AGP
Third party brands and names are the property of their respective owners.
MIN
2
VSS-0.3
14.318
MAX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
180
mA
600
µA
MHz
pF
pF
27
16
5
45
-125
-100
-500
3
125
100
500
ms
ps
ICS9248-163
Preliminary Product Preview
Electrical Characteristics - USB, REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
1
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
MIN
2.4
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
16
TYP
MAX UNITS
V
0.4
V
-22
mA
mA
tr5
VOL = 0.4 V, VOH = 2.4 V
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V
4
ns
d t5
VT = 50%
55
%
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
SYMBOL
ZO
Output High Voltage
VOH2B
Output Low Voltage
VOL2B
Output Low Current
IOL2B
CONDITIONS
VO = VX
Termination to
Vpull-up(external)
Termination to
Vpull-up(external)
VOL = 0.3 V
tr2B
VOL = 0.3 V, VOH = 1.2 V
0.9
ns
tf2B
VOH = 1.2 V, VOL = 0.3 V
0.9
ns
Differential voltage-AC1
VDIF
Note 2
0.4
Differential voltage-DC1
VDIF
Note 2
0.2
VX
Note 3
550
1100
mV
dt2B
tsk2B
VT = 50%
VT = 50%
VT = VX
VT = 50%
45
55
200
250
+250
%
ps
ps
ps
Rise Time
Fall Time
1
1
Differential Crossover
Voltage1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
tjcyc-cyc2B
tjabs2B
MIN
1
TYP
MAX
UNITS
Ω
1.2
V
0.4
V
18
-250
mA
Vpullup(external)
+ 0.6
Vpullup(external)
+ 0.6
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup (external)/2-150mV; Max=(Vpullup (external)/2)+150mV
Third party brands and names are the property of their respective owners.
7
V
V
ICS9248-163
Preliminary Product Preview
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
CONDITIONS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
tr2B
VOL = 0.4 V, VOH = 2.0 V
1
VOH = 2.0 V, VOL = 0.4 V
Fall Time
tf2B
d t2B1
VT = 1.25 V
Skew
tsk2B1
Jitter, Cycle-to-cycle
tjcyc-cyc2B1
tj1s2B1
tjabs2B1
Jitter, One Sigma
Jitter, Absolute
1
TYP
19
1
Duty Cycle
MIN
2
MAX UNITS
V
0.4
V
-19
mA
mA
1.6
ns
1.6
ns
55
%
VT = 1.25 V
175
ps
VT = 1.25 V
250
ps
45
VT = 1.25 V
VT = 1.25 V
-250
150
ps
+250
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew (window)
1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.6
19
TYP
MAX UNITS
V
0.4
V
-16
mA
mA
tr1
VOL = 0.4 V, VOH = 2.4 V
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
2
ns
55
%
500
ps
d t1
Tsk
1
VT = 50%
45
VT = 1.5V
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-163
Preliminary Product Preview
Electrical Characteristics - PCICLK_F
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
CONDITIONS
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.6
TYP
12
MAX UNITS
V
0.4
V
-12
mA
mA
tr1
VOL = 0.4 V, VOH = 2.4 V
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
2
ns
55
%
200
ps
d t1
1
Skew (window)
1
SYMBOL
VOH1
VOL1
IOH1
IOL1
Tsk
1
VT = 50%
45
VT = 1.5V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
Jitter, One Sigma
Jitter, Absolute
1
1
1
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
16
TYP
MAX UNITS
V
0.4
V
-22
mA
mA
tr5
VOL = 0.4 V, VOH = 2.4 V
4
ns
tf5
VOH = 2.4 V, VOL = 0.4 V
4
ns
d t5
VT = 50%
55
%
tj1s5
VT = 1.5 V
0.5
ns
tjabs5
VT = 1.5 V
1
ns
45
-1
Guaranteed by design, not 100% tested in production.
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9
ICS9248-163
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
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10
ICS9248-163
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248163 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
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11
ICS9248-163
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered
to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state
as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may
require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-163 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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12
ICS9248-163
Preliminary Product Preview
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-163. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-163.
3. All other clocks continue to run undisturbed.
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13
ICS9248-163
Preliminary Product Preview
SYMBOL
In Millimeters
COMMON DIMENSIONS
MIN
MAX
In Inches
COMMON DIMENSIONS
MIN
MAX
A
2.413
2.794
.095
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
.005
.010
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
α
0.635
0°
.110
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
28
9.398
9.652
.370
.380
34
11.303
11.557
.445
.455
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
64
20.828
21.082
.820
.830
VARIATIONS
D mm.
N
D (inch)
Ordering Information
ICS9248yF-163-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
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14
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.