To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ●Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized) ●Serial I/O2 ................................... 8-bit ✕ 1 (Clock-synchronized) ●PWM output .................................................................... 8-bit ✕ 1 ●A-D converter ............................................... 10-bit ✕ 8 channels ●D-A converter ................................................. 8-bit ✕ 2 channels ●LCD drive control circuit Bias ................................................................................... 1/2, 1/3 Duty ........................................................................... 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ........................................................................ 40 ●2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) ●Watchdog timer ............................................................ 14-bit ✕ 1 ●Power source voltage ................................................ 2.2 to 5.5 V ●Power dissipation In high-speed mode .......................................................... 40 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) ●Operating temperature range................................... – 20 to 85°C DESCRIPTION The 7513 group is the 8-bit microcomputer based on the 740 family core technology. The 7513 group has the LCD drive control circuit, the A-D/D-A converter, the UART, and the PWM as additional functions. The various microcomputers in the 7513 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 7513 group, refer to the section on group expansion. FEATURES ●Basic machine-language instructions ...................................... 71 ●The minimum instruction execution time ........................... 0.5 µs (at 8MHz oscillation frequency) ●Memory size ROM ............................................................... 32 K to 60 K bytes RAM ............................................................... 1024 to 2048 bytes ●Programmable input/output ports ............................................ 55 ●Output port ................................................................................. 8 ●Input port .................................................................................... 1 ●Interrupts ................................................. 17 sources, 16 vectors (includes key input interrupt) ●Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2 APPLICATIONS Camera, Wireless phone, etc. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 58 57 56 55 54 53 52 51 64 63 62 61 60 59 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M37513EFFS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 10 6 7 8 5 3 4 C1 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/φ/TOUT P42/INT2 P41/INT1 P40/ADT P77 P76 P75 P74 2 100 1 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 71 70 69 68 67 66 65 80 79 78 77 76 75 74 73 72 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 P14/SEG38 P15/SEG39 PIN CONFIGURATION (TOP VIEW) Package type : 100D0 (Window type ceramic LCC) Fig. 1 M37513EFFS pin configuration P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN XCOUT XCIN RESET P70/INT0 P71 P72 P73 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 53 52 51 57 56 55 54 70 69 68 67 66 65 64 63 62 61 60 59 58 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 50 49 48 47 46 45 M37513M8-XXXGP M37513M8-XXXHP 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 98 99 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P14/SEG38 P15/SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN XCOUT XCIN RESET P70/INT0 P71 P72 P73 P74 P75 P76 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCL K22/AN3 P62/SCL K21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCL K1 P45/TXD P44/RXD P43/φ/TOUT P42/INT2 P41/INT1 P40/ADT P77 10 100 1 2 3 4 5 6 7 8 9 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VC C VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 C1 VL1 73 72 71 75 74 SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 PIN CONFIGURATION (TOP VIEW) Package type : GP........ 100P6Q-A (100-pin plastic-molded LQFP) Package type : HP ........ 100PFB-A (100-pin plastic-molded TQFP) Fig. 2 M37513M8-XXXGP/M37513M8-XXXHP pin configuration 2 X COUT CIN I/O port P7 P7(8) Watchdog timer Sub-clock output Sub-clock input X COUT Sub-clock output X CIN Sub-clock input XCIN XCOUT X Main clock output X OUT φ P6(8) SI/O2(8) I/O port P6 Reset Clock generating circuit X IN Main clock input VREF AVSS A-D converter (10) PC H C P U DA2 DA1 ADT I/O port P5 P5(8) CNTR0,CNTR1 PS PCL S Y X A PWM(8) I/O port P4 P4(8) φ SI/O1 (8) Timer 1(8) Output port P3 P3(8) TOUT Timer 3(8) Timer 2(8) Timer Y(16) Timer X(16) ROM VSS VCC RESET Data bus (0V) (5V) Reset input INT1,INT2 FUNCTIONAL BLOCK DIAGRAM I/O port P2 P2(8) D-A2 LCD display RAM (20 bytes) RAM P1(8) I/O port P1 D-A1 LCD drive control circuit I/O port P0 P0(8) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM0 COM1 COM2 COM3 VL1 C1 C2 VL2 VL3 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key input/key-on wake-up interrupt Real time port function INT0 Fig. 3 Functional block diagram 3 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description (1) Pin Name Function Function except a port function VCC, VSS Power source •Apply voltage of 2.2 V to 5.5 V to VCC, and 0 V to VSS. VREF Analog reference voltage •Reference voltage input pin for A-D converter and D-A converter. AVSS Analog power source •GND input pin for A-D converter and D-A converter. •Connect to VSS. RESET XIN Reset input •Reset input pin for active “L”. Clock input •Input and output pins for the main clock generating circuit. XOUT Clock output •Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. VL1–VL3 LCD power source •Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage. C 1 , C2 Charge-pump capacitor pin •External capacitor pins for a voltage multiplier (3 times) of LCD contorl. COM0–COM3 Common output •LCD common output pins. •Input 0 – VL3 voltage to LCD. •COM2 and COM3 are not used at 1/2 duty ratio. •COM3 is not used at 1/3 duty ratio. SEG0–SEG17 Segment output •LCD segment output pins. P00/SEG26– P07/SEG33 I/O port P0 •8-bit I/O port. •LCD segment output pins •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled. •I/O direction register allows each 8-bit pin to be programmed as either input or output. P10/SEG34– P15/SEG39 I/O port P1 •6-bit I/O port with same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled. •I/O direction register allows each 6-bit pin to be programmed as either input or output. P16, P17 •2-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. P20 – P27 I/O port P2 •Pull-up control is enabled. •8-bit I/O port with same function as P16 and P17. •CMOS compatible input level. •CMOS 3-state output structure. •Key input (key-on wake-up) interrupt input pins •Pull-up control is enabled. P30/SEG18 – P37/SEG25 Output port P3 •8-bit output port with same function as port P0. •LCD segment output pins •CMOS 3-state output structure. •Port output control is enabled. 4 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 2 Pin description (2) Pin P40/ADT Function Name •1-bit I/O port with same function as P16 and P17. •A-D trigger input pin •CMOS compatible input level. •N-channel open-drain output structure. •Interrupt input pin P41/INT1, P42/INT2 •7-bit I/O port with same function as P16 and P17. •Interrupt input pins P43/φ/TOUT •CMOS 3-state output structure. •Pull-up control is enabled. P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 I/O port P4 Function except a port function •CMOS compatible input level. •φ clock output pin •Timer 2 output pin •Serial I/O1 I/O pins I/O port P5 •8-bit I/O port with same function as P16 and P17. •PWM function pins •CMOS compatible input level. •CMOS 3-state output structure. P52/RTP0, P53/RTP1 •Real time port function pins •Pull-up control is enabled. P54/CNTR0, P55/CNTR1 •Timer X, Y function pins P56/DA1, P57/DA2 •D-A conversion output pins P60/AN0/SIN2, I/O port P6 P61/AN1/SOUT2, P62/AN2/SCLK21, P63/AN3/SCLK22 •8-bit I/O port with same function as P16 and P17. •A-D conversion input pins •CMOS compatible input level. •Serial I/O2 I/O pins •CMOS 3-state output structure. •Pull-up control is enabled. P64/AN4– P67/AN7 P70/INT0 •A-D conversion input pins Input port P7 •1-bit I/O port. •Interrupt input pin •CMOS compatible input level. P71–P77 I/O port P7 •7-bit I/O port with same function as P16 and P17. •CMOS compatible input level. •N-channel open-drain output structure. XCOUT Sub-clock output XCIN Sub-clock input •Sub-clock generating circuit I/O pins. (Connect a resonator. External clock cannot be used.) 5 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M37513 M 8 – XXX HP Package type HP : 100PFB-A package GP : 100P6Q-A package FS : 100D0 package ROM number Omitted in One Time PROM version shipped in blank and EPROM version. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size M37513M8-XXXGP/HP: 1024 byte M37513EFGP/HP/FS : 2048 bytes Fig. 4 Part numbering 6 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Package Mitsubishi plans to expand the 7513 group as follows: 100PFB-A ................................ 0.4 mm-pitch plastic molded TQFP 100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP 100D0 ..................... Window type ceramic LCC (EPROM version) Memory Type Support for Mask ROM, One Time PROM, and EPROM versions Memory Size ROM/PROM size ............................................... 32 K to 60 K bytes RAM size .......................................................... 1024 to 2048 bytes Memory Expansion Plan ROM size (bytes) Under development M37513EF 60 K 56 K 52 K 48 K 44 K 40 K 36 K Mass production M37513M8 32 K 28 K 24 K 20 K 16 K 12 K 8K 4K 192 256 384 512 640 768 896 1024 1152 1280 1408 1536 1664 1792 1920 2048 RAM size (bytes) Note: Products under development or planning: the development schedule and specifications may be revised without notice. Fig. 5 Memory expansion plan Currently supported products are listed below. As of Nov. 2000 Table 3 List of supported products Product M37513M8-XXXHP M37513M8-XXXGP M37513EFHP M37513EFGP M37513EFFS (P) ROM size (bytes) ROM size for User in ( ) RAM size (bytes) 32768 (32638) 1024 61440 (61310) 2048 Package 100PFB-A 100P6Q-A 100PFB-A 100P6Q-A 100D0 Remarks Mask ROM version Mask ROM version One Time PROM version (blank) One Time PROM version (blank) EPROM version 7 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) [Stack Pointer (S)] The 7513 group uses the standard 740 Family instruction set. Refer to the table of 740 Series addressing modes and machine instructions or the 740 Series Software Manual for details on the instruction set. Machine-resident 740 Series instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL . It is used to indicate the address of the next instruction to be executed. The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 PCH Stack pointer b0 Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig. 6 740 Family CPU register structure 8 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) – 1 M (S) (PCL) (S) (S)– 1 (S) M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) (S) – 1 (PCL) Push return address on stack (S) – 1 (PS) Push contents of processor status register on stack (S) – 1 Interrupt Service Routine Execute RTS (S) (PCH) I Flag is set from “0” to “1” Fetch the jump vector Execute RTI Note: Condition for acceptance of an interrupt (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) POP contents of processor status register from stack POP return address from stack Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 7 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP 9 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag D flag SEI CLI SED CLD B flag _ _ T flag V flag SET CLT CLV _ N flag _ _ 10 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B 16. b7 b0 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0: Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit.) Sub-clock (XCIN-XCOUT) stop bit 0 : Stopped 1 : Oscillating Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : XIN/2 (high-speed mode) 1 : XIN/8 (middle-speed mode) Internal system clock selection bit 0 : XIN-XOUT selected (middle-/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) Fig. 8 Structure of CPU mode register 11 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area 000016 RAM size (bytes) Address XXXX16 192 00FF 16 004016 256 013F 16 005416 384 01BF16 512 023F 16 640 02BF16 768 033F 16 896 03BF16 1024 043F 16 1536 063F 16 2048 083F 16 SFR area LCD display RAM area Zero page 010016 RAM XXXX16 Reserved area 084016 Not used ROM area ROM size (bytes) Address YYYY16 Address ZZZZ 16 4096 F000 16 F080 16 8192 E00016 E080 16 12288 D00016 D08016 16384 C00016 C08016 20480 B00016 B080 16 24576 A00016 A080 16 28672 900016 908016 32768 800016 808016 36864 700016 708016 40960 600016 608016 45056 500016 508016 49152 400016 408016 53248 300016 308016 57344 200016 208016 61440 100016 108016 YYYY16 Reserved ROM area (128 bytes) ZZZZ 16 ROM FF0016 FFDC16 Interrupt vector area Special page FFFE16 Reserved ROM area FFFF 16 Fig. 9 Memory map diagram 12 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 output control register (P1D) 002016 Timer X (low) (TXL) 002116 Timer X (high) (TXH) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 output control register (P3C) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 TOUT/φ output control register (CKOUT) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 002B16 PWM control register (PWMCON) 002C16 PWM prescaler (PREPWM) 000F16 Port P7 direction register (P7D) 002F16 003016 001016 001116 001216 001316 001416 001516 Key input control register (KIC) 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 Serial I/O2 control register (SIO2CON) 001E16 Reserved area 001F16 Serial I/O2 register (SIO2) 002216 Timer Y (low) (TYL) 002316 Timer Y (high) (TYH) 002D16 PWM register (PWM) 002E16 003116 A-D control register (ADCON) 003216 A-D conversion register (low-order) (ADL) 003316 A-D conversion register (high-order) (ADH) 003416 D-A1 conversion register (DA1) 003516 D-A2 conversion register (DA2) 003616 D-A control register (DACON) 003716 Watchdog timer control register (WDTCON) 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) Fig. 10 Memory map of special function register (SFR) 13 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS Direction Registers The I/O ports have direction registers which determine the input/ output direction of each individual pin. (P00–P07 and P10 –P15 use bit 0 of port P0, P1 direction registers respectively.) When “1” is written to that bit, that pin becomes an output pin. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating and the value of that pin can be read. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Port P3 Output Control Register Bit 0 of the port P3 output control register (address 000716) enables control of the output of ports P30 to P37 . When the bit is set to “1”, the port output function is valid. When resetting, bit 0 of the port P3 output control register is set to “0” (the port output function is invalid) and ports P3 0 to P37 are pulled up. Pull-up Control By setting the PULL register A (address 001616 ) or the PULL register B (address 001716 ), ports P1, P2, P4 to P6 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. The PULL register A setting is invalid for pins set to segment output on the segment output enable register. b7 b0 PULL register A (PULLA : address 001616) Not used P10–P13 pull-up P14, P15 pull-up P16, P17 pull-up P20–P23 pull-up P24–P27 pull-up b7 b0 PULL register B (PULLB : address 001716) P41–P43 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60–P63 pull-up P64–P67 pull-up Not used (return “0” when read) 0 : No pull-up 1 : Pull-up Note : The contents of PULL register A and PULL register B do not affect ports programmed as the output port. Fig. 11 Structure of PULL register A and PULL register B 14 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 6 List of I/O port function (1) Pin Name P00 /SEG26 – P07 /SEG33 Port P0 Input/output, byte unit CMOS compatible input level CMOS 3-state output LCD segment output Segment output enable register P10 /SEG34 – P15 /SEG39 Port P1 Input/output, 6-bit unit CMOS compatible input level CMOS 3-state output LCD segment output PULL register A Segment output enable register (3) (4) Input/output, individual bits CMOS compatible input level CMOS 3-state output PULL register A (6) Input/output, individual bits CMOS compatible input level CMOS 3-state output Key input (key-on wake-up) interrupt input PULL register A (6) P16 , P17 P20 –P27 Port P2 Input/Output I/O Format Non-Port Function Related SFRs Diagram No. (1) (2) Interrupt control register2 Key input control register Segment output enable register P3 output enable register (5) P30 /SEG18 – P37 /SEG25 Port P3 Output CMOS 3-state output LCD segment output P40 /ADT Port P4 Input/output, individual bits CMOS compatible input level N-channel open-drain output A-D trigger input External interrupt input A-D control register Interrupt edge selection register (15) CMOS compatible input level CMOS 3-state output External interrupt input PULL register B Interrupt edge selection register PULL register B Timer 123 mode register TOUT /φ output control register PULL register B Serial I/O1 control register Serial I/O1 status register UART control register (6) P41 /INT1 , P42 /INT2 P43/φ/TOUT Timer output φ output P44 /RXD, P45 /TXD, P46 /SCLK1 , P47 /SRDY1 Serial I/O1 function I/O P50 /PWM0, P51 /PWM1 Input/output, individual bits CMOS compatible input level CMOS 3-state output (7) (8) (9) (10) PWM output PULL register B PWM control register (12) Real time port function output PULL register B Timer X mode register (11) P54 /CNTR0 Timer X function I/O (13) P55 /CNTR1 Timer Y function input PULL register B Timer X mode register PULL register B P56 /DA1 DA 1 output A-D V REF input P57 /DA2 DA2 output P52 /RTP0 , P53 /RTP1 Port P5 (14) Timer Y mode register PULL register B D-A control register A-D control register PULL register B D-A control register (16) (17) (17) 15 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 7 List of I/O port function (2) Pin P60 /SIN2/AN0 Name Port P6 P61 /SOUT2/ AN 1 Input/Output Input/ output, individual bits I/O Format CMOS compatible input level CMOS 3-state output Non-Port Function A-D conversion input Serial I/O2 function I/O Related SFRS A-D control register Serial I/O2 control register Diagram No. (19) (20) P62 /SCLK21/ AN 2 (21) P63 /SCLK22 / AN 3 (22) P64 /AN4– P67 /AN7 P70 /INT0 Port P7 P71 –P77 Input CMOS compatible input level Input/ output, individual bits CMOS compatible input level N-channel open-drain output COM0–COM3 Common Output LCD common output SEG 0–SEG17 Segment Output LCD segment output A-D conversion input A-D control register (18) External interrupt input Interrupt edge selection register (25) (15) LCD mode register (23) (24) Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow VCC to V SS through the input-stage gate. 16 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P01–P07 VL2/VL3/VCC LCD drive timing Segment data Data bus Port latch Interface logic level shift circuit Segment/Port Segment Port direction register VL1/VSS Port Port/Segment Port direction register (2) Port P00 VL2/VL3/VCC LCD drive timing Segment/Port Direction register Segment data Data bus Port latch Interface logic level shift circuit Segment Port/Segment Port direction register (3) Ports P11–P15 Pull-up LCD drive timing Segment data Port latch Data bus Interface logic level shift circuit VL2/VL3/VCC Segment/Port Segment Port direction register Port/Segment Port direction register VL1/VSS Port (4) Port P10 Pull-up VL2/VL3/VCC Segment/Port LCD drive timing Direction register Segment data Data bus VL1/VSS Port Port latch Interface logic level shift circuit Segment Port/Segment Port direction register VL1/VSS Port (5) Port P3 VL2/VL3/VCC Segment data Data bus Port latch LCD drive timing Segment/Port Interface logic level shift circuit Segment Port/Segment Output control VL1/VSS Port Fig. 12 Port block diagram (1) 17 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (6) Ports P16, P17, P2, P41, P42 (7) Port P44 Pull-up control Serial I/O1 enable bit Reception enable bit Direction register Data bus Pull-up control Direction register Port latch Port latch Data bus Key input interrupt input INT1, INT2 interrupt input Serial I/O1 input Except P16, P17 AAAAA AAAAA (8) Port P45 (9) Port P46 Pull-up control P45/TxD P-channel output disable bit Serial I/O1 enable bit Transmission enable bit Serial I/O1 clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Direction register Port latch Data bus Pull-up control Data bus Serial I/O1 output Port latch Serial I/O1 clock outupt Serial I/O1 clock input (11) Ports P52, P53 (10) Port P47 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Pull-up control Pull-up control Direction register Direction register Data bus Port latch Serial I/O1 ready output Data bus Port latch Real time control bit Real time port data Fig. 13 Port block diagram (2) 18 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (13) Port P54 (12) Ports P50,P51 Pull-up control Pull-up control Direction register Direction register Port latch Data bus Data bus Port latch Pulse output mode Timer output PWM function enable bit PWM output CNTR0 interrupt input (15) Ports P40, P71–P77 (14) Port P43 Pull-up control Direction register Direction register Data bus Data bus Port latch TOUT/φ output control Timer output TOUT/φ selection bit φ output Port latch A-D trigger input Except P71 to P77 (17) Ports P56, P57 (16) Port P55 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus CNTR1 interrupt input Except P57 Port latch D-A conversion output D-A1, D-A2 output enable bit VREF input switch VREF input selection bit Fig. 14 Port block diagram (3) 19 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (19) Port P60 (18) Ports P64–P67 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch Serial I/O2 input A-D conversion input Analog input pin selection bit A-D conversion input Analog input pin selection bit (20) Port P61 (21) Port P62 P61/SOUT2 P-channel output disable bit Serial I/O2 transmit completion signal Synchronous clock selection bit Serial I/O2 port selection bit Pull-up control Serial I/O2 port selection bit Synchronous clock output pin selection bit Direction register Data bus Pull-up control Synchronous clock selection bit Direction register Port latch Data bus Serial I/O2 output A-D conversion input Analog input pin selection bit Port latch Serial I/O2 clock output Serial I/O2 clock input A-D conversion input Analog input pin selection bit (22) Port P63 Pull-up control (23) COM0–COM3 Synchronous clock selection bit Serial I/O2 port selection bit Synchronous clock output pin selection bit VL 3 Direction register Data bus VL2 VL 1 Port latch The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VSS Serial I/O2 clock output A-D conversion input Analog input pin selection bit (25) Port P70 (24) SEG0–SEG17 Data bus VL2/VL3 The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. INT0 input VL1/VSS Fig. 15 Port block diagram (4) 20 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupt Operation Interrupts occur by seventeen sources: seven external, nine internal, and one software. Upon acceptance of an interrupt the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Interrupt Control Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time, the interrupt with highest priority is accepted first. ■Notes When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: A-D control register (address 003116) Table 8 Interrupt vector addresses and priority Interrupt Source Priority Vector Addresses (Note 1) High Low Interrupt Request Generating Conditions At reset Non-maskable At detection of either rising or falling edge of INT0 input External interrupt (active edge selectable) Remarks Reset (Note 2) INT0 1 2 FFFD16 FFFB16 FFFC16 FFFA16 INT1 3 FFF916 FFF816 At detection of either rising or falling edge of INT1 input External interrupt (active edge selectable) Serial I/O1 reception 4 FFF716 FFF616 At completion of serial I/O1 data reception Valid when serial I/O1 is selected Serial I/O1 transmission 5 FFF516 FFF416 Valid when serial I/O1 is selected Timer X 6 FFF316 FFF216 At completion of serial I/O1 transmit shift or when transmission buffer is empty At timer X underflow Timer Y 7 FFF116 FFF016 At timer Y underflow Timer 2 Timer 3 FFEF16 FFED16 FFEB16 FFEE16 FFEC16 FFEA16 At timer 2 underflow CNTR0 8 9 10 CNTR1 11 FFE916 FFE816 External interrupt (active edge selectable) Timer 1 INT2 12 FFE716 FFE616 At detection of either rising or falling edge of CNTR1 input At timer 1 underflow 13 FFE516 FFE416 At detection of either rising or falling edge of INT2 input External interrupt (active edge selectable) Serial I/O2 14 FFE316 FFE216 At completion of serial I/O2 data transmission or reception Valid when serial I/O2 is selected Key input (Key-on wake-up) 15 FFE116 FFE016 At falling of conjunction of input level for port P2 (at input mode) ADT 16 FFDF16 FFDE16 At either rising or falling edge of ADT input External interrupt (valid at falling) External interrupt (Valid when ADT interrupt is selected A-D conversion BRK instruction 17 FFDD16 FFDC16 At timer 3 underflow At detection of either rising or falling edge of CNTR0 input External interrupt (active edge selectable) At completion of A-D conversion Valid when A-D interrupt is selected At BRK instruction execution Non-maskable software interrupt Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 21 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge selection bit (active edge switch bit) or the interrupt source selection bit to “1”. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Interrupt request BRK instruction Reset Fig. 16 Interrupt control b7 b0 Key input control register (KIC : address 001516) P20 trigger valid P21 trigger valid P22 trigger valid P23 trigger valid P24 trigger valid P25 trigger valid P26 trigger valid P27 trigger valid b7 bit bit bit bit bit bit bit bit b0 Interrupt request register 1 (IREQ1 : address 003C16) Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit ADT interrupt edge selection bit Not used (return “0” when read) 0 : Falling edge active 1 : Rising edge active 0 : Trigger invalid 1 : Trigger valid b7 b0 b7 b0 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit Serial I/O2 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNT R0 interrupt enable bit CNT R1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit Serial I/O2 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 17 Structure of interrupt-related registers 22 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key Input Interrupt (Key-on wake-up) A Key-on wake up interrupt request is generated by applying a falling edge to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P23. Port PXx “L” level output ✽ Port P27 output ✽ Port P26 output ✽ Port P25 output ✽ Port P24 output ✽ Port P23 input ✽ Port P22 input ✽ Port P21 input ✽ Port P20 input PULLA register Key input control register = “1” Bit 2 = “1” Port P27 direction register = “1” ✽✽ Port P27 latch Key input interrupt request Key input control register = “1” Port P26 direction register = “1” ✽✽ Port P26 latch Key input control register = “1” Port P25 direction register = “1” ✽✽ Port P25 latch Key input control register = “1” Port P24 direction register = “1” ✽✽ Port P24 latch Key input control register = “1” Port P23 direction register = “0” ✽✽ Port P23 latch Port P2 input reading circuit Key input control register = “1” Port P22 direction register = “0” ✽✽ Port P22 latch Key input control register = “1” Port P21 direction register = “0” ✽✽ Port P21 latch Key input control register = “1” Port P20 direction register = “0” ✽✽ Port P20 latch ✽ P-channel transistor for pull-up ✽✽ CMOS output buffer Fig. 18 Connection example when using key input interrupt and port P2 block diagram 23 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. TIMERS The 7513 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- Real time port control bit “1” Data bus Q D P52 data for real time port P 52 Latch “0” P52 direction register P52 latch Real time port control bit “1” Q D P53 data for real time port P 53 Real time port control bit “0” Latch “0” P53 direction register P53 latch f(XIN)/16 (f(XCIN)/16 in low-speed mode*) Timer X stop control bit Timer X operatCNT R0 active edge switch bit ing mode bits “00”,“01”,“11” “0” P54/CNTR0 “10” “1” Pulse width measurement mode CNTR0 active edge switch bit “0” “1” P54 direction register Timer X mode register write signal “1” Timer X write control bit Timer X (low) latch (8) Timer X (high) latch (8) Timer X (low) (8) Timer X (high) (8) CNTR0 interrupt request Pulse output mode QS Timer Y operating mode bit “00”,“01”,“10” T Q Pulse width HL continuously measurement mode P54 latch “11” Rising edge detection Pulse output mode Timer Y stop control bit “00”,“01”,“11” Timer Y (low) latch (8) P55/CNTR1 Timer Y (high) latch (8) Timer Y (low) (8) Timer Y (high) (8) “10” Timer Y operating mode bit “1” f(XIN)/16 (f(XCIN)/16 in low-speed mode*) Timer 1 count source selection bit “0” Timer 1 latch (8) XCIN CNT R1 interrupt request Period measurement mode Falling edge detection f(XIN)/16 (f(XCIN)/16 in low-speed mode*) CNT R1 active edge switch bit “0” Timer X interrupt request Timer 2 count source selection bit Timer 2 latch (8) “0” Timer 1 (8) Timer 2 (8) “1” “1” Timer 2 write control bit Timer Y interrupt request Timer 1 interrupt request Timer 2 interrupt request f(XIN)/16 (f(XCIN)/16 in low-speed mode*) TOUT output TOUT output active edge control bit TOUT output switch bit control bit “0” QS P43/φ/TOUT T “1” P43 latch Q P43 direction register f(XIN)/16(f(XCIN)/16 in low-speed mode*) “0” Timer 3 latch (8) Timer 3 (8) “1” Timer 3 count source selection bit Timer 3 interrupt request * φ = XCIN divided by 2 in low-speed mode Fig. 19 Timer block diagram 24 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X ■Notes on CNTR0 interrupt active edge selection Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. (1) Timer Mode The timer counts f(XIN)/16 (or f(X CIN)/16 in low-speed mode). (2) Pulse Output Mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR0 pin to input. ●Real time port control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1”, data are output without the timer X.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR 0 pin to input. (4) Pulse Width Measurement Mode The count source is f(XIN )/16 (or f(XCIN)/16 in low-speed mode). If CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR 0 pin is at “L”. When using a timer in this mode, set the port shared with tha CNTR0 pin to input. ●Timer X write control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. b7 b0 Timer X mode register (TXM : address 0027 16) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P52 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR 0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNTR 0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Fig. 20 Structure of timer X mode register 25 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer Mode The timer counts f(XIN)/16 (or f(X CIN)/16 in low-speed mode). (2) Period Measurement Mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR1 interrupt. When using a timer in this mode, set the port shared with the CNTR 1 pin to input. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR 1 pin to input. b7 b0 Timer Y mode register (TYM : address 0028 16) Not used (return “0” when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop Fig. 21 Structure of timer Y mode register (4) Pulse Width HL Continuously Measurement Mode CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the port shared with the CNTR1 pin to input. ■Notes on CNTR1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 26 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. ●Timer 2 write control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. ●Timer 2 output control When the timer 2 (TOUT) is output enabled, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the port shared with the TOUT pin to the output. ■Notes on timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. b7 b0 Timer 123 mode register (T123M :address 002916) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at ”L” output TOUT/φ output control bit 0 : TOUT/φ output disabled 1 : TOUT/φ output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode*) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode*) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode*) 1 : f(XCIN) Not used (return “0” when read) * Internal clock φ is XCIN/2 in the low-speed mode. Fig. 22 Structure of timer 123 mode register 27 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Clock Synchronous Serial I/O Mode SERIAL I/O Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock synchronous serial I/O1 can be selected by setting the mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer registers. Data bus Serial I/O1 control register Address 0018 16 Receive buffer register Receive shift register P44/RXD Address 001A 16 Receive buffer full flag (RBF) Receive interrupt request (RI) Shift clock Clock control circuit P46/SCLK Serial I/O1 clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C 16 BRG count source selection bit f(XIN ) (f(XCIN ) in low-speed mode) 1/4 P47/SRDY1 F/F Clock control circuit Falling-edge detector Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Shift clock P45 /TXD Transmit shift register Transmit buffer register Transmit buffer empty flag (TBE) Address 0019 16 Serial I/O1 status register Address 0018 16 Data bus Fig. 23 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output T XD D0 D1 D2 D3 D4 D5 D6 D7 Serial input R XD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal S RDY1 Write signal to receive/transmit buffer register (address 0018 16) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the T XD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 24 Operation of clock synchronous serial I/O1 function 28 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- Data bus Address 001816 P44/RXD Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive buffer register OE Character length selection bit STdetector 7 bits Receive shift register 1/16 8 bits UART control register Address 001B16 SP detector PE FE Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator Transmit shift register shift completion flag (TSC) 1/16 Transmit interrupt source selection bit Transmit shift register P45/TXD Transmit interrupt request (TI) Character length selection bit Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit buffer register Address 001816 Data bus Fig. 25 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output T XD TBE=0 TSC=1 ✽ TBE=1 ST D0 D1 SP ST D0 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) Receive buffer read signal ✽Generated RBF=0 RBF=1 Serial input R XD ST D0 D1 D1 SP ST D0 D1 SP at 2nd bit in 2-stop-bit mode RBF=1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 26 Operation of UART serial I/O1 function 29 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE. Writing “0” to the serial I/O1 enable bit (SIOE) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. ■ Notes When setting the transmit enable bit to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. ➀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON) ]001B16 This is a 5 bit register containing four control bits, which are valid when UART is selected and set the data format of an data receiver/transfer, and one control bit, which is always valid and sets the output structure of the P45/TXD pin. [Baud Rate Generator(BRG)] 001616 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 30 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O1 status register (SIO1STS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty b0 b0 Serial I/O1 control register (SIO1CON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN ) in low-speed mode) 1: f(XIN)/4 (f(X CIN)/4 in low-speed mode) Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. Overrun error flag (OE) 0: No error 1: Overrun error SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin. 1: P47 pin operates as S RDY1 output pin. Parity error flag (PE) 0: No error 1: Parity error Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Framing error flag (FE) 0: No error 1: Framing error Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Summing error flag (SE) 0: OE U PE U FE =0 1: OE U PE U FE =1 Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Not used (returns “1” when read) Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full b7 b7 UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 –P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44 –P47 operate as serial I/O pins) Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45 /TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) Fig. 27 Structure of serial I/O1 control registers 31 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. When an internal clock is selected as the synchronous clock of the serial I/O2, either P6 2 or P63 can be selected as an output pin of the synchronous clock. In this case, the pin that is not selected as an output pin of the synchronous clock functions as a port. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock select bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 0 0: 1 0 1: Do not set 1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) [Serial I/O2 Control Register (SIO2CON)] 001D16 Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK21/SCLK22 signal output The serial I/O2 control register contains 8 bits which control various serial I/O2 functions. P61/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Transfer direction selection bit 0: LSB first 1: MSB first Synchronous clock selection bit 0: External clock 1: Internal clock Synchronous clock output pin selection bit 0: SCLK21 1: SCLK22 Fig. 28 Structure of serial I/O2 control register 1/8 Divider 1/16 f(XIN) (f(XCIN) in low-speed mode) Internal synchronous clock select bits 1/32 Data bus 1/64 1/128 1/256 P63 latch (Note) P63/SCLK22 Synchronous clock selection bit “1” SCLK2 Synchronous circuit “0” External clock P62 latch “0” P62/SCLK21 (Note) “1” Serial I/O counter 2 (3) Serial I/O2 interrupt request P61 latch “0” P61/SOUT2 “1” Serial I/O2 port selection bit P60/SIN2 Serial I/O shift register 2 (8) Note: It is selected by the synchronous clock selection bit, the synchronous clock output pin selection bit, and the serial I/O port selection bit. Fig. 29 Block diagram of serial I/O2 function 32 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. When the external clock is selected as the transfer clock, a content of the serial I/O shift register is continued to shift during inputting a transfer clock. The SOUT2 pin does not go to high impedance after transfer completion. Fig. 30 Timing of serial I/O2 function 33 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PULSE WIDTH MODULATION (PWM) PWM Operation The 7513 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2. When at least either bit 1 (PWM0 output enable bit) or bit 2 (PWM1 output enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. When one PWM output is enabled and that the other PWM output is enabled, PWM output which is enabled to output later starts pulse output from halfway. When the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as ports P50 and P51 . Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If PWM count source is f(XIN) and the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1)/f(XIN) = 51 ✕ (n+1) µs (when f(XIN) = 5 MHz) Output pulse “H” period = PWM period ✕ m/255 = 0.2 ✕ (n+1) ✕ m µs (when f(XIN) = 5 MHz) 51 ✕ m ✕ (n+1) 255 µs PWM output T = [51 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when f(X IN ) = 5 MHz) Fig. 31 Timing of PWM cycle Data bus PWM prescaler pre-latch PWM register pre-latch PWM1 enable bit Transfer control circuit PWM prescaler latch PWM register latch Port P51 Count source selection bit “0” PWM prescaler XIN 1/2 PWM circuit Port P50 “1” PWM0 enable bit Fig. 32 Block diagram of PWM function 34 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b0 b7 PWM control register (PWMCON : address 002B16) Count source selection bit 0 : f(XIN) 1 : f(XIN)/2 PWM0 function enable bit 0 : PWM0 disabled 1 : PWM0 enabled PWM1 function enable bit 0 : PWM1 disabled 1 : PWM1 enabled Not used (return “0” when read) Fig. 33 Structure of PWM control register A PWM (internal) C B B = C T2 T stop stop T T T2 Port PWM 0 output PWM 1 output Port Port Port PWM register write signal (Changes from “A” to “B” during “H” period) PWM prescaler write signal (Changes from “T” to “T2” during PWM period) PWM 0 function enable bit PWM 1 function enable bit When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 34 PWM output timing when PWM register or PWM prescaler is changed 35 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003216, 003316 b7 b0 A-D control register (ADCON : address 003116) Analog input pin selection bits 0 0 0 : P60/SIN2/AN0 0 0 1 : P61/SOUT2/AN1 0 1 0 : P62/SCLK21/AN2 0 1 1 : P63/SCLK22/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : OFF 1 : ON AD external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Interrupt source selection bit 0 : Interrupt request at A-D conversion completed 1 : Interrupt request at ADT input rising or falling Reference voltage input selection bit 0 : VREF 1 : P56/DA1 The A-D conversion registers are read-only registers that contain the result of an A-D conversion. During A-D conversion, do not read these registers. [A-D Control Register (ADCON)] 003116 The A-D control register controls the A-D conversion process. Bits 0 to 2 are analog input pin selection bits. Bit 3 is an A-D conversion completion bit and “0” during A-D conversion, then changes to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to “1”, A-D conversion is star ted even by a rising edge or falling edge of an ADT input. Set ports which share with ADT pin to input when using an A-D external trigger. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AVSS and VREF, and outputs the divided voltages. •8-bit read (Read only address 003216.) b7 [Channel Selector] A-D conversion register (low-order) (ADL: Address 003216) The channel selector selects one of the input ports P6 7/AN7–P6 0/ AN 0, and inputs it to the comparator. •10-bit read (Read address 003316 first.) b7 A-D conversion register (high-order) (ADH: Address 003316) [Comparator and Control Circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500 kHz during A-D conversion. Use a clock divided the main clock XIN as the internal clock φ. b0 b9 b8 b7 b6 b5 b4 b3 b2 b0 b9 b8 b0 b7 A-D conversion register (low-order) (ADL: Address 003216) b7 b6 b5 b4 b3 b2 b1 b0 Note: High-order 6 bits of address 003316 becomes “0” at reading. Fig. 35 Structure of A-D control register Data bus b0 b7 A-D control register P40/ADT 3 A-D control register P61/SOUT2/AN1 P62/SCLK21 /AN2 P63/SCLK22 /AN3 P64/AN4 P65/AN5 P66/AN6 Channel selector P60/SIN2/AN0 ADT/A-D interrupt request (H) Comparater A-D conversion register (L) A-D conversion register 10 Resistor ladder P67/AN7 AVSS VREF P56/DA 1 Fig. 36 A-D converter block diagram 36 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A CONVERTER The 7513 group has an on-chip D-A converter with 8-bit resolution and 2 channels (DAi (i=1, 2)). The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from DAi pin. When using the D-A converter, the corresponding port direction register bit (P56 /DA1 , P57 /DA 2) should be set to “0” (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: b7 b0 D-A control register (DACON : address 0036 16) DA1 output enable bit/DA 1 V REF ON/OFF switch DA2 output enable bit/DA 2 V REF ON/OFF switch Not used (return “0” when read) V=VREF ✕ n/256 (n=0 to 255) Where V REF is the reference voltage. 0 : Output disabled/OFF 1 : Output enabled/ON At reset, the D-A conversion registers are cleared to “0016”, the DAi output enable bits are cleared to “0”, and DAi pin goes to high impedance state. The DA output is not buffered, so connect an external buffer when driving a low-impedance load. Fig. 37 Structure of D-A control register Data bus D-A1 conversion register (DA1: address 003416) D-A2 conversion register (DA2: address 003516) D-A i conversion register (8) DA i output enable bit R-2R resistor ladder P56/DA1 P57/DA2 Fig. 38 Block diagram of D-A converter VREF Internal: D-A output External: V REF Reference voltage input select switch Resistor ladder VREF input ON/OFF switch D-A1 output (P56) A-D conversion register (10 bits) D-A1 output enable switch D-A1 VREF ON/OFF switch R-2R resistor ladder D-A1 conversion register (8 bits) D-A2 output enable switch D-A2 V REF ON/OFF switch D-A2 output R-2R resistor ladder D-A2 conversion register (8 bits) (P5 7) Fig. 39 A-D converter, D-A converter block diagram 37 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD DRIVE CONTROL CIRCUIT The 7513 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. ●LCD display RAM ●Segment output enable register ●LCD mode register ●Voltage multiplier ●Selector ●Timing controller ●Common driver ●Segment driver ●Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. b7 Up to 160 pixels can be controlled for LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 9 Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits b0 Segment output enable register (SEG : address 0038 16) Segment output enable bit 0 0 : Output ports P3 0 –P35 1 : Segment output SEG 18–SEG23 Segment output enable bit 1 0 : Output ports P3 6 , P37 1 : Segment output SEG 24,SEG25 Segment output enable bit 2 0 : I/O ports P0 0–P05 1 : Segment output SEG 26–SEG31 Segment output enable bit 3 0 : I/O ports P0 6,P07 1 : Segment output SEG 32,SEG33 Segment output enable bit 4 0 : I/O port P1 0 1 : Segment output SEG 34 Segment output enable bit 5 0 : I/O ports P1 1–P15 1 : Segment output SEG 35–SEG39 LCD output enable bit 0 : Disable 1 : Enable Not used (return “0” when read) (Do not write “1” to this bit) b7 b0 LCD mode register (LM : address 0039 16) Duty ratio selection bits 0 0 : Not used 0 1 : 2 duty (use COM 0 , COM1 ) 1 0 : 3 duty (use COM 0 –COM2 ) 1 1 : 4 duty (use COM 0 –COM3 ) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disabled 1 : Voltage multiplier enabled LCD circuit divider division ratio selection bits 0 0 : 1 division of clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(XCIN )/32 1 : f(XIN )/8192 (f(X CIN)/8192 in low-speed mode) Note : LCDCK is a clock for a LCD timing controller. Fig. 40 Structure of LCD mode register 38 Level shift Level shift SEG0 SEG1 SEG2 SEG3 Segment Segment Segment Segment driver driver driver driver Level shift P30/SEG18 Level shift VCC VSS VL1 VL2 VL3 C1 C2 Level Shift Level Shift Level Shift COM0 COM1 COM2 COM3 Common Common Common Common driver driver driver driver Level Shift 2 Timing controller 2 LCD circuit divider division ratio selection bits Duty ratio selection bits LCD enable bit LCD output enable bit Bias control bit Bias control Voltage multiplier control bit LCD display RAM P14/SEG38 P15/SEG39 Segment Segment driver driver Level shift Selector Selector Selector Selector Selector Selector Level shift Address 005316 Address 004116 Address 004016 Data bus LCDCK LCD divider “1” f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) LCDCK count source selection bit “0” f(XCIN)/32 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 41 Block diagram of LCD controller/driver 39 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Voltage Multiplier (3 Times) Bias Control and Applied Voltage to LCD Power Input Pins The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin VL1. (However, when using a 1/2 bias, connect VL1 and V L2 and apply voltage by external resistor division.) Set each bit of the segment output enable register and the LCD mode register in the following order for operating the voltage multiplier. 1. Set the segment output enable bits (bits 0 to 5) of the segment output enable register to “0” or “1.” 2. Set the duty ratio selection bits (bits 0 and 1), the bias control bit (bit 2), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register to “0” or “1.” 3. Set the LCD output enable bit (bit 6) of the segment output enable register to “1.” 4. Set the voltage multiplier control bit (bit 4) of the LCD mode register to “1.” When voltage is input to the V L1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. When using the voltage multiplier, apply 1.3 V ≤ Voltage ≤ 2.3 V to the VL1 pin. When not using the voltage multiplier,apply proper voltage to the LCD power input pins (VL1 –VL3 ). Then set the LCD output enable bit to “1.” When the LCD output enable bit is set to “0,” the V CC voltage is applied to the VL3 pin inside of this microcomputer. The voltage multiplier control bit (bit 4 of the LCD mode register) controls the voltage multiplier. To the LCD power input pins (V L1 –VL3 ), apply the voltage shown in Table 10 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 10 Bias control and applied voltage to VL1–VL3 Bias value Voltage value 1/3 bias VL3 =VLCD VL2 =2/3 V LCD VL1 =1/3 V LCD 1/2 bias VL3 =VLCD VL2 =VL1 =1/2 VLCD Note: V LCD is the maximum value of supplied voltage for the LCD panel. Contrast control Contrast control VCC VL3 VCC VL3 VL3 R4 R1 VL2 VL2 C2 C2 VL2 Open C2 Open C1 Open R2 C1 C1 VL1 VL1 Open VL1 R5 R3 PXX R4=R5 R1=R2=R3 1/3 bias when using the voltage multiplier 1/3 bias when not using the voltage multiplier 1/2 bias Fig. 42 Example of circuit at each bias 40 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Common Pin and Duty Ratio Control ment/output port pins are the high impedance condition. The segment/I/O port pins(SEG26–SEG 33). are set to input ports, and the high impedance condition.The segment/I/O port pins(SEG 34– SEG39 ). are set to input ports, and VCC (=VL3 ) is applied to them by pull-up resistor. The common pins (COM 0–COM 3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). When releasing from reset, the V CC (VL3) voltage is output from the common pins. LCD Display RAM Address 004016 to 005316 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. Table 11 Duty ratio control and common pins used Duty ratio Duty ratio selection bit Common pins used Bit 1 Bit 0 2 0 1 COM0, COM1 (Note 1) 3 1 COM0–COM2 (Note 2) 4 1 0 1 LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; COM0–COM3 Notes1: COM2 and COM3 are open. 2: COM3 is open. f(LCDCK) = Segment Signal Output Pin (frequency of count source for LCDCK) (divider division ratio for LCD) Frame frequency = Segment signal output pins are classified into the segment-only pins (SEG 0 –SEG 17 ), the segment/output port pins (SEG 18– SEG25 ), and the segment/I/O port pins (SEG26 –SEG39 ). Segment signals are output according to the bit data of the LCD RAM corresponding to the duty ratio. After reset release, a VCC (=V L3) voltage is output to the segment-only pins and the seg- f(LCDCK) (duty ratio) Bit 7 6 5 4 3 2 1 0 address 004016 SEG1 SEG0 004116 SEG3 SEG2 004216 SEG5 SEG4 004316 SEG7 SEG6 004416 SEG9 SEG8 004516 SEG11 SEG10 004616 SEG13 SEG12 004716 SEG15 SEG14 004816 SEG17 SEG16 004916 SEG19 SEG18 004A16 SEG21 SEG20 004B16 SEG23 SEG22 004C16 SEG25 SEG24 004D16 SEG27 SEG26 004E16 SEG29 SEG28 004F16 SEG31 SEG30 005016 SEG33 SEG32 005116 SEG35 SEG34 005216 SEG37 SEG36 005316 SEG39 SEG38 COM3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 Fig. 43 LCD display RAM map 41 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 VL3 VSS SEG0 OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2=VL1 VSS COM0 COM1 COM2 VL3 VSS SEG0 ON COM0 OFF COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2=VL1 VSS COM0 COM1 VL3 VSS SEG0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 44 LCD drive waveform (1/2 bias) 42 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2 VL1 VSS COM0 COM1 COM2 COM3 VL3 SEG0 VSS OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2 VL1 VSS COM0 COM1 COM2 VL3 SEG0 VSS ON OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2 VL1 VSS COM0 COM1 VL3 SEG0 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 45 LCD drive waveform (1/3 bias) 43 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 6bit watchdog timer H. At reset or writing to the watchdog timer control register (address 0037 16), the watchdog timer is set to “3FFF16 .” When any data is not written to the watchdog timer control register (address 003716 ) after reset, the watchdog timer is in stop state. The watchdog timer starts to count down from “3FFF16 ” by writing an optional value into the watchdog timer control register (address 0037 16) and an internal reset occurs at an underflow. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0037 16) may be started before an underflow. The watchdog timer does not function when an optional value has not been written to the watchdog timer control register (address 003716 ). When address 0037 16 is read, the following values are read: “1” Internal system clock selection bit “0” Watchdog timer L (8) 1/16 When bit 6 of the watchdog timer control register (address 003716 ) is set to “0,” the STP instruction is valid. The STP instruction is disabled by rewriting this bit to “1.” At this time, if the STP instruction is executed, it is processed as an undefined instruction, so that a reset occurs inside. This bit cannot be rewritten to “0” by programming. This bit is “0” immediately after reset. The count source of the watchdog timer becomes the system clock φ divided by 8. The detection time in this case is set to 8.19 s at f(XCIN) = 32 kHz and 65.536 ms at f(X IN) = 4 MHz. However, count source of high-order 6-bit timer can be connected to a signal divided system clock by 8 directly by writing the bit 7 of the watchdog timer control register (address 003716) to “1.” The detection time in this case is set to 32 ms at f(XCIN) = 32 kHz and 256 µs at f(X IN) = 4 MHz. There is no difference in the detection time between the middle-speed mode and the high-speed mode. Data bus “FF16” is set when watchdog timer is written to. XCIN ●value of high-order 6-bit counter ●value of STP instruction disable bit ●value of count source selection bit. Watchdog timer count source selection bit “0” “1” Watchdog timer H (6) “3F16” is set when watchdog timer is written to. XIN Undefined instruction Reset STP instruction disable bit STP instruction RESETIN Reset circuit Internal reset Reset release time wait Fig. 46 Block diagram of watchdog timer b7 b0 Watchdog timer register (address 003716) WDTCON Watchdog timer H (for read-out of high-order 6 bit) “3FFF16” is set to the watchdog timer by writing values to this address. STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selecion bit 0 : Internal system clock/2048 (f(XIN)/4096) 1 : Internal system clock/8 (f(XIN)/16) Fig. 47 Structure of watchdog timer control register f(XIN) Internal reset signal Watchdog timer detection ≅ 2 ms (f(XIN) = 4 MHZ) Fig. 48 Timing of reset output 44 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TOUT/φ CLOCK OUTPUT FUNCTION The internal system clock φ or timer 2 divided by 2 (TOUT output) can be output from port P43 by setting the TOUT/φ output control bit (bit 1) of the timer 123 mode register and the TOUT/φ output control register. Set bit 3 of the port P4 direction register to “1” when outputting the clock. b7 b0 TOUT /φ output control register (CKOUT : address 002A 16) TOUT /φ output control bit 0 : φ clock output 1 : TOUT output Not used (return “0” when read) b7 b0 Timer 123 mode register (T123M : address 0029 16) TOUT output active edge switch bit 0 : Start on “H” output 1 : Start on “L” output TOUT /φ output control bit 0 : TOUT /φ output disable 1 : TOUT /φ output enable Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode ✽) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode ✽) Timer 1 count source selection bit 0 : f(XIN )/16 (or f(XCIN )/16 in low-speed mode ✽) 1 : f(XCIN ) Not used (return “0” when read) ✽ : Internal clock φ is f(X CIN)/2 in low-speed mode. Fig. 49 Structure of TOUT/f output-related register 45 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT Poweron To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between VCC(min.) and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.2 V CC for V CC of VCC (min.). RESET VCC (Note) Power source voltage 0V Reset input voltage 0V 0.2VCC Note : Reset release voltage ; VCC=VCC(min.) RESET VCC Power source voltage detection circuit Fig. 50 Reset Circuit Example XIN φ RESET Internal reset Reset address from vector table Address ? ? ? Data ? FFFC ADL FFFD ADH, ADL ADH SYNC XIN : about 8200 cycles Notes 1: The frequency relation of f(X IN) and f(φ) is f(XIN) = 8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 51 Reset Sequence 46 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Address Register contents Register contents (1) Port P0 direction register 000116 0016 (28) A-D control register 003116 0816 (2) Port P1 direction register 000316 0016 003216 XX16 (3) Port P2 direction register 000516 0016 003316 XX16 (4) Port P3 output control register 000716 0016 (29) A-D conversion register (low-order) (30) A-D conversion register (high-order) (31) D-A1 conversion register 003416 0016 (5) Port P4 direction register 000916 0016 (32) D-A2 conversion register 003516 0016 (6) Port P5 direction register 000B16 0016 (33) D-A control register 003616 0016 (7) Port P6 direction register 000D16 0016 (34) Watchdog timer control register 003716 0 0 1 1 1 1 1 1 (8) Port P7 direction register 000F16 0016 (35) Segment output enable register 003816 0016 (9) Key input control register 001516 0016 (36) LCD mode register 003916 0016 (10) PULL register A 001616 3F16 (37) Interrupt edge selection register 003A16 0016 (11) PULL register B 001716 0016 (38) CPU mode register 003B16 0 1 0 0 1 0 0 0 (12) Serial I/O1 status register 001916 1 0 0 0 0 0 0 0 (39) Interrupt request register 1 003C16 0016 (13) Serial I/O1 control register 001A16 (40) Interrupt request register 2 003D16 0016 (14) UART control register 001B16 1 1 1 0 0 0 0 0 (41) Interrupt control register 1 003E16 0016 (15) Serial I/O2 control register 001D16 0016 (42) Interrupt control register 2 003F16 0016 (16) Timer X (low-order) 002016 FF16 (43) Processor status register (17) Timer X (high-order) 002116 FF16 (44) Program counter (18) Timer Y (low-order) 002216 FF16 (19) Timer Y (high-order) 002316 FF16 (45) Watchdog timer (high-order) 3F16 (20) Timer 1 002416 FF16 (46) Watchdog timer (low-order) FF16 (21) Timer 2 002516 0116 (22) Timer 3 002616 FF16 (23) Timer X mode register 002716 0016 (24) Timer Y mode register 002816 0016 (25) Timer 123 mode register 002916 0016 (26) TOUT/φ output control register 002A16 0016 (27) PWM control register 002B16 0016 0016 (PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕ (PCH) Contents of address FFFD 16 (PCL) Contents of address FFFC 16 Note: The contents of all other register and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined Fig. 52 Initial status at reset 47 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 7513 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and X COUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-X COUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins go to high impedance state. Oscillation Control (1) Stop Mode Frequency Control (1) Middle-speed Mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and X IN and X CIN oscillators stop. The value set to the timer latch 1 and the timer latch 2 is loaded automatically to the timer 1 and the timer 2. Thus, a value generated time for stabilizing oscillation should be set to the timer 1 latch and the timer 2 latch (low-order 8 bits for the timer 1, high-order 8 bits for the timer 2) before executing the STP instruction. Either X IN or X CIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0,” Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows timer for the clock circuit oscillation to stabilize. The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. (2) Wait Mode (2) High-speed Mode The internal clock φ is half the frequency of XIN. (3) Low-speed Mode ●The internal clock φ is half the frequency of XCIN. ●A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock X IN is restarted, set enough time for oscillation to stabilize by programming. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and X CIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency on condition that f(XIN)>3f(XCIN ). If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. XCOUT XCIN Rf XIN XOUT Rd CIN CCOUT CCIN COUT Fig. 53 Ceramic resonator circuit XCIN Rf CCIN XCOUT XIN XOUT Open Rd CCOUT External oscillation circuit VCC VSS Fig. 54 External clock input circuit 48 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT XIN Internal system clock selection bit (Note) Low-speed mode “0” 1/2 1/2 1/4 “1” Middle-/High-speed mode XOUT Timer 1 count source selection bit Timer 2 count source selection bit “1” Timer 1 “0” “0” Timer 2 “1” Main clock division ratio selection bit Middle-speed mode “1” Main clock stop bit Q S S STP instruction R Timing φ (Internal clock) “0” High-speed mode or Low-speed mode WIT instruction Q R Q S R STP instruction Reset Interrupt disable flag I Interrupt request Note: When selecting the XC oscillation, set the port XC switch bit to “1” . Fig. 55 Clock generating circuit block diagram 49 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset “0” ” “0 CM6 “1” “0” CM7=0(8MHz selected) CM6=0(High-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating) CM6 “1” “0” CM7=1(32kHz selected) CM6=0(High-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating) ” “0 CM6 “1” “0” CM5 “1” ” “1 C “1 M5 C ” “1 M6 ” “0 ” “0” 5 CM7=1(32kHz selected) CM6=1(Middle-speed) CM5=1(8MHz stopped) CM4=1(32kHz oscillating) Low-speed mode (f(φ) =16 kHz) C ” M “0 6 C ” M1 “ Low-power dissipation mode (f(φ) =16 kHz) “0 ” CM7 “1” “0” “0” High-speed mode (f(φ) =4 MHz) CM7 “1” Low-speed mode (f(φ) =16 kHz) CM7=1(32kHz selected) CM6=1(Middle-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating) CM5 “1” CM4 “1” ” “1 C “1 M4 C ” “1 M6 ” “0 ” “0” CM7=0(8MHz selected) CM6=0(High-speed) CM5=0(8MHz oscillating) CM4=0(32kHz stoped) 4 CM4 “1” High-speed mode (f(φ) =4 MHz) “0” C ” M “0 6 C ” M1 “ Middle-spe ed mode (f(φ) =1 MHz) CM7=0(8MHz selected) CM6=1(Middle-speed) CM5=0(8MHz oscillating) CM4=1(32kHz oscillating) CM6 “1” “0 ” Middle-spe ed mode (f(φ) =1 MHz) CM7=0(8MHz selected) CM6=1(Middle-speed) CM5=0(8MHz oscillating) CM4=0(32kHz stoped) Low-power dissipation mode (f(φ) =16 kHz) “0” CM7=1(32kHz selected) CM6=0(High-speed) CM5=1(8MHz stopped) CM4=1(32kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Sub-clock (XCIN–XCOUT) stop bit 0: Stopped 1: Oscillating CM5 : Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : T he all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : T imer and LCD operate in the wait mode. 4 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in middle-/high-speed mode. 5 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode. 7 : T he example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 56 State transitions of system clock 50 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupt The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1). Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. In serial I/O2, the SOUT2 pin goes to high impedance state after transmission is completed. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN ) is at least 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency. Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. 51 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) or in one floppy disk The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 12 Special programming adapter Package Name of Programming Adapter 100PFB-A PCA4738H-100A 100P6Q-A PCA4738G-100A 100D0 PCA4738L-100A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 57 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 57 Programming and testing of One Time PROM version 52 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Table 13 Absolute maximum ratings Symbol VCC VI Parameter Conditions VI VI VI VI VI VI VI VO Power source voltage Input voltage P00–P07, P10–P17 , P20–P27, P41–P47, P50–P57 , P60–P67 Input voltage P40, P71–P77 Input voltage P70 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1 , C2 Input voltage RESET, XIN Output voltage C 1, C2 All voltages are based on V SS. Output transistors are cut off. VO Output voltage P00 –P07 , P10–P15, P30 –P37 At output port At segment output VO VO VO VO VO Pd Topr Tstg Output voltage P16, P1 7, P20–P27, P4 1–P47, P50–P57 , P60–P67 Output voltage P40 , P71–P77 Output voltage VL3 , SEG0–SEG 17,COM 0–COM3 Output voltage VL2 Output voltage XOUT Ta = 25°C Power dissipation Operating temperature Ratings –0.3 to 7.0 Unit V –0.3 to V CC +0.3 V –0.3 to 7.0 –0.3 to V CC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 7.0 –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to 7.0 –0.3 to V CC –0.3 to VL3 V V V V V V V V V V –0.3 to V CC +0.3 V –0.3 to 7.0 –0.3 to 7.0 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 V V V V mW °C °C RECOMMENDED OPERATING CONDITIONS Table 14 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter High-speed mode f(X IN) = 8 MHz Middle-speed mode f(XIN) = 8 MHz Low-speed mode VCC Power source voltage VSS VREF AVSS VIA Power source voltage A-D, D-A conversion reference voltage Analog power source voltage Analog input voltage AN0–AN 7 “H” input voltage P00–P07 , P56, P6 1, “H” input voltage P20–P27 , P62, P6 3, “H” input voltage RESET “H” input voltage XIN “L” input voltage P00–P07 , P56, P6 1, “L” input voltage P20–P27 , P62, P6 3, “L” input voltage RESET “L” input voltage XIN VIH VIH VIH VIH VIL VIL VIL VIL Min. 4.0 2.2 2.2 Limits Typ. 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 AVSS VCC 0.7 V CC VCC V 0.8 VCC VCC V 0.8 V CC 0.8 V CC VCC VCC V V 0 0.3 VCC V 0 0.2 VCC V 0 0 0.2 VCC 0.2 VCC V V VCC+0.3 0 P10–P17, P40 , P43, P45 , P47, P50–P53 , P64–P67, P7 1–P77 P41, P42, P4 4, P46, P54 , P55, P57 , P60, P70 V V V V V 2.7 P10–P17, P40 , P43, P45 , P47, P50–P53 , P64–P67, P7 1–P77 P41, P42, P4 4, P46, P54 , P55, P57 , P60, P70 Unit 53 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 15 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter ΣI OH(peak) ΣI OH(peak) ΣI OL(peak) ΣI OL(peak) ΣI OL(peak) ΣI OH(avg) ΣI OH(avg) ΣI OL(avg) ΣI OL(avg) ΣI OL(avg) I OH(peak) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current “H” peak output current I OH(peak) “H” peak output current I OL(peak) “L” peak output current I OL(peak) “L” peak output current I OL(peak) I OH(avg) I OH(avg) I OL(avg) “L” peak output current “H” average output current “H” average output current “L” average output current I OL(avg) “L” average output current I OL(avg) “L” average output current P00–P07, P1 0–P17, P20–P27 , P30–P37 (Note 1) P41–P47, P5 0–P57, P60–P67 (Note 1) P00–P07, P1 0–P17, P20–P27 , P30–P37 (Note 1) P41–P47, P5 0–P57, P60–P67 (Note 1) P40, P71 –P77 (Note 1) P00–P07, P1 0–P17, P20–P27 , P30–P37 (Note 1) P41–P47, P5 0–P57, P60–P67 (Note 1) P00–P07, P1 0–P17, P20–P27 , P30–P37 (Note 1) P41–P47, P5 0–P57, P60–P67 (Note 1) P40, P71 –P77 (Note 1) P00–P07, P1 0–P15, P30–P37 (Note 2) P16, P17 , P20–P27, P41 –P47, P50–P57, P6 0–P67 (Note 2) P00–P07, P1 0–P15, P30–P37 (Note 2) P16, P17 , P20–P27, P41 –P47, P50–P57, P6 0–P67 (Note 2) P40, P71 –P77 (Note 2) P00–P07, P1 0–P15, P30–P37 (Note 3) P16, P17 , P20–P27, P41 –P47, P50–P57, P6 0–P67 P00–P07, P1 0–P15, P30–P37 (Note 3) P16, P17 , P20–P27, P41 –P47, P50–P57, P6 0–P67 (Note 3) P40, P71 –P77 (Note 3) Min. Limits Typ. Max. –20 –20 20 20 80 –10 –10 10 10 40 –1.0 Unit mA mA mA mA mA mA mA mA mA mA mA –5.0 mA 5.0 mA 10 mA 20 –0.5 –2.5 2.5 mA mA mA mA 5.0 mA 10 mA Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 54 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 16 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol f(CNTR 0) f(CNTR 1) Parameter Input frequency for timers X and Y (duty cycle 50%) f(XIN ) Main clock input oscillation frequency (Note 1) f(XCIN ) Sub-clock input oscillation frequency (Notes 1, 2) Test conditions (4.0 V ≤ V CC ≤ 5.5 V) (2.2 V ≤ V CC ≤ 4.0 V) High-speed mode (4.0 V ≤ V CC ≤ 5.5 V) High-speed mode (2.2 V ≤ V CC ≤ 4.0 V) Middle-speed mode Min. Limits Typ. Max. 4.0 Unit MHz (10✕VCC –4)/9 MHz 8.0 MHz (20✕VCC –8)/9 MHz 8.0 MHz 32.768 50 kHz Notes1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN )/3. 55 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 17 Electrical characteristics (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter VOH “H” output voltage P00–P07, P10–P15 , P30–P37 VOH “H” output voltage P16, P17, P20 –P27, P41–P47 , P50–P57, P60–P67 (Note 1) VOL VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– I IH I IH I IH I IL I IL I IL I IL I LEAK “L” output voltage P00–P07, P10–P15 , P30–P37 “L” output voltage P16, P17, P20 –P27, P41–P47 , P50–P57, P60–P67 “L” output voltage P40, P71–P77 Test conditions IOH = –1 mA IOH = –0.25 mA VCC = 2.2 V IOH = –5 mA IOH = –1.5 mA IOH = –1.25 mA VCC = 2.2 V IOL = 5 mA IOL = 1.5 mA IOL = 1.25 mA VCC = 2.2 V IOL = 10 mA IOL = 3.0 mA IOL = 2.5 mA VCC = 2.2 V I OL = 10 mA I OL = 5 mA VCC = 2.2 V Hysteresis INT0–INT2 , ADT, CNTR 0, CNTR1, P20 –P27 Hysteresis SCLK, RXD Hysteresis RESET “H” input current P00–P07, P10–P17 , P20–P27, P40 –P47, VI = VCC P50–P57, P60–P67 , P70–P77 “H” input current RESET VI = V CC “H” input current XIN VI = V CC VI = V SS Pull-ups “off” “L” input current VCC = 5 V, VI = VSS P10 –P17, P20–P27,P4 0–P47, Pull-ups “on” P50 –P57, P60–P67, P7 0–P77 VCC = 2.2 V, VI = VSS Pull-ups “on” “L” input current P00–P07,P7 0 “L” input current RESET VI = VSS “L” input current XIN VI = VSS VO = V CC Output transistors “off” Output load current P30–P37 VO = V SS Output transistors “off” Limits Min. VCC–2.0 Typ. Max. Unit V VCC–0.8 V VCC–2.0 VCC–0.5 V V VCC–0.8 V 2.0 0.5 V V 0.8 V 2.0 0.5 V V 0.8 V 0.5 V 0.3 V 0.5 V 0.5 0.5 V V 5.0 µA 5.0 µA µA –5.0 µA 4.0 –60.0 –120.0 –240.0 µA –5.0 –20.0 –40.0 µA –5.0 –5.0 µA µA µA –4.0 5.0 µA –5.0 µA 56 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 18 Electrical characteristics (VCC =2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VRAM Parameter RAM retention voltage Test conditions Min. 2.0 At clock stop mode • High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • Low-speed mode, VCC = 5 V, Ta ≤ 55°C I CC Power source current f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” VL1 Power source voltage I L1 Power source current (VL1) (Note) When using voltage multiplier VL1 = 1.8 V VL1 < 1.3 V Ta = 25 °C Limits Typ. Max. 5.5 Unit V 6.4 13 mA 1.6 3.2 mA 35 70 µA 20 40 µA 15.0 22.0 µA 4.5 9.0 µA 0.1 1.0 Ta = 85 °C µA 10.0 1.3 1.8 3.0 10.0 2.3 6.0 50.0 V µA Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”. 57 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 19 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted) Symbol – Parameter Test conditions Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 4 V VCC = VREF = 2.7 V (Note 2) t CONV Conversion time f(XIN) = 4 MHz RLADDER I VREF IIA Ladder resistor Reference power source input current Analog port input current VREF = 5 V – Min. Limits Typ. 30.5 50 35 150 0.5 Max. 10 ±2.5 ±4.0 31 (Note 1) 200 5.0 Unit Bits LSB LSB µs kΩ µA µA Notes1: When an internal trigger is used in middle-speed mode, it is 34 ms. 2: 4 MHz ≤ f(XIN) ≤ 5.1 MHz in high-speed mode. Table 20 D-A converter characteristics (VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted) Symbol – – t su RO I VREF Parameter Test conditions Min. Limits Typ. Resolution Absolute accuracy Setting time Output resistor Reference power source input current VCC = VREF = 5 V VCC = VREF = 2.7 V 1 (Note) 3 2.5 Max. 8 1.0 2.0 4 6.0 Unit Bits % % µs kΩ mA Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “00 16”, and excluding currents flowing through the A-D resistance ladder. 58 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 21 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t w(RESET) t c(X IN) t wH(XIN) t wL(XIN) t c(CNTR) t wH(CNTR) t wL(CNTR) t wH(INT) t wL(INT) t c(S CLK1) t wH(SCLK1) t wL(SCLK1) t su(RXD–SCLK1) t h(SCLK1 –RX D) t c(S CLK2) t wH(SCLK2) t wL (SCLK2 ) t su(SIN2–SCLK2) t h(SCLK2 –SIN2) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT2 input “H” pulse width INT0 to INT2 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 1000 400 400 200 200 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A 16 is “1”. Divide this value by four when bit 6 of address 001A 16 is “0”. Table 22 Timing requirements 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t w(RESET) t c(XIN) t wH(XIN) t wL(XIN) t c(CNTR) t wH(CNTR) t wL(CNTR) t wH(INT) t wL(INT) t c(SCLK1 ) t wH(SCLK1 ) t wL(SCLK1) t su(RXD–SCLK1) t h(SCLK1 –RX D) t c(S CLK2) t wH(SCLK2) t wL(SCLK2) tsu(S IN2–S CLK2) t h(SCLK2 –SIN2 ) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT2 input “H” pulse width INT0 to INT2 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time Limits Min. Typ. 2 125 45 40 900/(V CC–0.4) t c(CNTR)/2–20 t c(CNTR)/2–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A 16 is “1”. Divide this value by four when bit 6 of address 001A 16 is “0”. 59 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 23 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t wH(SCLK1) t wL(SCLK1) t d(SCLK1 –TX D) t v(S CLK1–TX D) t r(SCLK1 ) t f(SCLK1) t wH(SCLK2) t wL(SCLK2) t d(SCLK2–SOUT2 ) t v(SCLK2–S OUT2) t f(SCLK2) t r(CMOS) t f(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. tC (S CLK1)/2–30 tC (S CLK1)/2–30 Typ. Max. 140 –30 30 30 tC (SCLK2)/2–160 tC (SCLK2)/2–160 0.2 ✕ tC (S CLK2) 0 10 10 40 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and X COUT pins are excluded. Table 24 Switching characteristics 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol t wH(SCLK1) twL(S CLK1) t d(SCLK1 –TX D) t v(S CLK1–TX D) t r(SCLK1 ) t f(SCLK1) t wH(SCLK2) t wL(SCLK2) t d(SCLK2–SOUT2 ) t v(SCLK2–S OUT2) t f(SCLK2) t r(CMOS) t f(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Min. tC (S CLK1)/2–50 tC (S CLK1)/2–50 Limits Typ. Max. 350 –30 50 50 tC (SCLK2)/2–240 tC (SCLK2)/2–240 0.2 ✕ tC (S CLK2) 0 20 20 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and X COUT pins are excluded. 60 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Measurement output pin 1 kΩ 100 pF Measurement output pin CMOS output 100 pF N-channel open-drain output (Note) Note : When bit 4 of the UART control register (address 001B 16) is “1”. (N-channel open-drain output mode) Fig. 58 Circuit for measuring output switching characteristics 61 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER tC (CNTR) tWL (CNTR) tWH (CNTR) CNTR0, CNTR1 0.8VCC INT0–INT3 0.8VCC 0.2VCC tWL (INT) tWH (INT) 0.2VCC tW (RESET) RESET 0.8VCC 0.2VCC tC (XIN) tWL (XIN) tWH (XIN) 0.8VCC XIN tC (SCLK) tr tf SCLK 0.2VCC tWL (SCLK) tWH (SCLK) 0.8VCC 0.2VCC tsu (RXD-SCLK) th (SCLK-RXD) 0.8VCC 0.2VCC RX D td (SCLK-TXD) tv (SCLK-TXD) TXD Fig. 59 Timing diagram 62 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE MMP Plastic 100pin 14✕14mm body LQFP Weight(g) 0.63 JEDEC Code – Lead Material Cu Alloy MD b2 HD ME EIAJ Package Code LQFP100-P-1414-0.50 e 100P6Q-A D 76 100 l2 Recommended Mount Pad 75 1 Symbol E HE A A1 A2 b c D E e HD HE L L1 Lp 51 25 26 50 A L1 F A3 y M L Detail F 100PFB-A x y c x A1 b A3 A2 e b2 I2 MD ME Lp MMP EIAJ Package Code TQFP100-P-1212-0.40 Dimension in Millimeters Min Nom Max 1.7 – – 0.1 0.2 0 1.4 – – 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 – – 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.08 0.1 – – 0° 10° – – – 0.225 0.9 – – 14.4 – – 14.4 – – Plastic 100pin 12✕12mm body TQFP Weight(g) 0.37 Lead Material Cu Alloy MD e JEDEC Code – ME HD 100 b2 D 76 1 I2 Recommended Mount Pad 75 25 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 51 26 50 A L1 e F y b x M L Detail F Lp c A1 A3 A2 A3 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max – – 1.2 0.1 0.15 0.05 – – 1.0 0.13 0.18 0.23 0.105 0.125 0.175 11.9 12.0 12.1 11.9 12.0 12.1 – 0.4 – 13.8 14.0 14.2 13.8 14.0 14.2 0.4 0.5 0.6 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.07 – – 0.08 – 0° 10° – – 0.225 – – 1.0 12.4 – – – – 12.4 63 MITSUBISHI MICROCOMPUTERS 7513 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 100D0 Glass seal 100pin QFN EIAJ Package Code – JEDEC Code – Weight(g) 18.85±0.15 5.0MAX 21.0±0.13 3.5TYP 0.65TYP 0.45TYP 51 80 81 INDEX 0.35TYP 0.65TYP 12.35±0.15 1.075TYP 15.6±0.13 0.65TYP 50 31 100 30 1.075TYP 1 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • • © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective Feb. 2001. Specifications subject to change without notice. 64 REVISION HISTORY Rev. 7513 GROUP USER’S MANUAL Date Description Summary Page 1.0 1.1 02/02/01 02/06/01 4 First edition issued. Table 1: Function explanation of I/O port P0 and I/O port P1 is revised. (1/1)