CALOGIC CLM7660DY Dc-to-dc voltage converter Datasheet

DC-to-DC
Voltage Converter
CORPORATION
CLM7660
FEATURES
•
•
•
•
•
•
DESCRIPTION
Converts +5V Logic Supply to ±5 System
Wide Input Voltage Range . . . . . . . . . . . . . . 1.5V to 10V
Low Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . 500µA
Efficient Voltage Conversion . . . . . . . . . . . . . . . . . 99.9%
RS232 Negative Power Supply
Low Cost, Simple to Use
APPLICATIONS
•
•
•
•
A-to-D Converters
D-to-A Converters
Multiplexers
Operational Amplifiers
Calogic CLM7660 DC-to-DC converter will generate a negative
voltage from a positive source. The CLM7660 generates -5V
in +5V digital systems and with two external capacitors, the device
will convert a 1.5V to 10V input signal to a -1.5V to -10V level.
Applications include analog-to-digital converters, digital-to-analog
converters, operational amplifiers and multiplexers. Many of these
systems require negative supply voltages. The CLM7660 allows
+5V digital logic systems to incorporate these analog components
without an additional main power source. Lower part count, less real
estate, ease of use are just a few of the benefits of the CLM7660.
ORDERING INFORMATION
Part
Package
Temperature
CLM7660CP
CLM7660DY
8 Pin DIP
8 Pin SOIC
-40oC to +85oC
-40oC to +85oC
PIN CONFIGURATION AND BLOCK DIAGRAM
NC
1
CAP +
2
V+
8
7
OSC
CLM7660
GND
3
6
LOW
VOLTAGE (LV)
CAP –
4
5
VOUT
NC = NO INTERNAL CONNECTION
1K-17
V + CAP +
8
OSC
LV
7
RC
OSCILLATOR
÷2
2
VOLTAGELEVEL
TRANSLATOR
4
CAP –
6
5
VOUT
INTERNAL
VOLTAGE
REGULATOR
LOGIC
NETWORK
3
GND
1B-35
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V
LV and OSC Inputs
Voltage (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to (V++0.3V)
for V+ <5.5V
+
(V -5.5V) to (V++0.3V)
for V+ <5.5V
Current into LV (Note 1). . . . . . . . . . . . . . . 20µA for V+ >3.5V
Output Short Duration (VSUPPLY ≤ 5.5V) . . . . . . . . Continuous
Power Dissipation (Note 2)
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375mW
Operating Temperature Range
D Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300oC
Static-sensitive device. Unused devices must be stored in conductive material.
Protect devices from static discharge and static fields. Stresses above those
listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at
these or any other conditions above those indicated in the operation sections of
the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS V+ = 5V, TA = +25oC, COSC = 0, Test Circuit (Figure 1), unless otherwise indicated.
SYMBOL
+
PARAMETER
MIN
TYP
MAX
UNIT
TEST CONDITIONS
I
Supply Current
-
80
180
µA
RL = ∞
V+H1
Supply Voltage Range, High
3
-
6.5
V
0oC ≤ TA ≤ +70oC, RL = 10kΩ, LV Open
3
-
5
V
-55oC ≤ TA ≤ +125oC, 10kΩ, LV Open
V+L1
Supply Voltage Range, Low
(DX Out of Circuit)
1.5
-
3.5
V
Min ≤ TA ≤ Max, RL = 10kΩ, LV to GND
V+H2
Supply Voltage Range, High
(DX In Circuit)
3
-
10
V
Min ≤ TA ≤ Max, RL = 10kΩ, LV Open
V+L2
Supply Voltage Range, Low
(DX In Circuit)
1.5
-
3.5
V
Min ≤ TA ≤ Max, RL = 10kΩ, LV to GND
ROUT
Output Source Resistance
-
55
100
Ω
IOUT = 20mA, TA = 25oC
-
-
120
Ω
IOUT = 20mA, 0oC ≤ TA ≤ +70 oC (C Device)
-
-
300
Ω
V+ = 2V, IOUT = 3mA, LV to GND
0 oC ≤ TA ≤ +70oC
-
10
-
kHz
fOSC
Oscillator Frequency
PEF
Power Efficiency
95
98
-
%
RL = 5kΩ
VOUT EF
Voltage Conversion Efficiency
97
99.9
-
%
RL = ∞
ZOSC
Oscillator Impedance
-
1
-
MΩ
V+ = 2V
-
100
-
kΩ
V+ = 5V
NOTES:
1. Connecting any input terminal to voltages greater than C+ or less than GND may cause destructive latch-up. It is recommended that no inputs
from sources operating from external supplies be applied prior to "power up" of the CLM7660.
2. Derate linearly above 50oC by 5.5mW/ oC.
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION
CIRCUIT DESCRIPTION
The CLM7660 is an excellent voltage doubler, the device has
all the characteristic with the exception of two inexpensive
10µF polarized electrolytic external capacitors. Figure 3
demonstrates the most effective means of using the device as
a voltage doubler. Capacitor C1 is charged to a voltage, V+,
for the half cycle when switches S1 and S3 are closed. (Note
Switches S2 and S4 are open during this half cycle.) During
the second half of the operation, switches S2 and S4 are
closed, with S1 and S3 open, thereby shifting capacitor C1
negatively by V+ volts. Charge is then transferred from C1 to
C2, such that voltage on C2 is exactly V+, asumming ideal
switches and no load on C2.
The four switches in Figure 3 are MOS power switches, S1 is
a P-Channel device, S2, S3 and S4 are N-Channel devices.
The major challenge with this approach while integrating the
switches, the substrates of S3 and S4 must always remain
reversed-biased with respect to their sources, but not so
much as to degrade their ON-resistances. In addition, at
circuit start-up, and under short circuit conditions (VOUT=V+),
the output voltage must be sensed and the substrate bias
adjusted accordingly. Failure to accomplish this will result in
high power losses and probable device latch-up.
The above problem is eliminated in the CLM7660 by a logic
network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of S3 and S4
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the CLM7660 is an integral
part of the anti-latch-up circuitry. Its inherent voltage drop can
degrade operation at low voltages. To improve low-voltage
operation, the LV pin should be connected to GND, disabling
the regulator. For supply voltages greater than 3.5V, the LV
terminal must be left open to ensure latch-up proof operation
and prevent device damage.
When larger values of C1 and C2 are used, the CLM7660
approaches the above conditions for negative voltage
multiplication. Energy is lost only if the transfer of the charge
between capacitors if a change in voltage occurs. The energy
lost is defined by:
E=1/2C1 (V12-V22)
During the pump and transfer cycles V1 and V2 are the
voltages on C1. If the impedances of C1 and C2 are high at
the pump frequency (see Figure 3), compared to the value of
RL, there will be a substantial difference in voltages V1 and
V2. The most optimum selection would be to make C2 as
large as possible to eliminate output voltage ripple, and to
utilize a large value for C1 to achieve maximum efficiency of
operation.
OPERATIONAL RULES:
Never exceed maximum supply voltages.
Never connect LV terminal to GND for supply voltages over
3.5V.
Never short circuit the output to V+ supply voltages above
5.5V for extended periods; however, transient conditions
including start-up are acceptable.
For polarized capacitors, the + terminal of C1 must be
connected to pin 2 of the CLM7660 and the + terminal to of C2
must be connected to GND.
For high-voltage, elevated temperature applications add a
diode DX (reference Figure 1). The 1N914 diode is an
appropriate choice.
THEORETICAL POWER EFFICIENCY CONSIDERATIONS
In theory, a voltage multiplier can approach 100% efficiency if
certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON-resistance and
virtually no offset.
3. The impedances of the pump and reservoir capacitors are
negligible at the pump frequency.
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION
FIGURE 1. CLM7660 TEST CIRCUIT
FIGURE 2. CHIP TOPOGRAPHY
IS
C1
10µF
1
8
2
7
IL
CLM7660
+
3
6
4
5
GND
V+
(+5)
C+
C-
C OSC *
VOUT
RL
LV
D X**
VO
1K-11
+
C2
10µF
NOTES:
* For large values of COSC (>1000pf), the
values of C1 and C2 should be increased to 100µF.
** DX is required for supply voltages greater than 6.5V at
-55o ≤ TA ≤ +70oC. Refer to performance curves for
additional information.
DIE SIZE = 81.5 x 57.5 (mm)
FIGURE 3. IDEALIZED SWITCHED CAPACITOR
V+
S1
V8
OSC
1L-05
FIGURE 4. SIMPLE NEGATIVE CONVERTER
S2
V+
1
C1
2
C1
10µF
C2
GND
S3
S4
DX
8
VOUT *
7
CLM7660
+
3
6
4
5
+
C2
10µF
1K-05
V OUT = –VIN
*NOTES:
1. VOUT = -n V+ for 1.5V ≤ V+ ≤ 6.5V.
2. VOUT = -n (V+ –VFDX) for 6.5V ≤ V + ≤ 10V.
1K-12
FIGURE 5. PARALLELING DEVICES LOWERS OUTPUT IMPEDANCE
V+
1
8
2
7
1
6
2
8
CLM7660
C1
3
4
"1"
5
C1
DX
3
4
RL
7
CLM7660
6
"n"
DX
5
1K-06
+
C2
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION
FIGURE 6. INCREASED OUTPUT VOLTAGE BY CASCADING DEVICES
V+
1
8
2
7
1
8
CLM7660
+
10µF
3
4
6
"1"
2
7
CLM7660
+
5
10µF
3
DX
DX
6
4
5
"n"
VOUT *
10µF
+
*NOTES:
1. VOUT = -n V+ for 1.5V ≤ V+ ≤ 6.5V.
2. VOUT = -n (V+ –VFDX) for 6.5V ≤ V + ≤ 10V.
1K-07
FIGURE 7. EXTERNAL CLOCKING
FIGURE 8. LOWERING OSCILLATOR FREQUENCY
V+
1
V+
V+
8
1kΩ
2
7
CLM7660
+
10µF
3
6
4
5
1
8
2
7
C OSC
CMOS
GATE
CLM7660
+
DX
C1
VOUT
3
6
4
5
DX
VOUT
10µF
+
C2
+
1K-08
1K-09
FIGURE 9. POSITIVE VOLTAGE MULTIPLIER
FIGURE 10. COMBINED NEGATIVE CONVERTER
AND POSITIVE MULTIPLIER
V+
1
8
2
7
V+
1
D1
CLM7660
3
6
4
5
VOUT =
D2
8
2
(2V+ ) - (2VF )
VOUT
= –(V+– VF )
7
CLM7660
3
6
4
5
DX
D1
+
C3
+
+
C1
C2
+
1K-10
C1
+
C2
D2
VOUT =
(2V + ) – (2VF )
+
C4
1J-49
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION
FIGURE 11. POSITIVE VOLTAGE CONVERSION
FIGURE 13A. FIXED POWER SUPPLY OPERATION
OF CLM7106 A-D
VOUT = –V –
1
+5V
8
+
2
7
CLM7660
+
C1
10µF
10µF
1MΩ
3
6
4
5
V – INPUT
1J-50
CA1004
1
V
LCD
DRIVE
+
REF IN
REF LO
FIGURE 12. SPLITTING A SUPPLY IN HALF
CLM7106
3-1/2 DIGIT
A-D
V+
COM
IN HI
+
50µF
R L1
1
8
2
7
IN LO
8
2
VOUT =
+
V –V
2
–
+
CLM7660
50µF
1MΩ
3
6
4
5
10m F
36
35
32
31
VIN
30
V+
+
(–5V)
5
CLM7660
26
4
100k Ω
100k Ω
3
R L2
+
10m F
1K-02
+
50µF
V–
1K-01
FIGURE 13B. NEGATIVE POWER SUPPLY GENERATION FOR 3 1/2 DIGIT A-D
+
2
+5V
4
8
CLM7660
3
5
1
V+
+
26
V–
REF IN
REF LO
COM
LED
DRIVE
CLM7107A
3-1/2 DIGIT
A-D
IN HI
IN LO
COMMON ANODE
LED DISPLAY
36
35
32
31
VIN
30
GND
21
1K-03
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION
FIGURE 14. CLM7660 SUPPLIES -5V FOR CONVERTERS IN MICROPROCESSOR-CONTROLLED
DATA ACQUISITION SYSTEMS
10µF
+
+5V
2
4
8
V
100kΩ
+
ANALOG
INPUT
–
0.1µF
1µF
0.47µF
1µF
6502 µP BUS
+
+5V
CA1004
100kΩ
5
–5V
20kΩ
3
CLM7660
2
11
1
+
–
V
10µF
B1
REF IN
B2
3 ANALOG
COMMON
10
+ INPUT
9
– INPUT
7
REF CAP –
8
REF CAP+
4
INT OUT
B4
5
6
B8
OR
UR
POL
D5
STROBE
RUN/HOLD
AZ IN
D1
BUFF OUT
D2
100kΩ
D3
4-1/2 DIGIT
A-D=7135
DIGITAL
GND
24
D4
BUSY
CLOCK IN
13
2
14
3
15
4
16
5
27
6
28
7
23
8
12
9
26
40
25
39
20
19
18
17
21
DATA BUS
20
PA0
D0
PA3
..
..
..
PA4
D7
PA1
PA2
ADDRESS
BUS
PA5
CONTROL
BUS
PA6
..
PA7
RS0
CA1
RS3
CA2
CS1
CS2
ADDRESS
DECODER
NC
NC
PB0-PB7
NC
NC
SY6522
NC
22 CLOCK
INPUT
f = 120kHz
RESET
R/W
O2
IRQ
VSS
1
1K-04
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
CLM7660
CORPORATION
PERFORMANCE CURVES
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs OUTPUT CURRENT
0V
2V
–1V
–2V
–3V
5V
–4V
–5V
–6V
–7V
10V
–8V
–9V
–10V
10 20 30 40 50 60
OUTPUT CURRENT (mA)
100%
90%
@ 5V EFFICIENCY vs
OSCILLATOR FREQUENCY (5mA)
92
95
s
N v D)
A
TIO
MP NO LO
U
S
(
ON NCY
C
ER
UE
OW FREQ
VP
@ 5 ATOR
LL
SCI
300µA
200µA
O
100µA
7.4
70
12.6
1
5
10
OSCILLATOR FREQUENCY (kHz)
1K-13
1K-14
OUTPUT RESISTANCE
OUTPUT RESISTANCE
vs SUPPLY VOLTAGE
200Ω
100Ω
0
5V
INPUT VOLTAGE
10V
1K-15
CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025
Similar pages