MX29F800C T/B 8M-BIT [1024K x 8 / 512K x 16] SINGLE VOLTAGE 5V ONLY FLASH MEMORY FEATURES GENERAL FEATURES • Single Power Supply Operation - 4.5 to 5.5 volt for read, erase, and program operations • 1,048,576 x 8 / 524,288 x 16 switchable • Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector • Sector Structure - 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 15 • Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotected allows code changes in previously locked sectors • Latch-up protected to 100mA from -1V to Vcc + 1V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE • High Performance - Access time: 70ns - Byte/Word program time: 9us/11us (typical) - Erase time: 0.7s/sector, 8s/chip (typical) • Low Power Consumption - Low active read current: 40mA (maximum) at 5MHz - Low standby current: 1uA (typical) • Minimum 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode PACKAGE • 44-Pin SOP • 48-Pin TSOP • 48-Ball LFBGA (6x8mm) • All devices are RoHS Compliant • All non RoHS Compliant devices are not recommeded for new design in P/N:PM1493 REV. 1.2, JUL. 05, 2012 1 MX29F800C T/B PIN CONFIGURATIONS RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MX29F800CT/CB 44 SOP(500mil) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC 48 TSOP(TYPE I) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29F800C T/B P/N:PM1493 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 REV. 1.2, JUL. 05, 2012 2 MX29F800C T/B 48-Ball LFBGA (6x8mm) 6 A13 A12 A14 A15 A16 5 A9 A8 A10 A11 Q7 4 WE# RESET# NC NC Q5 BYTE# Q15/ A-1 GND Q14 Q13 Q6 Q12 VCC Q4 3 RY/ BY# NC A18 NC Q2 Q10 Q11 Q3 2 A7 A17 A6 A5 Q0 Q8 Q9 Q1 1 A3 A4 A2 A1 A0 CE# OE# GND A B C D E F G H PIN DESCRIPTION SYMBOL LOGIC SYMBOL PIN NAME A0~A18 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE# Chip Enable Input WE# Write Enable Input BYTE# RESET# 19 A0-A18 OE# Hardware Reset Pin/Sector Protect Unlock Output Enable Input RY/BY# Ready/Busy Output VCC Power Supply Pin (+5V) GND Ground Pin 16 or 8 CE# Word/Byte Selection input OE# Q0-Q15 (A-1) WE# RESET# BYTE# P/N:PM1493 RY/BY# REV. 1.2, JUL. 05, 2012 3 MX29F800C T/B BLOCK DIAGRAM CE# OE# WE# RESET# BYTE# CONTROL INPUT LOGIC PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER FLASH REGISTER ARRAY ARRAY Y-DECODER AND STATE X-DECODER ADDRESS A0-AM WRITE Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER AM: MSB address P/N:PM1493 REV. 1.2, JUL. 05, 2012 4 MX29F800C T/B Table 1. SECTOR STRUCTURE MX29F800CT TOP BOOT SECTOR ADDRESS TABLE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Sector Size Byte Mode 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 32Kbytes 8Kbytes 8Kbytes 16Kbytes Word Mode 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 16Kwords 4Kwords 4Kwords 8Kwords Address range Byte Mode (x8) 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-F7FFFh F8000h-F9FFFh FA000h-FBFFFh FC000h-FFFFFh Word Mode(x16) 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7BFFFh 7C000h-7CFFFh 7D000h-7DFFFh 7E000h-7FFFFh Sector Address A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X X X X X X X X X 0 1 1 1 A13 X X X X X X X X X X X X X X X X 0 0 1 A12 X X X X X X X X X X X X X X X X 0 1 X A13 0 1 1 X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X MX29F800CB BOTTOM BOOT SECTOR ADDRESS TABLE Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Sector Size Byte Mode 16Kbytes 8Kbytes 8Kbytes 32Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes Word Mode 8Kwords 4Kwords 4Kwords 16Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords Address range Byte Mode (x8) 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-FFFFFh Word Mode(x16) 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh Sector Address A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X X X X X X X X X Note: Address range is A18~A-1 in byte mode and A18~A0 in word mode. P/N:PM1493 REV. 1.2, JUL. 05, 2012 5 MX29F800C T/B Table 2. BUS OPERATION Mode Pins Read Silicon ID Manufacture Code Read Silicon ID Device Code Read Standby Output Disable Write Sector Protect Chip Unprotect Verify Sector Protect/Unprotect Reset CE# OE# WE# RESET# A0 A1 A6 A9 Q0 ~ Q15 C2H (Byte mode) 00C2H (Word mode) D6/58 (Byte mode) 22D6/2258(Word mode) DOUT HIGH Z HIGH Z DIN DIN DIN Code(4) HIGH Z L L H H L L X Vhv L L H H H L X Vhv L H L L L L L X L X H H H H L X H X H L L L H X H H H H Vhv Vhv H L A0 X X A0 L L L X A1 X X A1 H H H X A6 X X A6 L H L X A9 X X A9 X X Vhv X Notes: 1. Vhv is the very high voltage, 11.5V to 12.5V. 2. X means input high (Vih) or input low (Vil). 3. SA means sector address: A12~A18. 4. Code=00H/XX00H means unprotected. Code=01H/XX01H means protected. P/N:PM1493 REV. 1.2, JUL. 05, 2012 6 MX29F800C T/B REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array out. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped after a period of time no more than Treadyand the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND±0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory. P/N:PM1493 REV. 1.2, JUL. 05, 2012 7 MX29F800C T/B SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on these sectors. MX29F800C T/B provides one method for sector protection. Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details. This method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the algorithm for this method. CHIP UNPROTECT OPERATION MX29F800C T/B provides one method for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sector are unprotected when shipped from the factory. This method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for algorithm of the operation. TEMPORARY SECTOR UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected. AUTOMATIC SELECT OPERATION When the device is in Read array mode or erase-suspended read array mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE# and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. P/N:PM1493 REV. 1.2, JUL. 05, 2012 8 MX29F800C T/B VERIFY SECTOR PROTECT STATUS OPERATION MX29F800C T/B provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to A17 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is still not being protected. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29F800C T/B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1493 REV. 1.2, JUL. 05, 2012 9 MX29F800C T/B TABLE 3. MX29F800C T/B COMMAND DEFINITIONS Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Addr Data XXX F0 Data Manufacturer ID Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 X00 X00 00C2 C2 Automatic Select Device ID Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 X01 X02 ID ID Sector Protect Verify Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 (Sector)X02 (Sector)X04 XX00/XX01 00/01 Addr Data Addr Data Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Read Mode Reset Mode Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Program Word 555 AA 2AA 55 555 A0 Addr Data Byte AAA AA 555 55 AAA A0 Addr Data Chip Erase Word 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase Byte AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Word 555 AA 2AA 55 555 80 555 AA 2AA 55 Sector 30 Byte AAA AA 555 55 AAA 80 AAA AA 555 55 Sector 30 Erase Erase Suspend Resume Sector B0 Sector 30 Sector Protect Word XXX 60 sector 60 sector 40 sector 00/01 Byte XXX 60 sector 60 sector 40 sector 00/01 Notes: 1. Device ID: 22D6H/D6H for Top Boot Sector device. 2258H/58H for Bottom Boot Sector device. 2. For sector protect verify result, XX00H/00H means sector is not protected, XX01H/01H means sector has been protected. 3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus cyc is for protect verify. 4. It is not allowed to adopt any other code which is not in the above command definition table. P/N:PM1493 REV. 1.2, JUL. 05, 2012 10 MX29F800C T/B RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode or sector protect verify mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Manufacturer ID Device ID Sector Protect Verify Address Data (Hex) Representation Word X00 00C2 Byte X00 C2 Word X01 22D6/2258 Top/Bottom Boot Sector Byte X02 D6/58 Top/Bottom Boot Sector Word (Sector address) X 02 00/01 Unprotected/protected Byte (Sector address) X 04 00/01 Unprotected/protected There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1493 REV. 1.2, JUL. 05, 2012 11 MX29F800C T/B AUTOMATIC PROGRAMMING The MX29F800C T/B can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. With the internal write state controller, the device requires the user to write the program command and data only. The typical chip program time at room temperature of the MX29F800C T/B is 3 seconds. (Word-Mode) When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 RY/BY#*2 In progress*1 Q7# Toggling 0 0 Finished Q7 Stop toggling 0 1 Exceed time limit Q7# Toggling 1 0 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us and the device returns to read array state without programing the data in the protected sector. P/N:PM1493 REV. 1.2, JUL. 05, 2012 12 MX29F800C T/B CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q2 RY/BY# In progress 0 Toggling 0 Toggling 0 Finished 1 Stop toggling 0 1 1 Exceed time limit 0 Toggling 1 Toggling 0 SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 40us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 40us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2 Time-out period 0 Toggling 0 0 Toggling 0 In progress 0 Toggling 0 1 Toggling 0 Finished 1 Stop toggling 0 1 1 1 Exceed time limit 0 Toggling 1 1 Toggling 0 *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us and the device returned to read array status without erasing the data in the protected sector. P/N:PM1493 REV. 1.2, JUL. 05, 2012 13 MX29F800C T/B SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1(<=20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2 to judge the sector is erasing or the erase is suspended. Status Q7 Q6 Q5 Q3 Q2 RY/BY# 1 No toggle 0 N/A Toggle 1 Erase suspend read in non-erase suspended sector Data Data Data Data Data 1 Erase suspend program in non-erase suspended sector Q7# Toggle 0 N/A N/A 0 Erase suspend read in erase suspended sector When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, and erase resume. SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 400us interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. P/N:PM1493 REV. 1.2, JUL. 05, 2012 14 MX29F800C T/B ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias Storage Temperature Voltage Range -65°C to +125°C -65°C to +150°C VCC -0.5V to +7.0V RESET#, A9 -0.5V to +12.5V The other pins. -0.5V to VCC+0.7V Output Short Circuit Current (less than one second) 200 mA OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ) Industrial (I) Grade Surrounding Temperature VCC Supply Voltages VCC range (TA ) 0°C to +70°C -40°C to +85°C +4.5 V to 5.5 V P/N:PM1493 REV. 1.2, JUL. 05, 2012 15 MX29F800C T/B DC CHARACTERISTICS Symbol Description Min. Typ. Max. Remark Iilk Input Leak Iolk Output Leak 10uA Iilk9 A9 Leak 35uA A9: 12.5V Icr1 Read Current (10MHz) 50mA CE#=Vil, OE#=Vih Icr2 Read Current (5MHz) 40mA CE#=Vil, OE#=Vih 1mA Vcc=Vcc max, CE#=Vih other pin disable 50uA Vcc=Vccmax, CE#=vcc +0.3V, other pin disable 50mA CE#=Vil, OE#=Vih, WE#=Vil Isb1 ±1.0uA Standby Current (TTL) Isb2 Standby current (CMOS) Icw Write Current Vil Input Low Voltage -0.3V 0.8V Vih Input High Voltage 0.7xVcc Vcc+0.3V Vhv Very High Voltage for hardware Protect/ Unprotect/Auto Select/ Temporary Unprotect Vol Output Low Voltage Voh1 Ouput High Voltage (TTL) Voh2 Ouput High Voltage (CMOS) 1uA 11.5V 12V 12.5V 0.45V 2.4V Vcc-0.4V P/N:PM1493 Iol=2.1mA, Vcc=Vcc min Ioh1=-2mA Ioh2=-100uA REV. 1.2, JUL. 05, 2012 16 MX29F800C T/B SWITCHING TEST CIRCUITS Vcc 0.1uF R2 TESTED DEVICE CL R1 Vcc DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=2.7K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30PF for 70ns Rise/Fall Times : 10ns Input pulse levels: 0.45V/0.7xVcc Reference levels for measuring timing :0.8V, 2.0V SWITCHING TEST WAVEFORMS 0.7xVCC 2.0V 2.0V TEST POINTS 0.45V 0.8V 0.8V INPUT OUTPUT P/N:PM1493 REV. 1.2, JUL. 05, 2012 17 MX29F800C T/B AC CHARACTERISTICS Symbol Description Taa Tce Toe Tdf Toh Twc Tcwc Tas Tah Tds Tdh Tvcs Tcs Tch Toes Toeh Tcep Tceph Valid data output after address Valid data output after CE# low Valid data output after OE# low Data output floating after OE# high Output hold time from the earliest rising edge of Address, CE#, OE# Write period time Command write period time Address setup time Address hold time Data setup time Data hold time Vcc setup time CE# Setup time CE# hold time Output enable setup time Read Output enable hold time Toggle & Data# Polling CE# pulse width CE# pulse width high Speed Option -70 Min. Typ. Max. 70 70 30 20 Unit ns ns ns ns 0 ns 70 70 0 45 30 0 50 0 0 0 0 ns ns ns ns ns ns us ns ns ns ns 10 ns 35 20 ns ns Twp WE# pulse width 35 ns Twph WE# pulse width high 30 ns Tghwl Read recover time before write 0 ns Tbusy Program/Erase active time by RY/BY# Tavt Taetc Taetb Tbal Program operation Byte Word Chip Erase operation Sector Erase operation Sector address hold time P/N:PM1493 9 11 8 0.7 90 300 360 32 15 40 ns us us sec sec us REV. 1.2, JUL. 05, 2012 18 MX29F800C T/B Figure 1. COMMAND WRITE OPERATION Tcwc CE# Vih Vil Tch Tcs WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Data Vih Vil DIN VA: Valid Address P/N:PM1493 REV. 1.2, JUL. 05, 2012 19 MX29F800C T/B READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS CE# Tce Vih Vil Vih WE# OE# Vil Tdf Toe Vih Vil Toh Taa Trc Vih Addresses Outputs ADD Valid Vil Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1493 REV. 1.2, JUL. 05, 2012 20 MX29F800C T/B AC CHARACTERISTICS Item Description Setup Speed Unit Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns Trh RESET# High Time Before Read MIN 0 ns Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns Trb2 RY/BY# Recovery Time (to WE# go low) MIN 50 ns Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write MAX 20 us Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write MAX 500 ns Figure 3. RESET# TIMING WAVEFORM Trb1 CE#, OE# Trb2 WE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CE#, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1493 REV. 1.2, JUL. 05, 2012 21 MX29F800C T/B ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# Tch Taetc WE# Tcs OE# Last 2 Erase Command Cycle Twc Address 2AAh VA SA Tds Data Read Status Tah Tas Tdh VA In Progress Complete 55h 10h Tbusy Trb RY/BY# SA: 555h for chip erase P/N:PM1493 REV. 1.2, JUL. 05, 2012 22 MX29F800C T/B Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1493 REV. 1.2, JUL. 05, 2012 23 MX29F800C T/B Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status CE# Tch Taetb WE# Tcs OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Data Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h Tbusy 30h Trb RY/BY# P/N:PM1493 REV. 1.2, JUL. 05, 2012 24 MX29F800C T/B Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1493 REV. 1.2, JUL. 05, 2012 25 MX29F800C T/B Figure 8. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H Toggle Bit checking Q6 NO ERASE SUSPEND not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1493 REV. 1.2, JUL. 05, 2012 26 MX29F800C T/B Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS CE# Tch Tavt WE# Tcs OE# Last 2 Program Command Cycle Address 555h VA PA Tds Data Last 2 Read Status Cycle Tah Tas VA Tdh A0h Status PD Tbusy DOUT Trb RY/BY# P/N:PM1493 REV. 1.2, JUL. 05, 2012 27 MX29F800C T/B Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Tavt or Taetb Tcep CE# Tceph Tghwl OE# Tah Tas Address 555h Tds Data VA PA VA Tdh A0h Status PD DOUT Tbusy RY/BY# P/N:PM1493 REV. 1.2, JUL. 05, 2012 28 MX29F800C T/B Figure 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1493 REV. 1.2, JUL. 05, 2012 29 MX29F800C T/B SECTOR PROTECT/CHIP UNPROTECT Figure 12. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) 150uS: Sector Protect 15mS: Chip Unprotect 1us CE# WE# OE# Verification Data 60h SA, A6 A1, A0 60h 40h VA VA Status VA Vhv RESET# Vih VA: valid address P/N:PM1493 REV. 1.2, JUL. 05, 2012 30 MX29F800C T/B Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait 150us Reset PLSCNT=1 Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No Retry Count=25? No Data=01h? Yes Yes Device fail Protect another sector? Yes No Temporary Unprotect Mode RESET#=Vih Write RESET CMD Sector Protect Done P/N:PM1493 REV. 1.2, JUL. 05, 2012 31 MX29F800C T/B Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes All sectors protected? No Protect All Sectors Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms Write [A6,A1,A0]:[1,1,0] data: 40h Retry Count +1 Read [A6,A1,A0]:[1,1,0] No Retry Count=1000? No Data=00h? Yes Device fail Yes Temporary Unprotect Write reset CMD Chip Unprotect Done P/N:PM1493 REV. 1.2, JUL. 05, 2012 32 MX29F800C T/B Table 5. TEMPORARY SECTOR UNPROTECT Parameter Alt Description Condition Speed Unit Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us Figure 14. TEMPORARY SECTOR UNPROTECT WAVEFORMS Program or Erase Command Sequence CE# WE# Tvhhwl RY/BY# Vhv 12V RESET# 0 or 5V 0 or 5V Trpvhh Trpvhh P/N:PM1493 REV. 1.2, JUL. 05, 2012 33 MX29F800C T/B Figure 15. TEMPORARY SECTOR UNPROTECT FLOWCHART Start Apply RESET# pin Vhv Volt Enter Program or Erase Mode Mode Operation Completed (1) Remove Vhv Volt from RESET# (2) RESET# = Vih Completed Temporary Sector Unprotected Mode Notes: 1. Temporary unprotect all protected sectors Vhv=11.5 ~ 12.5V. 2. The protected conditions of the protected sectors are the same to temporary sector unprotect mode. P/N:PM1493 REV. 1.2, JUL. 05, 2012 34 MX29F800C T/B Figure 16. SILICON ID READ TIMING WAVEFORM CE# Vih Vil Tce Vih WE# Vil Toe Vih OE# Tdf Vil Toh Toh Vhv Vih A9 A0 Vil Vih Vil Taa A1 Taa Vih Vil ADD DATA Q0-Q7 Vih Vil Vih Vil DATA OUT DATA OUT C2H 23H (TOP boot) ABH (Bottom boot) P/N:PM1493 REV. 1.2, JUL. 05, 2012 35 MX29F800C T/B WRITE OPERATION STATUS Figure 17. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Complement Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1493 REV. 1.2, JUL. 05, 2012 36 MX29F800C T/B Figure 18. DATA# POLLING ALGORITHM Start Read Q7~Q0 at valid address (Note 1) Q7 = Data# ? No Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address Q7 = Data# ? (Note 2) No Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1493 REV. 1.2, JUL. 05, 2012 37 MX29F800C T/B Figure 19. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Tdf Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data Tbusy RY/BY# Notes: 1. VA : Valid Address 2. CE# must be toggled when toggle bit toggling. P/N:PM1493 REV. 1.2, JUL. 05, 2012 38 MX29F800C T/B Figure 20. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Twice (Note1) NO Q6 Toggle ? YES NO Q5 = 1? YES Read Q7~Q0 Twice (Note1, 2) NO Q6 Toggle ? YES Program/Erase fail Write Reset CMD Program/Erase Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1493 REV. 1.2, JUL. 05, 2012 39 MX29F800C T/B RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device powerup. If the timing in the figure is ignored, the device may not operate correctly. Vcc Vcc(min) GND Tvr Tvcs Tf CE# WE# Tce Vil Vih Vil Tf OE# WP#/ACC Symbol Tvr Tr Tf Tvcs Tr Vil Taa Vih Tr or Tf Valid Address Vil Voh DATA Toe Vih Tr or Tf ADDRESS Tr Vih High Z Valid Ouput Vol Vih Vil Figure A. AC Timing at Device Power-Up Parameter Vcc Rise Time Input Signal Rise Time Input Signal Fall Time Vcc setup time Min. 20 50 P/N:PM1493 Max. 500000 20 20 Unit us/V us/V us/V us REV. 1.2, JUL. 05, 2012 40 MX29F800C T/B ERASE AND PROGRAMMING PERFORMANCE Limits Typ. Max. Byte Programming Time 9 300 us Word Programming Time 11 360 us Sector Erase Time 0.7 8 sec 8 32 sec Byte Mode 10 27 sec Word Mode 7.5 17 sec Parameter Min. Chip Erase Time Chip Programming Time Erase/Program Cycles Note: Units 100,000 Cycles 1. Typical condition means 25°C, 5V. 2. Maximum condition means 85°C, 4.5V, 100K cycles. LATCH-UP CHARACTERISTICS Min. Max. Input Voltage voltage difference with GND on A9, Reset# pins -1.0V 12.5V Input Voltage voltage difference with GND on all normal pins inputs -1.0V Vcc + 1.0V -100mA +100mA Input current pulse Includes all pins except Vcc. Test conditions: Vcc = 5V, one pin per testing PIN CAPACITANCE Parameter Symbol Parameter Description CIN2 Control Pin Capacitance COUT Output Capacitance CIN Max. Unit VIN=0 12 pF VOUT=0 12 pF VIN=0 8 pF Test Set Input Capacitance P/N:PM1493 Typ. REV. 1.2, JUL. 05, 2012 41 MX29F800C T/B ORDERING INFORMATION Access Time (ns) Temperature Range Package MX29F800CTMI-70G 70 -40oC~85oC 44 Pin SOP MX29F800CBMI-70G 70 -40oC~85oC 44 Pin SOP MX29F800CTTI-70G 70 -40oC~85oC 48 Pin TSOP (Normal Type) MX29F800CBTI-70G 70 -40oC~85oC 48 Pin TSOP (Normal Type) MX29F800CTXEI-70G 70 -40oC~85oC 48 Ball LFBGA (6x8mm) MX29F800CBXEI-70G 70 -40oC~85oC 48 Ball LFBGA (6x8mm) Part No. P/N:PM1493 Remark RoHS Compliant RoHS Compliant RoHS Compliant RoHS Compliant RoHS Compliant RoHS Compliant REV. 1.2, JUL. 05, 2012 42 MX29F800C T/B PART NAME DESCRIPTION MX 29 F 800 C T T I 70 G OPTION: G: RoHS Compliant SPEED: 70:70ns TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M:SOP T: TSOP XE: LFBGA (6x8x1.3mm, Pitch 0.8mm, 0.4mm Ball) BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot REVISION: C DENSITY & MODE: 800: 8M, x8/x16 Boot Sector TYPE: F: 5V DEVICE: 29: Flash P/N:PM1493 REV. 1.2, JUL. 05, 2012 43 MX29F800C T/B PACKAGE INFORMATION P/N:PM1493 REV. 1.2, JUL. 05, 2012 44 MX29F800C T/B P/N:PM1493 REV. 1.2, JUL. 05, 2012 45 MX29F800C T/B P/N:PM1493 REV. 1.2, JUL. 05, 2012 46 MX29F800C T/B REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Removed 90ns grade at Order Information 3. Modified Tbal spec from 50us to 40us 4. Modified typical chip programming time 1.1 1. Added Tvcs, Toeh, Twp, Twph and Tghwl 2. Modified description wording for "RoHS Compliant" 1.2 1. Modified 48-ball LFBGA package type P/N:PM1493 Page Date P1 NOV/17/2009 P1,18,42,43 P13,17 P41 P18,19,40 NOV/21/2011 P1,42,43 P1,3,42,43 JUL/05/2012 REV. 1.2, JUL. 05, 2012 47 MX29F800C T/B Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2009~2012. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 48