MOTOROLA Order this document by MCM63P733A/D SEMICONDUCTOR TECHNICAL DATA Advance Information MCM63P733A 128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P733A is a 4M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 128K words of 32 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and Linear Burst Order (LBO) are clock (K) controlled through positive–edge–triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P733A (burst sequence operates in linear or interleaved mode dependent upon state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge–triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM63P733A operates from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible. TQ PACKAGE TQFP CASE 983A–01 • MCM63P733A–133 = 4 ns Access/7.5 ns Cycle (133 MHz) MCM63P733A–117 = 4.2 ns Access/8.5 ns Cycle (117 MHz) MCM63P733A–100 = 4.5 ns Access/10 ns Cycle (100 MHz) MCM63P733A–90 = 5 ns Access/11 ns Cycle (90 MHz) • 3.3 V + 10% / – 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply • ADSP, ADSC, and ADV Burst Control Pins • Selectable Burst Sequencing Order (Linear/Interleaved) • Internally Self–Timed Write Cycle • Byte Write and Global Write Control • Single–Cycle Deselect • Sleep Mode (ZZ) • 100–Pin TQFP Package PowerPC is a trademark of IBM Corp. This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 3/24/98 Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM63P733A 1 FUNCTIONAL BLOCK DIAGRAM LBO ADV K ADSC BURST COUNTER K2 2 17 128K x 32 ARRAY CLR ADSP 2 SA SA1 SA0 ADDRESS REGISTER 17 15 SGW SW SBa SBb WRITE REGISTER a 32 32 WRITE REGISTER b 4 SBc SBd G MCM63P733A 2 DATA–OUT REGISTER K WRITE REGISTER d K2 SE1 SE2 SE3 DATA–IN REGISTER WRITE REGISTER c ENABLE REGISTER K ENABLE REGISTER DQa – DQd MOTOROLA FAST SRAM SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA PIN ASSIGNMENT 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC MOTOROLA FAST SRAM MCM63P733A 3 PIN DESCRIPTIONS Pin Locations Symbol Type Description 85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 86 G Input Asynchronous Output Enable Input. 89 K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 31 LBO Input Linear Burst Order Input: This pin may be left floating; it will default as interleaved. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium). 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 15, 41, 65, 91 VDD Supply Core Power Supply. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 14, 16, 38, 39, 42, 43, 66 NC — (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 MCM63P733A 4 Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). No Connection: There is no connection to the chip. MOTOROLA FAST SRAM TRUTH TABLE (See Notes 1 through 5) Address Used SE1 SE2 SE3 ADSP ADSC ADV G3 DQx Write 2, 4 Deselect None 1 X X X 0 X X High–Z X Deselect None 0 X 1 0 X X X High–Z X Deselect None 0 0 X 0 X X X High–Z X Deselect None X X 1 1 0 X X High–Z X Deselect None X 0 X 1 0 X X High–Z X Begin Read External 0 1 0 0 X X X High–Z X Begin Read External 0 1 0 1 0 X X High–Z READ Continue Read Next X X X 1 1 0 1 High–Z READ Continue Read Next X X X 1 1 0 0 DQ READ Continue Read Next 1 X X X 1 0 1 High–Z READ Continue Read Next 1 X X X 1 0 0 DQ READ Suspend Read Current X X X 1 1 1 1 High–Z READ Suspend Read Current X X X 1 1 1 0 DQ READ Suspend Read Current 1 X X X 1 1 1 High–Z READ Suspend Read Current 1 X X X 1 1 0 DQ READ Begin Write Next Cycle External 0 1 0 1 0 X X High–Z WRITE Continue Write Next X X X 1 1 0 X High–Z WRITE Continue Write Next 1 X X X 1 0 X High–Z WRITE Suspend Write Current X X X 1 1 1 X High–Z WRITE Suspend Write Current 1 X X X 1 1 X High–Z WRITE NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low, or 2) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. ASYNCHRONOUS TRUTH TABLE Operation ZZ G I/O Status Read L L Data Out (DQx) Read L H High–Z Write L X High–Z Deselected L X High–Z Selected H X High–Z 4th Address (Internal) LINEAR BURST ADDRESS TABLE (LBO = VSS) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 MOTOROLA FAST SRAM MCM63P733A 5 INTERLEAVED BURST ADDRESS TABLE (LBO = VDD) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 WRITE TRUTH TABLE Cycle Type SGW SW SBa SBb SBc SBd Read H H X X X X Read H L H H H H Write Byte a H L L H H H Write Byte b H L H L H H Write Byte c H L H H L H Write Byte d H L H H H L Write All Bytes H L L L L L Write All Bytes L X X X X X ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Symbol Value Unit VDD – 0.5 to + 4.6 V VDDQ VSS – 0.5 to VDD V 2 Vin, Vout – 0.5 to VDD + 0.5 V 2 Input Voltage (Three–State I/O) VIT – 0.5 to VDDQ + 0.5 V 2 Output Current (per I/O) Iout ± 20 mA Package Power Dissipation PD 1.2 W Tbias – 10 to + 85 °C Tstg – 55 to + 125 °C Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Temperature Under Bias Storage Temperature Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. 3 NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady–state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics. PACKAGE THERMAL CHARACTERISTICS Rating Symbol Max Unit Notes RθJA 40 25 °C/W 1, 2 Junction to Board (Bottom) RθJB 17 °C/W 3 Junction to Case (Top) RθJC 9 °C/W 4 Junction to Ambient (@ 200 lfm) Single–Layer Board Four–Layer Board NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MCM63P733A 6 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply (Voltages Referenced to VSS = 0 V) Symbol Min Typ Max Unit VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 2.375 2.5 2.9 V Input Low Voltage VIL – 0.3 — 0.7 V Input High Voltage VIH 1.7 — VDD + 0.3 V Input High Voltage (I/O Pins) VIH2 1.7 — VDDQ + 0.3 V Output Low Voltage (IOL = 2 mA) VOL — — 0.7 V Output High Voltage (IOH = – 2 mA) VOH 1.7 — — V Max Unit Parameter Supply Voltage RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O Supply (Voltages Referenced to VSS = 0 V) Parameter Supply Voltage Symbol Min Typ VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 3.135 3.3 VDD V Input Low Voltage VIL – 0.5 — 0.8 V Input High Voltage VIH 2 — VDD + 0.5 V Input High Voltage (I/O Pins) VIH2 2 — VDDQ + 0.5 V Output Low Voltage (IOL = 8 mA) VOL — — 0.4 V Output High Voltage (IOH = – 4 mA) VOH 2.4 — — V VIH VSS VSS – 1.0 V 20% tKHKH (MIN) Figure 1. Undershoot Voltage MOTOROLA FAST SRAM MCM63P733A 7 SUPPLY CURRENTS Parameter Symbol Min Typ Max Unit Notes Input Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(I) — — ±1 µA 1, 2 Output Leakage Current (0 V ≤ Vin ≤ VDDQ) Ilkg(O) — — ±1 µA MCM63P733A–133 MCM63P733A–117 MCM63P733A–100 MCM63P733A–90 IDDA — — TBD mA 3, 4, 5 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels) ISB2 — — TBD mA 6, 8 IZZ — — 2 mA 2, 7, 8 TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at TTL Levels) ISB3 — — TBD mA 6, 9 Clock Running (Device Deselected, Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels) MCM63P733A–133 MCM63P733A–117 MCM63P733A–100 MCM63P733A–90 ISB4 — — TBD mA 3, 4, 5, 6, 8 Static Clock Running (Device Deselected, MCM63P733A–133 Freq = Max, VDD = Max, All Inputs MCM63P733A–117 Static at TTL Levels) MCM63P733A–100 MCM63P733A–90 ISB5 — — TBD mA 6, 9 AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD Only Sleep Mode Supply Current (Sleep Mode, Freq = Max, VDD = Max, All Other Inputs Static at CMOS Levels, ZZ ≥ VDD – 0.2 V) NOTES: 1. LBO pin has an internal pullup and will exhibit leakage currents of ± 5 µA. 2. ZZ pin has an internal pulldown and will exhibit leakage currents of ± 5 µA. 3. Reference AC Operating Conditions and Characteristics for input and timing. 4. All addresses transition simultaneously low (LSB) then high (MSB). 5. Data states are all zero. 6. Device is deselected as defined by the Truth Table. 7. Device in Sleep Mode as defined by the Asynchronous Truth Table. 8. CMOS levels for I/O’s are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V. 9. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Min Typ Max Unit Input Capacitance Cin — 4 5 pF Input/Output Capacitance CI/O — 7 8 pF MCM63P733A 8 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20 to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1 through 4) 63P733A–133 133 MHz 63P733A–117 117 MHz 63P733A–100 100 MHz 63P733A–90 90 MHz Symbol S b l Min Max Min Max Min Max Min Max Unit U i Cycle Time tKHKH 7.5 — 8.5 — 10 — 11 — ns Clock High Pulse Width tKHKL 3 — 3.4 — 4 — 4.4 — ns Clock Low Pulse Width tKLKH 3 — 3.4 — 4 — 4.4 — ns Clock Access Time tKHQV — 4 — 4.2 — 4.5 — 5 ns Output Enable to Output Valid tGLQV — 3.8 — 3.8 — 4.5 — 5 ns Clock High to Output Active tKHQX1 0 — 0 — 0 — 0 — ns 5, 6 Clock High to Output Change tKHQX2 1.5 — 1.5 — 1.5 — 1.5 — ns 6 Output Enable to Output Active tGLQX 0 — 0 — 0 — 0 — ns 5, 6 Output Disable to Q High–Z tGHQZ — 3.8 — 3.8 — 4.5 — 5 ns 5, 6 Clock High to Q High–Z tKHQZ 1.5 7.5 1.5 8.5 1.5 10 1.5 11 ns 5, 6 Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tADKH tADSKH tDVKH tWVKH tEVKH 2 — 2 — 2 — 2 — ns Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHEX 0.5 — 0.5 — 0.5 — 0.5 — ns Sleep Mode Standby tZZS — 2x tKHKH — 2x tKHKH — 2x tKHKH — 2x tKHKH ns Sleep Mode Recovery tZZREC 2x tKHKH — 2x tKHKH — 2x tKHKH — 2x tKHKH — ns Sleep Mode High to Q High–Z tZZQZ — 15 — 15 — 15 — 15 ns Parameter P Notes N NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 5. This parameter is sampled and not 100% tested. 6. Measured at ± 200 mV from steady state. MOTOROLA FAST SRAM MCM63P733A 9 OUTPUT Z0 = 50 Ω RL = 50 Ω 1.25 V Figure 2. AC Test Load 2400 OUTPUT CL CLOCK ACCESS TIME DELAY (ps) 2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 20 40 60 80 100 LUMPED CAPACITANCE, CL (pF) Figure 3. Lumped Capacitive Load and Typical Derating Curve MCM63P733A 10 MOTOROLA FAST SRAM 2.9 2.5 PULL–UP I (mA) MIN I (mA) MAX – 0.5 – 38 – 105 0 – 38 – 105 0.8 – 38 – 105 1.25 – 30 – 83 1.5 – 27 – 75 2.3 0 – 40 2.7 0 – 15 2.9 0 0 VOLTAGE (V) 2.3 VOLTAGE (V) 1.25 0.8 0 0 – 40 CURRENT (mA) – 105 – 80 – 40 CURRENT (mA) – 120 (a) Pull–Up for VDDQ = 2.5 V 3.6 3.135 2.8 VOLTAGE (V) I (mA) MIN I (mA) MAX – 0.5 – 40 – 120 0 – 40 – 120 1.4 – 40 – 120 1.65 – 37 – 108 2.0 – 28 – 81 3.135 0 – 20 3.6 0 0 VOLTAGE (V) PULL–UP 1.65 1.4 0 0 (b) Pull–Up: VDDQ = 3.3 V VDD PULL–DOWN I (mA) MIN I (mA) MAX – 0.5 0 0 0 0 0 0.4 10 20 0.8 20 40 1.25 31 63 1.6 40 80 2.8 40 80 3.2 40 80 3.4 40 80 1.6 VOLTAGE (V) VOLTAGE (V) 1.25 0.3 0 0 40 CURRENT (mA) 80 (c) Pull–Down Figure 4. Typical Output Buffer Characteristics MOTOROLA FAST SRAM MCM63P733A 11 MCM63P733A 12 MOTOROLA FAST SRAM Q(n) B SINGLE READ tKHQX1 A Q(A) Q(B) tKHQX2 t KHQV tKHKL NOTE: E low = SE2 high and SE3 low. W low = SGW low and / or SW and SBx low. DESELECTED tKHQZ DQx G W E SE1 ADV ADSC ADSP SA K tKHKH Q(B+2) BURST READ Q(B+1) tGHQZ Q(B+3) BURST WRAPS AROUND tKLKH Q(B) ADSP, SA SE2, SE3 IGNORED READ/WRITE CYCLES D(C) C D(C+2) BURST WRITE D(C+1) D(C+3) tGLQX D SINGLE READ Q(D) t KHQV NORMAL OPERATION tZZREC NO READS OR WRITES ALLOWED MOTOROLA FAST SRAM IDD ZZ DQ G W E ADV ADDR ADS K NORMAL OPERATION tZZS tZZQZ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ NOTE: ADS low = ADSC low or ADSP low. ADS high = both ADSC, ADSP high. E low = SE1 low, SE2 high, SE3 low. IZZ (max) specifications will not be met if inputs toggle. I ZZ IN SLEEP MODE NO NEW READS OR WRITES ALLOWED SLEEP MODE TIMING ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ MCM63P733A 13 APPLICATION INFORMATION SLEEP MODE may continue to run without impacting the RAMs sleep current (IZZ). All inputs are allowed to toggle — the RAM will not be selected and perform any reads or writes. However, if inputs toggle, the IZZ (max) specification will not be met. A sleep mode feature, the ZZ pin, has been implemented on the MCM63P733A. It allows the system designer to place the RAM in the lowest possible power condition by asserting ZZ. The sleep mode timing diagram shows the different modes of operation: Normal Operation, No READ/WRITE Allowed, and Sleep Mode. Each mode has its own set of constraints and conditions that are allowed. Normal Operation: All inputs must meet setup and hold times prior to sleep and t ZZREC nanoseconds after recovering from sleep. Clock (K) must also meet cycle, high, and low times during these periods. Two cycles prior to sleep, initiation of either a read or write operation is not allowed. No READ/WRITE: During the period of time just prior to sleep and during recovery from sleep, the assertion of either ADSC, ADSP, or any write signal is not allowed. If a write operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM can not be guaranteed immediately after ZZ is asserted (prior to being in sleep). Sleep Mode: The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock NON–BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for PowerPC — and other high end MPU–based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM63P733A. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figure 4. CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL) Non–Burst ADSP ADSC ADV SE1 SE2 LBO Sync Non–Burst, Pipelined SRAM H L H L H X NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low. K ADDR A B C D E F G H SE3 W G DQ Q(A) Q(C) Q(B) Q(D) D(E) D(F) READS D(G) D(H) WRITES Figure 5. Example Configuration as Non–Burst Synchronous SRAM ORDERING INFORMATION (Order by Full Part Number) MCM 63P733A XX X X Motorola Memory Prefix Blank = Trays, R = Tape and Reel Part Number Speed (133 = 133 MHz, 117 = 117 MHz, 100 = 100 MHz, 90 = 90 MHz) Package (TQ = TQFP) Full Part Numbers — MCM63P733ATQ133 MCM63P733ATQ133R MCM63P733A 14 MCM63P733ATQ117 MCM63P733ATQ100 MCM63P733ATQ90 MCM63P733ATQ117R MCM63P733ATQ100R MCM63P733ATQ90R MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQ PACKAGE 100–PIN TQFP CASE 983A–01 4X e 0.20 (0.008) H A–B D 2X 30 TIPS e/2 0.20 (0.008) C A–B D –D– 80 51 50 81 B E/2 –A– –X– B X=A, B, OR D –B– VIEW Y E1 E BASE METAL PLATING E1/2 31 100 1 b1 c 30 D1/2 ÇÇÇÇ ÉÉÉ ÇÇÇÇ ÉÉÉ c1 b D/2 D1 D 0.13 (0.005) M C A–B S D S SECTION B–B 2X 20 TIPS 0.20 (0.008) C A–B D A q 2 0.10 (0.004) C –H– –C– SEATING PLANE q 3 VIEW AB 0.05 (0.002) S S q 1 0.25 (0.010) R2 A2 A1 R1 L2 L L1 VIEW AB GAGE PLANE q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 q q q q MOTOROLA FAST SRAM 1 2 3 MILLIMETERS MIN MAX ––– 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 ––– 0.08 ––– 0.08 0.20 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX ––– 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 ––– 0.003 ––– 0.003 0.008 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ MCM63P733A 15 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 Mfax : [email protected] – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274 MCM63P733A 16 ◊ MOTOROLAMCM63P733A/D FAST SRAM