® ® ADS-944 14-Bit, 5MHz Sampling A/D Converters FEATURES • • • • • • • • • 14-bit resolution 5MHz minimum sampling rate No missing codes over full military temperature range Edge-triggered, no pipeline delay Low power, 2.95 Watts Small, 32-pin, ceramic TDIP package SMT package available Excellent dynamic performance MIL-STD-883 screening or DESC SMD available INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION The low-cost ADS-944 is a high-performance, 14-bit, 5MHz sampling A/D converter. This device accurately samples fullscale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-944 has been optimized to achieve a THD of –77dB and a SNR of 76dB. Packaged in a small, 32-pin TDIP, the functionally complete ADS-944 contains a fast-settling sample-hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing and control logic, three-state outputs, and errorcorrection circuitry. Digital input and output levels are TTL. Requiring ±15V, +5V and –5.2V supplies, the ADS-944 typically dissipates 2.95 Watts. The unit is offered with a bipolar input range of ±1.25V. Models are available for use in either commercial (0 to +70°C) or military (–55 to +125°C) operating temperature ranges. Typical applications include radar signal analysis, medical/graphic imaging, and FFT spectrum analysis. PIN FUNCTION PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +5V ANALOG SUPPLY –5.2V DIGITAL SUPPLY ANALOG INPUT ANALOG GROUND OFFSET ADJUST ANALOG GROUND GAIN ADJUST COMP. BITS OUTPUT ENABLE +5V DIGITAL SUPPLY ANALOG GROUND +15V SUPPLY –15V SUPPLY –5.2V ANALOG SUPPLY DIGITAL GROUND EOC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 START CONVERT BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 (LSB) 31 BIT 1 (MSB) BUFFER – 30 BIT 1 (MSB) FLASH ADC 1 + GAIN CIRCUIT GAIN ADJUST 7 REF DAC Σ OFFSET CIRCUIT OFFSET ADJUST 5 29 BIT 2 FLASH ADC 2 AMP 28 BIT 3 3-STATE OUTPUT REGISTER S/H DIGITAL CORRECTION LOGIC ANALOG INPUT 3 27 BIT 4 26 BIT 5 25 BIT 6 24 BIT 7 23 BIT 8 22 BIT 9 21 BIT 10 20 BIT 11 19 BIT 12 18 BIT 13 17 BIT 14 (LSB) START CONVERT 32 TIMING AND CONTROL LOGIC EOC 16 9 OUTPUT ENABLE 1 2 4, 6, 11 10 12 14 15 8 +5V ANALOG SUPPLY –5.2V DIGITAL SUPPLY ANALOG GROUND +5V DIGITAL SUPPLY +15V SUPPLY –5.2V ANALOG SUPPLY DIGITAL GROUND COMP. BITS Figure 1. ADS-944 Functional Block Diagram DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) • Tel: (508) 339-3000 Fax: (508) 339-6356 • For immediate assistance: (800) 233-2765 ® ® ADS-944 ABSOLUTE MAXIMUM RATINGS PARAMETERS +15V Supply (Pins 12) –15V Supply (Pin 13) +5V Supply (Pins 1, 10) –5V Supply (Pin 2, 14) Digital Input (Pin 8, 9, 32) Analog Input (Pin 3) Lead Temperature (10 seconds) PHYSICAL/ENVIRONMENTAL LIMITS UNITS 0 to +16 0 to –16 0 to +6 0 to –6 –0.3 to +VDD +0.3 –5 to +5 +300 Volts Volts Volts Volts Volts Volts °C PARAMETERS MIN. TYP. MAX. UNITS 0 –55 — — +70 +125 °C °C — — –65 7 21 — — — +150 °C/Watt °C/Watt °C Operating Temp. Range, Case ADS-944MC ADS-944MM/883 Thermal Impedance θjc θca Storage Temperature Range Package Type Weight 32-pin, metal-sealed, ceramic TDIP or SMT 0.46 ounces (13 grams) FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±VCC = ±15V, +VDD = +5V,Vdd = –5.2V, 5MHz sampling rate, and a minimum 3 minute warmup ➀ unless otherwise specified.) +25°C 0 to +70°C –55 to +125°C ANALOG INPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Input Voltage Range Input Resistance Input Capacitance — 500 — ±1.25 550 6 — — 15 — 500 — ±1.25 550 6 — — 15 — 500 — ±1.25 550 6 — — 15 Volts Ω pF +2.0 — — — 40 — — — — 80 — +0.8 +20 –20 — +2.0 — — — 40 — — — — 80 — +0.8 +20 –20 — +2.0 — — — 40 — — — — 80 — +0.8 +20 –20 — Volts Volts µA µA ns — — –0.95 — — — — 14 14 ±0.75 ±0.5 ±0.15 ±0.1 ±0.2 ±0.2 — — — +1.2 ±0.4 ±0.3 ±0.4 ±0.4 — — — –0.95 — — — — 14 14 ±0.75 ±0.5 ±0.15 ±0.1 ±0.2 ±0.2 — — — +1.2 ±0.4 ±0.3 ±0.4 ±0.4 — — — –0.95 — — — — 14 14 ±1.0 ±0.5 ±0.4 ±0.3 ±0.3 ±0.4 — — — +1.5 ±0.8 ±0.6 ±0.9 ±1.5 — Bits LSB LSB %FSR %FSR %FSR % Bits — — — –85 –78 –75 –77 –71 –70 — — — –85 –78 –75 –75 –70 –68 — — — –81 –75 –71 –71 –67 –61 dB dB dB — — — –82 –77 –73 –76 –70 –68 — — — –82 –77 –73 –74 –70 –65 — — — –78 –73 –70 –70 –65 –60 dB dB dB 73 73 73 76 76 75 — — — 73 73 73 76 76 75 — — — 71 71 71 75 75 75 — — — dB dB dB 71 70 68 — 75 73 71 135 — — — — 71 69 66 — 75 73 71 135 — — — — 68 65 62 — 73 71 69 135 — — — — dB dB dB µVrms — –82 — — –82 — — –82 — dB — — — — — — 20 13 90 ±110 +10 3 — — — — — — — — — — — — 20 13 90 ±110 +10 3 — — — — — — — — — — — — 20 13 90 ±110 +10 3 — — — — — — MHz MHz dB V/µs ns ps rms DIGITAL INPUT Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" ➁ Start Convert Positive Pulse Width ➂ STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 100kHz 100kHz to 1MHz 1MHz to 2.5MHz Total Harmonic Distortion (–0.5dB) dc to 100kHz 100kHz to 1MHz 1MHz to 2.5MHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 100kHz 100kHz to 1MHz 1MHz to 2.5MHz Signal-to-Noise Ratio ➃ (& distortion, –0.5dB) dc to 100kHz 100kHz to 1MHz 1MHz to 2.5MHz Noise Two-tone Intermodulation Distortion (fin = 2.45MHz, 1.975MHz, fs = 5MHz, –0.5dB) Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 2.5MHz) Slew Rate Aperture Delay Time Aperture Uncertainty 2 ® ® ADS-944 +25°C DYNAMIC PERFORMANCE cont. S/H Acquisition Time ( to ±0.003%FSR, 2.5V step) Overvoltage Recovery Time ➄ A/D Conversion Rate 0 to +70°C –55 to +125°C MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS — — 5 85 200 — 90 — — — — 5 85 200 — 90 — — — — 5 85 200 — 90 — — ns ns MHz +2.4 — — — — — — — — +0.4 –4 +4 +2.4 — — — — — — — — +0.4 –4 +4 +2.4 — — — — — — — — +0.4 –4 +4 Volts Volts mA mA — — 10 ns +14.25 –14.25 +4.75 –4.95 +15.0 –15.0 +5.0 –5.2 +15.75 –15.75 +5.25 –5.45 +14.25 –14.25 +4.75 –4.95 +15.0 –15.0 +5.0 –5.2 +15.75 –15.75 +5.25 –5.45 +14.25 –14.25 +4.9 –5.1 +15.0 –15.0 +5.0 –5.2 +15.75 –15.75 +5.25 –5.45 Volts Volts Volts Volts — — — — — — +36 –55 +155 –167 2.95 — +45 –65 +168 –175 3.3 ±0.05 — — — — — — +36 –55 +155 –167 2.95 — +45 –65 +168 –175 3.3 ±0.05 — — — — — — +36 –55 +155 –167 2.95 — +45 –65 +168 –175 3.3 ±0.05 mA mA mA mA Watts %FSR/%V DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Delay, Edge of ENABLE to Output Data Valid/Invalid Output Coding 10 — — 10 — — Offset Binary, Complementary Offset Binary, Two's Complement POWER REQUIREMENTS Power Supply Ranges ➅ +15V Supply –15V Supply +5V Supply –5V Supply Power Supply Currents ➆ +15V Supply –15V Supply +5V Supply –5.2V Supply Power Dissipation Power Supply Rejection Footnotes: ➀ All power supplies should be on before applying a start convert pulse. All supplies and the clock (start convert pulses) must be present during warmup periods. The device must be continuously converting during this time. ➄ This is the time required before the A/D output is valid after the analog input is back within its range. ➅ The minimum supply voltages of +4.9V and –5.1V for ±VDD are required for –55°C operations only. The minimum limits are +4.75V and –4.95V when operating at +125°C. ➁ When COMP. BITS (pin 8) is low, logic loading "0" will be –350µA for this pin. ➂ An 80ns wide start convert pulse is used for all production testing. The start convert pulse should be between 40 – 80ns or 130 – 160ns to ensure proper operations. The latter range could be used for those applications requiring less than a 5MHz sampling rate. ➃ Effective bits is equal to: (SNR + Distortion) – 1.76 + 20 log ➆ Typical +5V and –5.2V current drain breakdowns are as follows: +5VAnalog = +85mA +5VDigital = +70mA +5VTotal = +155mA –5.2VAnalog = –114mA –5.2VDigital = –53mA –5.2VTotal = –167mA Full Scale Amplitude Actual Input Amplitude 6.02 TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-944 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are not connected to each other internally. For optimal performance, tie all ground pins (4, 6, 11, and 15) directly to a large analog ground plane beneath the package. Bypass all power supplies to ground with 4.7µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. It is very important that the bypass capacitors be located as close to the unit as possible. Inductors or ferrite beads can also be used to improve the power supply filtering. Refer to Figure 4, the ADS-944 Evaluation Board Schematic, for more details. circuitry, or any similar offset and gain-calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain. 3. Pin 8 (COMP. BITS) selects the ADS-944's digital output coding. When a logic "1" is applied to pin 8, the output coding is complementary offset binary. When pin 8 has a logic "0" applied, the output coding becomes offset binary. The MSB output (pin 31) may be used under these conditions to achieve two's complement coding. Pin 8 is TTLcompatible and can be driven with digital logic for those who want dynamic control of its function. There is an internal pull-up resistor on this pin, allowing pin 8 to be either connected to +5V or left open when a logic "1" is needed. 2. The ADS-944 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this 4. To enable the three-state outputs, apply a logic "0" (low) to OUTPUT ENABLE (pin 9). To disable, apply a logic "1" (high) to pin 9. 3 ® ® ADS-944 TECHNICAL NOTES CONT. For the ADS-944, offset adjusting is normally accomplished at the point where the MSB is a 1 and all other output bits are 0's and the LSB just changes from a 0 to a 1. This digital output transition ideally occurs when the applied analog input is +½ LSB (+76.3µV). 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") initiates a new and inaccurate conversion cycle. Data for the interrupted and subsequent conversions will be invalid. Gain adjusting is accomplished when all bits are 1's and the LSB just changes from a 1 to a 0. This transition ideally occurs when the analog input is at +full scale minus 1½ LSB's (+1.249771) . 6. A passive bandpass filter is used at the input of the A/D for all production testing. 7. Though the ADS-944's digital outputs are capable of driving multiple LSTTL or HCT loads, we recommend the output bits and the EOC line each drive only a single gate. These gates should be located as close to the unit as possible. If they can not, 33Ω resistors placed in series with each output can aid in isolating pc run inductances. The ADS-944 digital outputs should not be connected directly to noisy digital busses. Note: Due to inherent system noise, the averaging of several conversions may be needed to accurately adjust both offset and gain to 1LSB of accuracy. Zero/Offset Adjust Procedure 1. Apply a train of pulses to the START CONVERT input (pin 32) so the converter is continuously converting. 8. Do not enable/disable or complement the output bits during the conversion process (from the falling edge of START CONVERT to the falling edge of EOC). 2. Apply +76.3µV to the ANALOG INPUT (pin 3). 3. Adjust the offset potentiometer until the output bits are 10 0000 0000 0000 and the LSB flickers between 0 and 1 with pin 8 tied low (offset binary) or between 01 1111 1111 1111 and 01 1111 1111 1110 with pin 8 tied high (complementary offset binary). CALIBRATION PROCEDURE (Refer to Figure 2 and Table 1) Note: Connect pin 5 to ANALOG GROUND (pin 6) for operation without zero/offset adjustment. Connect pin 7 to ANALOG GROUND (pin 6) for operation without gain adjustment. 4. Two's complement coding requires using BIT 1 (MSB) (pin 31). With pin 8 tied low, adjust the trimpot until the code flickers between 00 0000 0000 0000 and 00 0000 0000 0001. Any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. To avoid interaction, offset must be adjusted before gain. The ranges of adjustment for the circuit in Figure 2 are guaranteed to compensate for the ADS-944's initial accuracy errors and may not be able to compensate for additional system errors. Gain Adjust Procedure 1. Apply +1.249771V to the ANALOG INPUT (pin 3). 2. Adjust the gain potentiometer until all output bits are 1's and the LSB flickers between 1 and 0 with pin 8 tied low (offset binary) or until all bits are 0's and the LSB flickers between 1 and 0 with pin 8 tied high (complementary offset binary). A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This can be accomplished by connecting LED's to the digital outputs and adjusting until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. 3. Two's complement coding requires using pin 31. With pin 8 tied low, adjust the gain trimpot until the output code flickers equally between 01 1111 1111 1110 and 01 1111 1111 1111. 4. To confirm proper operation of the device, vary the applied input voltage to obtain the output coding listed in Table 1. 31 BIT 1 (MSB) 10 DIGITAL SUPPLY + +5V 4.7µF 28 BIT 3 15 27 BIT 4 26 BIT 5 + 0.1µF 30 BIT 1 (MSB) 29 BIT 2 4.7µF 0.1µF –5.2V 4.7µF 25 BIT 6 24 BIT 7 23 BIT 8 22 BIT 9 21 BIT 10 1 ANALOG SUPPLY + +5V 2 DIGITAL SUPPLY 4, 6 20 BIT 11 19 BIT 12 + 0.1µF 4.7µF 0.1µF –5.2V 4.7µF 18 BIT 13 17 BIT 14 (LSB) 7 OVERFLOW ADS-944 12 + +15V ANALOG 14 SUPPLY 16 EOC 9 OUTPUT ENABLE 11 3 ANALOG INPUT + 0.1µF 4.7µF 13 –15V START CONVERT 32 COMP. BITS 2 GAIN ADJUST 7 +15V +15V OFFSET 5 ADJUST 20kΩ –15V 0.1µF 20kΩ 0.1µF –15V 4 Figure 2. ADS-944 Connection Diagram ® ® ADS-944 Table 1. Output Coding MSB LSB 11 1111 1111 1111 11 1000 0000 0000 11 0000 0000 0000 10 0000 0000 0000 01 0000 0000 0000 00 1000 0000 0000 00 0000 0000 0001 00 0000 0000 0000 OFF. BINARY OUTPUT CODING MSB LSB MSB 00 0000 0000 0000 00 1111 1111 1111 00 1111 1111 1111 01 1111 1111 1111 10 1111 1111 1111 11 0111 1111 1111 11 1111 1111 1110 11 1111 1111 1111 COMP. OFF. BIN. LSB INPUT RANGE ±1.25V BIPOLAR SCALE +1.249847 +0.937500 +0.625000 0.000000 –0.625000 –0.937500 –1.249847 –1.250000 +FS –1 LSB +3/4 FS +1/2FS 0 –1/2FS –3/4FS –FS +1 LSB –FS 01 1111 1111 1111 01 1000 0000 0000 01 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000 10 1000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 TWO'S COMP. TIMING THERMAL REQUIREMENTS The ADS-944 is an edge-triggered device. A conversion is initiated by the rising edge of the start convert pulse and no additional external timing signals are required. The device does not employ "pipeline" delays to increase its throughput rate. It does not require multiple start convert pulses to bring valid digital data to its output pins. All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70°C and –55 to +125°C. All room-temperature (TA = +25°C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. Approximately 10ns after the rising edge of the start convert signal, the ADS-944's internal sample-hold amplifier is driven into the hold mode by the internal S/H control line. After a 35ns delay to allow for S/H output transient settling, the conversion process begins, and the EOC line (pin 16) is driven high. The complete A/D conversion requires approximately 150ns. The falling of EOC signals that the conversion is now complete and digital output data is now valid. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically-insulating, thermally-conductive "pads" may be installed underneath the package. Devices should be soldered to boards rather than "socketed", and of course, minimal air flow over the surface can greatly help reduce the package temperature. This device actually guarantees that digital output data will be valid for 10ns prior to the falling edge of EOC. Therefore, EOC can be used to latch data into external registers that have appropriate setup times. Any other available timing edges, including a delayed EOC or the rising edge of the next EOC pulse, can also be used for this purpose. In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL's HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters", or contact DATEL directly, for additional information. The falling edge of the start convert pulse, though irrelevant to device timing, can cause conversion errors if it occurs at certain times. Therefore, the recommended start convert pulse width is between 40 and 80ns or between 130 and 160ns. DATEL performs ADS-944 production testing at the full 5MHz sampling rate using 80ns start convert pulses. ➀ START CONVERT N N+1 80ns typ. Acquisition Time 10ns typ. INTERNAL S/H 115ns typ. Hold 90ns max. Hold 60ns typ., ±10ns 35ns typ. Conversion Time EOC 150ns typ., 160ns max. 50ns typ., 60ns max. OUTPUT DATA INVALID DATA 140ns min., 150ns typ. DATA N VALID DATA (N-1) VALID Note: Scale is approximately 10ns per division. ➀ START CONVERT pulse width: 40 to 80ns or 130 to 160ns. Figure 3. ADS-944 Timing Diagram 5 ® ® ADS-944 THD vs. Input Frequency 90 80 80 70 70 60 60 THD (–dB) Peak Harmonic (–dB) PH vs. Input Frequency 90 50 40 50 40 30 30 20 20 10 10 0 0 1 10 100 1000 10000 1 10 Frequency (kHz) SNR vs. Input Frequency 1000 10000 1000 10000 SNR+D vs. Input Frequency 80 80 70 70 60 60 SNR+D (dB) SNR (dB) 100 Frequency (kHz) 50 40 30 50 40 30 20 20 10 10 0 0 1 10 100 1000 10000 1 10 Frequency (kHz) 100 Frequency (kHz) Figure 4. Typical ADS-944 Dynamic Performance vs. Input Frequency at +25°C +0.33 0 DNL (LSB's) –20 –30 0 –40 –50 –60 Number of Occurences Amplitude Relative to Full Scale (dB) –10 –70 –80 –90 –100 –110 –120 –0.55 0 Digital Output Code 16,384 –130 –140 0 250 kHz 500 kHz 750 kHz 1 MHz 1.25 MHz 1.5 MHz 1.75 MHz 2.0 MHz 2.25 MHz 2.5 MHz Frequency (fin = 2.45MHz, fs = 5MHz, Vin = –0.5dB, 16,384 points) 0 Figure 5. ADS-944 FFT Digital Output Code 16,384 Figure 6. ADS-944 Histogram and Differential Nonlinearity 6 P4 ANALOG IN SG10 SG3 SG2 SG1 26 24 22 20 18 16 14 12 10 8 6 4 2 P2 25 23 21 19 17 15 13 11 9 7 5 3 1 20MHY L7 20MHY L6 20MHY L5 20MHY L4 20MHY L3 20MHY L2 20MHY L1 C7 2.2MFD C6 2.2MFD C14 0.01MFD 0.01MFD C13 C12 0.01MFD -15V C5 2.2MFD +5VA +15V C11 -5VA 0.01MFD C10 0.01MFD +5V C9 0.01MFD -5V C4 2.2MFD C3 2.2MFD C2 2.2MFD C1 2.2MFD C8 0.01MFD +5VF R3 OFFSET GAIN 3 +15V + – 2 2. CLOSE SG1-SG3, SG9, SG10. -15V -15V 1 SG8 CLC402 HI2541 OPTION 10 SG6 +5VA C20 0.1MFD -15V C21 0.1MFD 20K R2 2 1 20K R1 -5VA 6 U4 11 +15V SG7 5 4 3 +15V OPTION SG5 OPTION 1. UNLESS OTHERWISE SPECIFIED ALL CAPACITORS ARE 50V. C1 - C6 ARE 20V. ALL RESISTORS ARE IN OHMS. NOTES: ANA. IN + + + + + + 7 + 1 COMP ANA. IN SG4 C27 0.1MFD + 7 14 8 -5V -15V -5VA C24 0.1MFD 15PF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +5VA -5V AIN GNDA OFF GNDA GAIN COMP ENA +5V GNDA +15V -15V -5VA GNDD EOC ST BIT1 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BIT10 BIT11 BIT12 BIT13 BIT14 U1 ADS-944 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 START CONV. C25 + U6 HCT7474 14 2.2MFD 4 PR +5V JPR3 2 5 Q D 1 3 3 6 2 CK Q 1 CLR R4 7 GND 3.2K C26 +15V +5V +5VA C28 2.2MFD X1 5MHZ SG9 +5VF +5VF 9 10 8 U5 74HCT86 U5 2 1 P3 START CONV. Figure 7. ADS-944 Evaluation Board Schematic JPR1 3 2 C19 0.1MFD OPTION C18 0.1MFD OPTION + C16 0.1MFD 2.2MFD C23 74HCT86 3 C22 2.2MFD + C17 0.1MFD GND 10 20 2 1D +5V Q1 3 2D Q2 4 3D Q3 5 4D Q4 6 U2 5D Q5 7 74HCT 6D 573 Q6 8 7D Q7 9 Q8 8D 11 LE OE GND 10 19 18 17 16 15 14 13 12 1 +5VF 20 2 19 1D +5V Q1 3 18 2D Q2 17 4 3D Q3 5 16 4D Q4 6 15 U3 5D Q5 14 7 74HCT 6D 573 Q6 8 13 7D Q7 9 12 Q8 8D 11 1 LE OE +5VF 1 JPR4 2 3 (MSB) B1 (MSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 (LSB) B14 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 P1 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 ® ® ADS-944 ® ® ADS-944 MECHANICAL DIMENSIONS INCHES (mm) 1.72 MAX. (43.69) 32 Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) 17 Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 1.11 MAX. (28.19) 1 0.235 MAX. (5.969) 16 0.100 TYP. (2.540) 1.500 (38.100) 0.200 MAX. (5.080) +0.002 0.010 –0.001 (0.254) 0.190 MAX. (4.826) 0.018 ±0.002 (0.457) SEATING PLANE 0.025 (0.635) 0.100 (2.540) 0.040 (1.016) 9000 0.900 ±0.010 (22.860) 0.100 (2.540) The histogram in Figure 8 represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-944. 16.384 conversions were processed with the input to the ADS-944 tied to analog ground. 8000 7000 ORDERING INFORMATION Occurences 6000 MODEL NUMBER 5000 ADS-944MC ADS-944MM ADS-944/883 4000 OPERATING TEMP. RANGE 0 to +70°C –55 to +125°C –55 to +125°C Contact DATEL for availability of surface-mount (J-lead) packaging or for MIL-STD-883 or DESC SMD product specifications. 3000 ACCESSORIES 2000 ADS-B944 HS-32 1000 Evaluation Board (without ADS-944) Heat sink for ADS-944 DDIP models Receptacles for PC board mounting can be ordered through AMP Inc., Part # 3-331272-8 (Component Lead Socket), 24 required. 0 Digital Output Code Figure 8. ADS-944 Grounded Input Histogram ISO 9001 R DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com E-mail:[email protected] Data Sheet Fax Back: (508) 261-2857 E G I S T E R E D DS-0240B 6/97 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH München, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.